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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
23 | */ |
24 | ||
25 | #include "hw.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "usb.h" | |
28 | #include "pci.h" | |
29 | #include "monitor.h" | |
439a97cc | 30 | #include "trace.h" |
0ce668bc | 31 | #include "dma.h" |
94527ead GH |
32 | |
33 | #define EHCI_DEBUG 0 | |
94527ead | 34 | |
26d53979 | 35 | #if EHCI_DEBUG |
94527ead GH |
36 | #define DPRINTF printf |
37 | #else | |
38 | #define DPRINTF(...) | |
39 | #endif | |
40 | ||
94527ead GH |
41 | /* internal processing - reset HC to try and recover */ |
42 | #define USB_RET_PROCERR (-99) | |
43 | ||
44 | #define MMIO_SIZE 0x1000 | |
45 | ||
46 | /* Capability Registers Base Address - section 2.2 */ | |
47 | #define CAPREGBASE 0x0000 | |
48 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
49 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
50 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
51 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
52 | #define EECP HCCPARAMS + 1 | |
53 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
54 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
55 | ||
56 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
57 | ||
58 | #define USBCMD OPREGBASE + 0x0000 | |
59 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
60 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
61 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
62 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
63 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
64 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
65 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
66 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
67 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
68 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
69 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
70 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
71 | ||
72 | #define USBSTS OPREGBASE + 0x0004 | |
73 | #define USBSTS_RO_MASK 0x0000003f | |
74 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
75 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
76 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
77 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
78 | #define USBSTS_HSE (1 << 4) // Host System Error | |
79 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
80 | #define USBSTS_HALT (1 << 12) // HC Halted | |
81 | #define USBSTS_REC (1 << 13) // Reclamation | |
82 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
83 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
84 | ||
85 | /* | |
86 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
87 | * so no need to redefine here. | |
88 | */ | |
89 | #define USBINTR OPREGBASE + 0x0008 | |
90 | #define USBINTR_MASK 0x0000003f | |
91 | ||
92 | #define FRINDEX OPREGBASE + 0x000c | |
93 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
94 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
95 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
96 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
97 | ||
98 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
99 | ||
100 | #define PORTSC (OPREGBASE + 0x0044) | |
101 | #define PORTSC_BEGIN PORTSC | |
102 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
103 | /* | |
c44fd61c | 104 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
105 | * written to us by software |
106 | */ | |
a0a3167a | 107 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
108 | #define PORTSC_RWC_MASK 0x0000002a |
109 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
110 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
111 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
112 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
113 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
114 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
115 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
116 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
117 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
118 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
119 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
120 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
121 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
122 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
123 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
124 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
125 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
126 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
127 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
128 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
129 | ||
130 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 131 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
132 | |
133 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 134 | #define NB_PORTS 6 // Number of downstream ports |
94527ead GH |
135 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
136 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
137 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
138 | ||
139 | /* Internal periodic / asynchronous schedule state machine states | |
140 | */ | |
141 | typedef enum { | |
142 | EST_INACTIVE = 1000, | |
143 | EST_ACTIVE, | |
144 | EST_EXECUTING, | |
145 | EST_SLEEPING, | |
146 | /* The following states are internal to the state machine function | |
147 | */ | |
148 | EST_WAITLISTHEAD, | |
149 | EST_FETCHENTRY, | |
150 | EST_FETCHQH, | |
151 | EST_FETCHITD, | |
2fe80192 | 152 | EST_FETCHSITD, |
94527ead GH |
153 | EST_ADVANCEQUEUE, |
154 | EST_FETCHQTD, | |
155 | EST_EXECUTE, | |
156 | EST_WRITEBACK, | |
157 | EST_HORIZONTALQH | |
158 | } EHCI_STATES; | |
159 | ||
160 | /* macros for accessing fields within next link pointer entry */ | |
161 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
162 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
163 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
164 | ||
165 | /* link pointer types */ | |
166 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
167 | #define NLPTR_TYPE_QH 1 // queue head | |
168 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
169 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
170 | ||
171 | ||
172 | /* EHCI spec version 1.0 Section 3.3 | |
173 | */ | |
174 | typedef struct EHCIitd { | |
175 | uint32_t next; | |
176 | ||
177 | uint32_t transact[8]; | |
178 | #define ITD_XACT_ACTIVE (1 << 31) | |
179 | #define ITD_XACT_DBERROR (1 << 30) | |
180 | #define ITD_XACT_BABBLE (1 << 29) | |
181 | #define ITD_XACT_XACTERR (1 << 28) | |
182 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
183 | #define ITD_XACT_LENGTH_SH 16 | |
184 | #define ITD_XACT_IOC (1 << 15) | |
185 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
186 | #define ITD_XACT_PGSEL_SH 12 | |
187 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
188 | ||
189 | uint32_t bufptr[7]; | |
190 | #define ITD_BUFPTR_MASK 0xfffff000 | |
191 | #define ITD_BUFPTR_SH 12 | |
192 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
193 | #define ITD_BUFPTR_EP_SH 8 | |
194 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
195 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
196 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
197 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
198 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
199 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 200 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
201 | } EHCIitd; |
202 | ||
203 | /* EHCI spec version 1.0 Section 3.4 | |
204 | */ | |
205 | typedef struct EHCIsitd { | |
206 | uint32_t next; // Standard next link pointer | |
207 | uint32_t epchar; | |
208 | #define SITD_EPCHAR_IO (1 << 31) | |
209 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
210 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
211 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
212 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
213 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
214 | #define SITD_EPCHAR_EPNUM_SH 8 | |
215 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
216 | ||
217 | uint32_t uframe; | |
218 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
219 | #define SITD_UFRAME_CMASK_SH 8 | |
220 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
221 | ||
222 | uint32_t results; | |
223 | #define SITD_RESULTS_IOC (1 << 31) | |
224 | #define SITD_RESULTS_PGSEL (1 << 30) | |
225 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
226 | #define SITD_RESULTS_TYBYTES_SH 16 | |
227 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
228 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
229 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
230 | #define SITD_RESULTS_ERR (1 << 6) | |
231 | #define SITD_RESULTS_DBERR (1 << 5) | |
232 | #define SITD_RESULTS_BABBLE (1 << 4) | |
233 | #define SITD_RESULTS_XACTERR (1 << 3) | |
234 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
235 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
236 | ||
237 | uint32_t bufptr[2]; | |
238 | #define SITD_BUFPTR_MASK 0xfffff000 | |
239 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
240 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
241 | #define SITD_BUFPTR_TPOS_SH 3 | |
242 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
243 | ||
244 | uint32_t backptr; // Standard next link pointer | |
245 | } EHCIsitd; | |
246 | ||
247 | /* EHCI spec version 1.0 Section 3.5 | |
248 | */ | |
249 | typedef struct EHCIqtd { | |
250 | uint32_t next; // Standard next link pointer | |
251 | uint32_t altnext; // Standard next link pointer | |
252 | uint32_t token; | |
253 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
254 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
255 | #define QTD_TOKEN_TBYTES_SH 16 | |
256 | #define QTD_TOKEN_IOC (1 << 15) | |
257 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
258 | #define QTD_TOKEN_CPAGE_SH 12 | |
259 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
260 | #define QTD_TOKEN_CERR_SH 10 | |
261 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
262 | #define QTD_TOKEN_PID_SH 8 | |
263 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
264 | #define QTD_TOKEN_HALT (1 << 6) | |
265 | #define QTD_TOKEN_DBERR (1 << 5) | |
266 | #define QTD_TOKEN_BABBLE (1 << 4) | |
267 | #define QTD_TOKEN_XACTERR (1 << 3) | |
268 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
269 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
270 | #define QTD_TOKEN_PING (1 << 0) | |
271 | ||
272 | uint32_t bufptr[5]; // Standard buffer pointer | |
273 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 274 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
275 | } EHCIqtd; |
276 | ||
277 | /* EHCI spec version 1.0 Section 3.6 | |
278 | */ | |
279 | typedef struct EHCIqh { | |
280 | uint32_t next; // Standard next link pointer | |
281 | ||
282 | /* endpoint characteristics */ | |
283 | uint32_t epchar; | |
284 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
285 | #define QH_EPCHAR_RL_SH 28 | |
286 | #define QH_EPCHAR_C (1 << 27) | |
287 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
288 | #define QH_EPCHAR_MPLEN_SH 16 | |
289 | #define QH_EPCHAR_H (1 << 15) | |
290 | #define QH_EPCHAR_DTC (1 << 14) | |
291 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
292 | #define QH_EPCHAR_EPS_SH 12 | |
293 | #define EHCI_QH_EPS_FULL 0 | |
294 | #define EHCI_QH_EPS_LOW 1 | |
295 | #define EHCI_QH_EPS_HIGH 2 | |
296 | #define EHCI_QH_EPS_RESERVED 3 | |
297 | ||
298 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
299 | #define QH_EPCHAR_EP_SH 8 | |
300 | #define QH_EPCHAR_I (1 << 7) | |
301 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
302 | #define QH_EPCHAR_DEVADDR_SH 0 | |
303 | ||
304 | /* endpoint capabilities */ | |
305 | uint32_t epcap; | |
306 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
307 | #define QH_EPCAP_MULT_SH 30 | |
308 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
309 | #define QH_EPCAP_PORTNUM_SH 23 | |
310 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
311 | #define QH_EPCAP_HUBADDR_SH 16 | |
312 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
313 | #define QH_EPCAP_CMASK_SH 8 | |
314 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
315 | #define QH_EPCAP_SMASK_SH 0 | |
316 | ||
317 | uint32_t current_qtd; // Standard next link pointer | |
318 | uint32_t next_qtd; // Standard next link pointer | |
319 | uint32_t altnext_qtd; | |
320 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
321 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
322 | ||
323 | uint32_t token; // Same as QTD token | |
324 | uint32_t bufptr[5]; // Standard buffer pointer | |
325 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
326 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
327 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
328 | #define BUFPTR_SBYTES_SH 5 | |
329 | } EHCIqh; | |
330 | ||
331 | /* EHCI spec version 1.0 Section 3.7 | |
332 | */ | |
333 | typedef struct EHCIfstn { | |
334 | uint32_t next; // Standard next link pointer | |
335 | uint32_t backptr; // Standard next link pointer | |
336 | } EHCIfstn; | |
337 | ||
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
347 | struct EHCIQueue { | |
348 | EHCIState *ehci; | |
8ac6d699 GH |
349 | QTAILQ_ENTRY(EHCIQueue) next; |
350 | bool async_schedule; | |
adddecb1 GH |
351 | uint32_t seen; |
352 | uint64_t ts; | |
0122f472 GH |
353 | |
354 | /* cached data from guest - needs to be flushed | |
355 | * when guest removes an entry (doorbell, handshake sequence) | |
356 | */ | |
357 | EHCIqh qh; // copy of current QH (being worked on) | |
358 | uint32_t qhaddr; // address QH read from | |
359 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
360 | uint32_t qtdaddr; // address QTD read from | |
361 | ||
362 | USBPacket packet; | |
0ce668bc | 363 | QEMUSGList sgl; |
0122f472 GH |
364 | int pid; |
365 | uint32_t tbytes; | |
366 | enum async_state async; | |
367 | int usb_status; | |
368 | }; | |
369 | ||
370 | struct EHCIState { | |
94527ead | 371 | PCIDevice dev; |
0122f472 | 372 | USBBus bus; |
94527ead | 373 | qemu_irq irq; |
e57964f5 | 374 | MemoryRegion mem; |
a0a3167a | 375 | int companion_count; |
16a2dee6 GH |
376 | |
377 | /* properties */ | |
378 | uint32_t freq; | |
379 | uint32_t maxframes; | |
380 | ||
94527ead GH |
381 | /* |
382 | * EHCI spec version 1.0 Section 2.3 | |
383 | * Host Controller Operational Registers | |
384 | */ | |
385 | union { | |
386 | uint8_t mmio[MMIO_SIZE]; | |
387 | struct { | |
388 | uint8_t cap[OPREGBASE]; | |
389 | uint32_t usbcmd; | |
390 | uint32_t usbsts; | |
391 | uint32_t usbintr; | |
392 | uint32_t frindex; | |
393 | uint32_t ctrldssegment; | |
394 | uint32_t periodiclistbase; | |
395 | uint32_t asynclistaddr; | |
396 | uint32_t notused[9]; | |
397 | uint32_t configflag; | |
398 | uint32_t portsc[NB_PORTS]; | |
399 | }; | |
400 | }; | |
0122f472 | 401 | |
94527ead GH |
402 | /* |
403 | * Internal states, shadow registers, etc | |
404 | */ | |
405 | uint32_t sofv; | |
406 | QEMUTimer *frame_timer; | |
407 | int attach_poll_counter; | |
408 | int astate; // Current state in asynchronous schedule | |
409 | int pstate; // Current state in periodic schedule | |
410 | USBPort ports[NB_PORTS]; | |
a0a3167a | 411 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 412 | uint32_t usbsts_pending; |
8ac6d699 | 413 | QTAILQ_HEAD(, EHCIQueue) queues; |
94527ead | 414 | |
0122f472 GH |
415 | uint32_t a_fetch_addr; // which address to look at next |
416 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 417 | |
0122f472 | 418 | USBPacket ipacket; |
0ce668bc | 419 | QEMUSGList isgl; |
94527ead | 420 | int isoch_pause; |
0122f472 | 421 | |
adddecb1 | 422 | uint64_t last_run_ns; |
0122f472 | 423 | }; |
94527ead GH |
424 | |
425 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 426 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
427 | |
428 | /* nifty macros from Arnon's EHCI version */ | |
429 | #define get_field(data, field) \ | |
430 | (((data) & field##_MASK) >> field##_SH) | |
431 | ||
432 | #define set_field(data, newval, field) do { \ | |
433 | uint32_t val = *data; \ | |
434 | val &= ~ field##_MASK; \ | |
435 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
436 | *data = val; \ | |
437 | } while(0) | |
438 | ||
26d53979 | 439 | static const char *ehci_state_names[] = { |
aac882e7 GH |
440 | [EST_INACTIVE] = "INACTIVE", |
441 | [EST_ACTIVE] = "ACTIVE", | |
442 | [EST_EXECUTING] = "EXECUTING", | |
443 | [EST_SLEEPING] = "SLEEPING", | |
444 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
445 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
446 | [EST_FETCHQH] = "FETCH QH", | |
447 | [EST_FETCHITD] = "FETCH ITD", | |
448 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
449 | [EST_FETCHQTD] = "FETCH QTD", | |
450 | [EST_EXECUTE] = "EXECUTE", | |
451 | [EST_WRITEBACK] = "WRITEBACK", | |
452 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
453 | }; |
454 | ||
455 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
456 | [CAPLENGTH] = "CAPLENGTH", |
457 | [HCIVERSION] = "HCIVERSION", | |
458 | [HCSPARAMS] = "HCSPARAMS", | |
459 | [HCCPARAMS] = "HCCPARAMS", | |
460 | [USBCMD] = "USBCMD", | |
461 | [USBSTS] = "USBSTS", | |
462 | [USBINTR] = "USBINTR", | |
463 | [FRINDEX] = "FRINDEX", | |
464 | [PERIODICLISTBASE] = "P-LIST BASE", | |
465 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
466 | [PORTSC_BEGIN] = "PORTSC #0", | |
467 | [PORTSC_BEGIN + 4] = "PORTSC #1", | |
468 | [PORTSC_BEGIN + 8] = "PORTSC #2", | |
469 | [PORTSC_BEGIN + 12] = "PORTSC #3", | |
335b8d20 GH |
470 | [PORTSC_BEGIN + 16] = "PORTSC #4", |
471 | [PORTSC_BEGIN + 20] = "PORTSC #5", | |
aac882e7 | 472 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 473 | }; |
94527ead | 474 | |
26d53979 | 475 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 476 | { |
26d53979 GH |
477 | if (nr < len && n[nr] != NULL) { |
478 | return n[nr]; | |
94527ead | 479 | } else { |
26d53979 | 480 | return "unknown"; |
94527ead GH |
481 | } |
482 | } | |
94527ead | 483 | |
26d53979 GH |
484 | static const char *state2str(uint32_t state) |
485 | { | |
486 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
487 | } | |
488 | ||
489 | static const char *addr2str(target_phys_addr_t addr) | |
490 | { | |
491 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
492 | } | |
493 | ||
439a97cc GH |
494 | static void ehci_trace_usbsts(uint32_t mask, int state) |
495 | { | |
496 | /* interrupts */ | |
497 | if (mask & USBSTS_INT) { | |
498 | trace_usb_ehci_usbsts("INT", state); | |
499 | } | |
500 | if (mask & USBSTS_ERRINT) { | |
501 | trace_usb_ehci_usbsts("ERRINT", state); | |
502 | } | |
503 | if (mask & USBSTS_PCD) { | |
504 | trace_usb_ehci_usbsts("PCD", state); | |
505 | } | |
506 | if (mask & USBSTS_FLR) { | |
507 | trace_usb_ehci_usbsts("FLR", state); | |
508 | } | |
509 | if (mask & USBSTS_HSE) { | |
510 | trace_usb_ehci_usbsts("HSE", state); | |
511 | } | |
512 | if (mask & USBSTS_IAA) { | |
513 | trace_usb_ehci_usbsts("IAA", state); | |
514 | } | |
515 | ||
516 | /* status */ | |
517 | if (mask & USBSTS_HALT) { | |
518 | trace_usb_ehci_usbsts("HALT", state); | |
519 | } | |
520 | if (mask & USBSTS_REC) { | |
521 | trace_usb_ehci_usbsts("REC", state); | |
522 | } | |
523 | if (mask & USBSTS_PSS) { | |
524 | trace_usb_ehci_usbsts("PSS", state); | |
525 | } | |
526 | if (mask & USBSTS_ASS) { | |
527 | trace_usb_ehci_usbsts("ASS", state); | |
528 | } | |
529 | } | |
530 | ||
531 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
532 | { | |
533 | if ((s->usbsts & mask) == mask) { | |
534 | return; | |
535 | } | |
536 | ehci_trace_usbsts(mask, 1); | |
537 | s->usbsts |= mask; | |
538 | } | |
539 | ||
540 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
541 | { | |
542 | if ((s->usbsts & mask) == 0) { | |
543 | return; | |
544 | } | |
545 | ehci_trace_usbsts(mask, 0); | |
546 | s->usbsts &= ~mask; | |
547 | } | |
94527ead GH |
548 | |
549 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
550 | { | |
551 | int level = 0; | |
552 | ||
553 | // TODO honour interrupt threshold requests | |
554 | ||
439a97cc | 555 | ehci_set_usbsts(s, intr); |
94527ead GH |
556 | |
557 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
558 | level = 1; | |
559 | } | |
560 | ||
561 | qemu_set_irq(s->irq, level); | |
562 | } | |
563 | ||
564 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
565 | { | |
566 | s->usbsts_pending |= intr; | |
567 | } | |
568 | ||
569 | static inline void ehci_commit_interrupt(EHCIState *s) | |
570 | { | |
571 | if (!s->usbsts_pending) { | |
572 | return; | |
573 | } | |
574 | ehci_set_interrupt(s, s->usbsts_pending); | |
575 | s->usbsts_pending = 0; | |
576 | } | |
577 | ||
26d53979 GH |
578 | static void ehci_set_state(EHCIState *s, int async, int state) |
579 | { | |
580 | if (async) { | |
581 | trace_usb_ehci_state("async", state2str(state)); | |
582 | s->astate = state; | |
583 | } else { | |
584 | trace_usb_ehci_state("periodic", state2str(state)); | |
585 | s->pstate = state; | |
586 | } | |
587 | } | |
588 | ||
589 | static int ehci_get_state(EHCIState *s, int async) | |
590 | { | |
591 | return async ? s->astate : s->pstate; | |
592 | } | |
593 | ||
0122f472 GH |
594 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
595 | { | |
596 | if (async) { | |
597 | s->a_fetch_addr = addr; | |
598 | } else { | |
599 | s->p_fetch_addr = addr; | |
600 | } | |
601 | } | |
602 | ||
603 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
604 | { | |
605 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
606 | } | |
607 | ||
8ac6d699 | 608 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 609 | { |
025b168c GH |
610 | /* need three here due to argument count limits */ |
611 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
612 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
613 | trace_usb_ehci_qh_fields(addr, | |
614 | get_field(qh->epchar, QH_EPCHAR_RL), | |
615 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
616 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
617 | get_field(qh->epchar, QH_EPCHAR_EP), | |
618 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
619 | trace_usb_ehci_qh_bits(addr, | |
620 | (bool)(qh->epchar & QH_EPCHAR_C), | |
621 | (bool)(qh->epchar & QH_EPCHAR_H), | |
622 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
623 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
624 | } |
625 | ||
8ac6d699 | 626 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 627 | { |
025b168c GH |
628 | /* need three here due to argument count limits */ |
629 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
630 | trace_usb_ehci_qtd_fields(addr, | |
631 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
632 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
633 | get_field(qtd->token, QTD_TOKEN_CERR), | |
634 | get_field(qtd->token, QTD_TOKEN_PID)); | |
635 | trace_usb_ehci_qtd_bits(addr, | |
636 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
637 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
638 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
639 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
640 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
641 | } |
642 | ||
643 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
644 | { | |
e654887f GH |
645 | trace_usb_ehci_itd(addr, itd->next, |
646 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
647 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
648 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
649 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
650 | } |
651 | ||
2fe80192 GH |
652 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
653 | EHCIsitd *sitd) | |
654 | { | |
655 | trace_usb_ehci_sitd(addr, sitd->next, | |
656 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
657 | } | |
658 | ||
8ac6d699 GH |
659 | /* queue management */ |
660 | ||
661 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
662 | { | |
663 | EHCIQueue *q; | |
664 | ||
7267c094 | 665 | q = g_malloc0(sizeof(*q)); |
8ac6d699 GH |
666 | q->ehci = ehci; |
667 | q->async_schedule = async; | |
668 | QTAILQ_INSERT_HEAD(&ehci->queues, q, next); | |
669 | trace_usb_ehci_queue_action(q, "alloc"); | |
670 | return q; | |
671 | } | |
672 | ||
673 | static void ehci_free_queue(EHCIQueue *q) | |
674 | { | |
675 | trace_usb_ehci_queue_action(q, "free"); | |
676 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
677 | usb_cancel_packet(&q->packet); | |
678 | } | |
679 | QTAILQ_REMOVE(&q->ehci->queues, q, next); | |
7267c094 | 680 | g_free(q); |
8ac6d699 GH |
681 | } |
682 | ||
683 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr) | |
684 | { | |
685 | EHCIQueue *q; | |
686 | ||
687 | QTAILQ_FOREACH(q, &ehci->queues, next) { | |
688 | if (addr == q->qhaddr) { | |
689 | return q; | |
690 | } | |
691 | } | |
692 | return NULL; | |
693 | } | |
694 | ||
695 | static void ehci_queues_rip_unused(EHCIState *ehci) | |
696 | { | |
697 | EHCIQueue *q, *tmp; | |
698 | ||
699 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
700 | if (q->seen) { | |
701 | q->seen = 0; | |
adddecb1 | 702 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
703 | continue; |
704 | } | |
adddecb1 | 705 | if (ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
706 | /* allow 0.25 sec idle */ |
707 | continue; | |
708 | } | |
709 | ehci_free_queue(q); | |
710 | } | |
711 | } | |
712 | ||
07771f6f GH |
713 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev) |
714 | { | |
715 | EHCIQueue *q, *tmp; | |
716 | ||
717 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
25d5de7d GH |
718 | if (q->packet.owner == NULL || |
719 | q->packet.owner->dev != dev) { | |
07771f6f GH |
720 | continue; |
721 | } | |
722 | ehci_free_queue(q); | |
723 | } | |
724 | } | |
725 | ||
8ac6d699 GH |
726 | static void ehci_queues_rip_all(EHCIState *ehci) |
727 | { | |
728 | EHCIQueue *q, *tmp; | |
729 | ||
730 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
731 | ehci_free_queue(q); | |
732 | } | |
733 | } | |
734 | ||
94527ead GH |
735 | /* Attach or detach a device on root hub */ |
736 | ||
737 | static void ehci_attach(USBPort *port) | |
738 | { | |
739 | EHCIState *s = port->opaque; | |
740 | uint32_t *portsc = &s->portsc[port->index]; | |
741 | ||
dcbd0b5c | 742 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead | 743 | |
a0a3167a HG |
744 | if (*portsc & PORTSC_POWNER) { |
745 | USBPort *companion = s->companion_ports[port->index]; | |
746 | companion->dev = port->dev; | |
747 | companion->ops->attach(companion); | |
748 | return; | |
749 | } | |
750 | ||
94527ead GH |
751 | *portsc |= PORTSC_CONNECT; |
752 | *portsc |= PORTSC_CSC; | |
753 | ||
a0a3167a | 754 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
755 | } |
756 | ||
757 | static void ehci_detach(USBPort *port) | |
758 | { | |
759 | EHCIState *s = port->opaque; | |
760 | uint32_t *portsc = &s->portsc[port->index]; | |
761 | ||
dcbd0b5c | 762 | trace_usb_ehci_port_detach(port->index); |
94527ead | 763 | |
a0a3167a HG |
764 | if (*portsc & PORTSC_POWNER) { |
765 | USBPort *companion = s->companion_ports[port->index]; | |
766 | companion->ops->detach(companion); | |
767 | companion->dev = NULL; | |
768 | return; | |
769 | } | |
770 | ||
4706ab6c HG |
771 | ehci_queues_rip_device(s, port->dev); |
772 | ||
fbd97532 | 773 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
774 | *portsc |= PORTSC_CSC; |
775 | ||
a0a3167a | 776 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
777 | } |
778 | ||
4706ab6c HG |
779 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
780 | { | |
781 | EHCIState *s = port->opaque; | |
a0a3167a HG |
782 | uint32_t portsc = s->portsc[port->index]; |
783 | ||
784 | if (portsc & PORTSC_POWNER) { | |
785 | USBPort *companion = s->companion_ports[port->index]; | |
786 | companion->ops->child_detach(companion, child); | |
787 | companion->dev = NULL; | |
788 | return; | |
789 | } | |
4706ab6c HG |
790 | |
791 | ehci_queues_rip_device(s, child); | |
792 | } | |
793 | ||
a0a3167a HG |
794 | static void ehci_wakeup(USBPort *port) |
795 | { | |
796 | EHCIState *s = port->opaque; | |
797 | uint32_t portsc = s->portsc[port->index]; | |
798 | ||
799 | if (portsc & PORTSC_POWNER) { | |
800 | USBPort *companion = s->companion_ports[port->index]; | |
801 | if (companion->ops->wakeup) { | |
802 | companion->ops->wakeup(companion); | |
803 | } | |
804 | } | |
805 | } | |
806 | ||
807 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
808 | uint32_t portcount, uint32_t firstport) | |
809 | { | |
810 | EHCIState *s = container_of(bus, EHCIState, bus); | |
811 | uint32_t i; | |
812 | ||
813 | if (firstport + portcount > NB_PORTS) { | |
814 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
815 | "firstport on masterbus"); | |
816 | error_printf_unless_qmp( | |
817 | "firstport value of %u makes companion take ports %u - %u, which " | |
818 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
819 | firstport + portcount - 1, NB_PORTS - 1); | |
820 | return -1; | |
821 | } | |
822 | ||
823 | for (i = 0; i < portcount; i++) { | |
824 | if (s->companion_ports[firstport + i]) { | |
825 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
826 | "an USB masterbus"); | |
827 | error_printf_unless_qmp( | |
828 | "port %u on masterbus %s already has a companion assigned\n", | |
829 | firstport + i, bus->qbus.name); | |
830 | return -1; | |
831 | } | |
832 | } | |
833 | ||
834 | for (i = 0; i < portcount; i++) { | |
835 | s->companion_ports[firstport + i] = ports[i]; | |
836 | s->ports[firstport + i].speedmask |= | |
837 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
838 | /* Ensure devs attached before the initial reset go to the companion */ | |
839 | s->portsc[firstport + i] = PORTSC_POWNER; | |
840 | } | |
841 | ||
842 | s->companion_count++; | |
843 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
94527ead GH |
848 | /* 4.1 host controller initialization */ |
849 | static void ehci_reset(void *opaque) | |
850 | { | |
851 | EHCIState *s = opaque; | |
94527ead | 852 | int i; |
a0a3167a | 853 | USBDevice *devs[NB_PORTS]; |
94527ead | 854 | |
439a97cc | 855 | trace_usb_ehci_reset(); |
94527ead | 856 | |
a0a3167a HG |
857 | /* |
858 | * Do the detach before touching portsc, so that it correctly gets send to | |
859 | * us or to our companion based on PORTSC_POWNER before the reset. | |
860 | */ | |
861 | for(i = 0; i < NB_PORTS; i++) { | |
862 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
863 | if (devs[i] && devs[i]->attached) { |
864 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
865 | } |
866 | } | |
867 | ||
94527ead GH |
868 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); |
869 | ||
870 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
871 | s->usbsts = USBSTS_HALT; | |
872 | ||
873 | s->astate = EST_INACTIVE; | |
874 | s->pstate = EST_INACTIVE; | |
94527ead GH |
875 | s->isoch_pause = -1; |
876 | s->attach_poll_counter = 0; | |
877 | ||
878 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
879 | if (s->companion_ports[i]) { |
880 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
881 | } else { | |
882 | s->portsc[i] = PORTSC_PPOWER; | |
883 | } | |
891fb2cd GH |
884 | if (devs[i] && devs[i]->attached) { |
885 | usb_attach(&s->ports[i]); | |
e0b8e72d | 886 | usb_send_msg(devs[i], USB_MSG_RESET); |
94527ead GH |
887 | } |
888 | } | |
8ac6d699 | 889 | ehci_queues_rip_all(s); |
94527ead GH |
890 | } |
891 | ||
892 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
893 | { | |
894 | EHCIState *s = ptr; | |
895 | uint32_t val; | |
896 | ||
897 | val = s->mmio[addr]; | |
898 | ||
899 | return val; | |
900 | } | |
901 | ||
902 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
903 | { | |
904 | EHCIState *s = ptr; | |
905 | uint32_t val; | |
906 | ||
907 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
908 | ||
909 | return val; | |
910 | } | |
911 | ||
912 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
913 | { | |
914 | EHCIState *s = ptr; | |
915 | uint32_t val; | |
916 | ||
917 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
918 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
919 | ||
439a97cc | 920 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
921 | return val; |
922 | } | |
923 | ||
924 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
925 | { | |
926 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
927 | exit(1); | |
928 | } | |
929 | ||
930 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
931 | { | |
932 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
933 | exit(1); | |
934 | } | |
935 | ||
a0a3167a HG |
936 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
937 | { | |
938 | USBDevice *dev = s->ports[port].dev; | |
939 | uint32_t *portsc = &s->portsc[port]; | |
940 | uint32_t orig; | |
941 | ||
942 | if (s->companion_ports[port] == NULL) | |
943 | return; | |
944 | ||
945 | owner = owner & PORTSC_POWNER; | |
946 | orig = *portsc & PORTSC_POWNER; | |
947 | ||
948 | if (!(owner ^ orig)) { | |
949 | return; | |
950 | } | |
951 | ||
891fb2cd GH |
952 | if (dev && dev->attached) { |
953 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
954 | } |
955 | ||
956 | *portsc &= ~PORTSC_POWNER; | |
957 | *portsc |= owner; | |
958 | ||
891fb2cd GH |
959 | if (dev && dev->attached) { |
960 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
961 | } |
962 | } | |
963 | ||
94527ead GH |
964 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
965 | { | |
966 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
967 | USBDevice *dev = s->ports[port].dev; |
968 | ||
fbd97532 HG |
969 | /* Clear rwc bits */ |
970 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
971 | /* The guest may clear, but not set the PED bit */ | |
972 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
973 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
974 | handle_port_owner_write(s, port, val); | |
975 | /* And finally apply RO_MASK */ | |
94527ead GH |
976 | val &= PORTSC_RO_MASK; |
977 | ||
94527ead | 978 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 979 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
980 | } |
981 | ||
982 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 983 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 984 | if (dev && dev->attached) { |
e0b8e72d | 985 | usb_reset(&s->ports[port]); |
94527ead GH |
986 | *portsc &= ~PORTSC_CSC; |
987 | } | |
988 | ||
fbd97532 HG |
989 | /* |
990 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 991 | * to SW that this port has a high speed device attached |
94527ead | 992 | */ |
891fb2cd | 993 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
994 | val |= PORTSC_PED; |
995 | } | |
94527ead GH |
996 | } |
997 | ||
998 | *portsc &= ~PORTSC_RO_MASK; | |
999 | *portsc |= val; | |
94527ead GH |
1000 | } |
1001 | ||
1002 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1003 | { | |
1004 | EHCIState *s = ptr; | |
c4f8e211 GH |
1005 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1006 | uint32_t old = *mmio; | |
94527ead | 1007 | int i; |
439a97cc | 1008 | |
c4f8e211 | 1009 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
1010 | |
1011 | /* Only aligned reads are allowed on OHCI */ | |
1012 | if (addr & 3) { | |
1013 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1014 | TARGET_FMT_plx "\n", addr); | |
1015 | return; | |
1016 | } | |
1017 | ||
1018 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1019 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 1020 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
1021 | return; |
1022 | } | |
1023 | ||
1024 | if (addr < OPREGBASE) { | |
1025 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1026 | TARGET_FMT_plx "\n", addr); | |
1027 | return; | |
1028 | } | |
1029 | ||
1030 | ||
1031 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
1032 | switch(addr) { |
1033 | case USBCMD: | |
94527ead | 1034 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
1035 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
1036 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 1037 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
1038 | } |
1039 | ||
1040 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead GH |
1041 | qemu_del_timer(s->frame_timer); |
1042 | // TODO - should finish out some stuff before setting halt | |
439a97cc | 1043 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
1044 | } |
1045 | ||
1046 | if (val & USBCMD_HCRESET) { | |
94527ead GH |
1047 | ehci_reset(s); |
1048 | val &= ~USBCMD_HCRESET; | |
1049 | } | |
1050 | ||
1051 | /* not supporting dynamic frame list size at the moment */ | |
1052 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1053 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1054 | val & USBCMD_FLS); | |
1055 | val &= ~USBCMD_FLS; | |
1056 | } | |
94527ead GH |
1057 | break; |
1058 | ||
94527ead GH |
1059 | case USBSTS: |
1060 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
439a97cc GH |
1061 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC |
1062 | val = s->usbsts; | |
94527ead GH |
1063 | ehci_set_interrupt(s, 0); |
1064 | break; | |
1065 | ||
94527ead GH |
1066 | case USBINTR: |
1067 | val &= USBINTR_MASK; | |
94527ead GH |
1068 | break; |
1069 | ||
1070 | case FRINDEX: | |
1071 | s->sofv = val >> 3; | |
94527ead GH |
1072 | break; |
1073 | ||
1074 | case CONFIGFLAG: | |
94527ead GH |
1075 | val &= 0x1; |
1076 | if (val) { | |
1077 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1078 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1079 | } |
1080 | break; | |
1081 | ||
1082 | case PERIODICLISTBASE: | |
1083 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1084 | fprintf(stderr, | |
1085 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1086 | " is enabled and HC is enabled\n"); | |
1087 | } | |
94527ead GH |
1088 | break; |
1089 | ||
1090 | case ASYNCLISTADDR: | |
1091 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1092 | fprintf(stderr, | |
1093 | "ehci: ASYNC list address register set while async schedule\n" | |
1094 | " is enabled and HC is enabled\n"); | |
1095 | } | |
94527ead GH |
1096 | break; |
1097 | } | |
1098 | ||
c4f8e211 GH |
1099 | *mmio = val; |
1100 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
1101 | } |
1102 | ||
1103 | ||
1104 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1105 | ||
1106 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1107 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1108 | uint32_t *buf, int num) | |
94527ead GH |
1109 | { |
1110 | int i; | |
1111 | ||
1112 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
4bf80119 | 1113 | pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); |
94527ead GH |
1114 | *buf = le32_to_cpu(*buf); |
1115 | } | |
1116 | ||
1117 | return 1; | |
1118 | } | |
1119 | ||
1120 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1121 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1122 | uint32_t *buf, int num) | |
94527ead GH |
1123 | { |
1124 | int i; | |
1125 | ||
1126 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1127 | uint32_t tmp = cpu_to_le32(*buf); | |
4bf80119 | 1128 | pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1129 | } |
1130 | ||
1131 | return 1; | |
1132 | } | |
1133 | ||
1134 | // 4.10.2 | |
1135 | ||
0122f472 | 1136 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead GH |
1137 | { |
1138 | int i; | |
1139 | int dtoggle; | |
1140 | int ping; | |
1141 | int eps; | |
1142 | int reload; | |
1143 | ||
1144 | // remember values in fields to preserve in qh after overlay | |
1145 | ||
0122f472 GH |
1146 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1147 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1148 | |
0122f472 GH |
1149 | q->qh.current_qtd = q->qtdaddr; |
1150 | q->qh.next_qtd = q->qtd.next; | |
1151 | q->qh.altnext_qtd = q->qtd.altnext; | |
1152 | q->qh.token = q->qtd.token; | |
94527ead GH |
1153 | |
1154 | ||
0122f472 | 1155 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1156 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1157 | q->qh.token &= ~QTD_TOKEN_PING; |
1158 | q->qh.token |= ping; | |
94527ead GH |
1159 | } |
1160 | ||
0122f472 GH |
1161 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1162 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1163 | |
1164 | for (i = 0; i < 5; i++) { | |
0122f472 | 1165 | q->qh.bufptr[i] = q->qtd.bufptr[i]; |
94527ead GH |
1166 | } |
1167 | ||
0122f472 | 1168 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1169 | // preserve QH DT bit |
0122f472 GH |
1170 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1171 | q->qh.token |= dtoggle; | |
94527ead GH |
1172 | } |
1173 | ||
0122f472 GH |
1174 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1175 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1176 | |
68d55358 DG |
1177 | put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, |
1178 | sizeof(EHCIqh) >> 2); | |
94527ead GH |
1179 | |
1180 | return 0; | |
1181 | } | |
1182 | ||
0ce668bc | 1183 | static int ehci_init_transfer(EHCIQueue *q) |
94527ead | 1184 | { |
0ce668bc | 1185 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1186 | dma_addr_t page; |
94527ead | 1187 | |
0ce668bc GH |
1188 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1189 | bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); | |
0122f472 | 1190 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; |
68d55358 | 1191 | pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5); |
94527ead | 1192 | |
0ce668bc GH |
1193 | while (bytes > 0) { |
1194 | if (cpage > 4) { | |
1195 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1196 | return USB_RET_PROCERR; | |
1197 | } | |
94527ead | 1198 | |
0ce668bc GH |
1199 | page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; |
1200 | page += offset; | |
1201 | plen = bytes; | |
1202 | if (plen > 4096 - offset) { | |
1203 | plen = 4096 - offset; | |
1204 | offset = 0; | |
1205 | cpage++; | |
94527ead GH |
1206 | } |
1207 | ||
0ce668bc GH |
1208 | qemu_sglist_add(&q->sgl, page, plen); |
1209 | bytes -= plen; | |
1210 | } | |
1211 | return 0; | |
1212 | } | |
94527ead | 1213 | |
0ce668bc GH |
1214 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1215 | { | |
1216 | uint32_t cpage, offset; | |
94527ead | 1217 | |
0ce668bc | 1218 | qemu_sglist_destroy(&q->sgl); |
94527ead | 1219 | |
0ce668bc GH |
1220 | if (status > 0) { |
1221 | /* update cpage & offset */ | |
1222 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1223 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1224 | |
0ce668bc GH |
1225 | offset += status; |
1226 | cpage += offset >> QTD_BUFPTR_SH; | |
1227 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1228 | |
0ce668bc GH |
1229 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1230 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1231 | q->qh.bufptr[0] |= offset; | |
1232 | } | |
94527ead GH |
1233 | } |
1234 | ||
d47e59b8 | 1235 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1236 | { |
a0a3167a HG |
1237 | EHCIQueue *q; |
1238 | EHCIState *s = port->opaque; | |
1239 | uint32_t portsc = s->portsc[port->index]; | |
1240 | ||
1241 | if (portsc & PORTSC_POWNER) { | |
1242 | USBPort *companion = s->companion_ports[port->index]; | |
1243 | companion->ops->complete(companion, packet); | |
1244 | return; | |
1245 | } | |
94527ead | 1246 | |
a0a3167a | 1247 | q = container_of(packet, EHCIQueue, packet); |
8ac6d699 GH |
1248 | trace_usb_ehci_queue_action(q, "wakeup"); |
1249 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
0122f472 | 1250 | q->async = EHCI_ASYNC_FINISHED; |
4f4321c1 | 1251 | q->usb_status = packet->result; |
94527ead GH |
1252 | } |
1253 | ||
0122f472 | 1254 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead GH |
1255 | { |
1256 | int c_err, reload; | |
1257 | ||
8ac6d699 | 1258 | assert(q->async != EHCI_ASYNC_INFLIGHT); |
0122f472 | 1259 | q->async = EHCI_ASYNC_NONE; |
94527ead GH |
1260 | |
1261 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1262 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1263 | |
0122f472 | 1264 | if (q->usb_status < 0) { |
94527ead GH |
1265 | err: |
1266 | /* TO-DO: put this is in a function that can be invoked below as well */ | |
0122f472 | 1267 | c_err = get_field(q->qh.token, QTD_TOKEN_CERR); |
94527ead | 1268 | c_err--; |
0122f472 | 1269 | set_field(&q->qh.token, c_err, QTD_TOKEN_CERR); |
94527ead | 1270 | |
0122f472 | 1271 | switch(q->usb_status) { |
94527ead | 1272 | case USB_RET_NODEV: |
d2bd525f GH |
1273 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1274 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1275 | break; |
1276 | case USB_RET_STALL: | |
0122f472 GH |
1277 | q->qh.token |= QTD_TOKEN_HALT; |
1278 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1279 | break; |
1280 | case USB_RET_NAK: | |
1281 | /* 4.10.3 */ | |
0122f472 GH |
1282 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1283 | if ((q->pid == USB_TOKEN_IN) && reload) { | |
1284 | int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1285 | nakcnt--; |
0122f472 | 1286 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead | 1287 | } else if (!reload) { |
0122f472 | 1288 | return; |
94527ead GH |
1289 | } |
1290 | break; | |
1291 | case USB_RET_BABBLE: | |
d2bd525f | 1292 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1293 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1294 | break; |
1295 | default: | |
0122f472 GH |
1296 | /* should not be triggerable */ |
1297 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1298 | assert(0); | |
94527ead GH |
1299 | break; |
1300 | } | |
1301 | } else { | |
1302 | // DPRINTF("Short packet condition\n"); | |
1303 | // TODO check 4.12 for splits | |
1304 | ||
0122f472 GH |
1305 | if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { |
1306 | q->usb_status = USB_RET_BABBLE; | |
94527ead GH |
1307 | goto err; |
1308 | } | |
1309 | ||
0122f472 | 1310 | if (q->tbytes && q->pid == USB_TOKEN_IN) { |
0122f472 | 1311 | q->tbytes -= q->usb_status; |
94527ead | 1312 | } else { |
0122f472 | 1313 | q->tbytes = 0; |
94527ead GH |
1314 | } |
1315 | ||
0122f472 GH |
1316 | DPRINTF("updating tbytes to %d\n", q->tbytes); |
1317 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1318 | } |
0ce668bc GH |
1319 | ehci_finish_transfer(q, q->usb_status); |
1320 | usb_packet_unmap(&q->packet); | |
94527ead | 1321 | |
0122f472 GH |
1322 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1323 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1324 | |
0122f472 GH |
1325 | if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) { |
1326 | ehci_record_interrupt(q->ehci, USBSTS_INT); | |
94527ead | 1327 | } |
94527ead GH |
1328 | } |
1329 | ||
1330 | // 4.10.3 | |
1331 | ||
0122f472 | 1332 | static int ehci_execute(EHCIQueue *q) |
94527ead GH |
1333 | { |
1334 | USBPort *port; | |
1335 | USBDevice *dev; | |
1336 | int ret; | |
1337 | int i; | |
1338 | int endp; | |
1339 | int devadr; | |
1340 | ||
0122f472 | 1341 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1342 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1343 | return USB_RET_PROCERR; | |
1344 | } | |
1345 | ||
0122f472 GH |
1346 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1347 | if (q->tbytes > BUFF_SIZE) { | |
94527ead GH |
1348 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1349 | return USB_RET_PROCERR; | |
1350 | } | |
1351 | ||
0122f472 GH |
1352 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1353 | switch(q->pid) { | |
1354 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1355 | case 1: q->pid = USB_TOKEN_IN; break; | |
1356 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
94527ead GH |
1357 | default: fprintf(stderr, "bad token\n"); break; |
1358 | } | |
1359 | ||
0ce668bc | 1360 | if (ehci_init_transfer(q) != 0) { |
94527ead GH |
1361 | return USB_RET_PROCERR; |
1362 | } | |
1363 | ||
0122f472 GH |
1364 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1365 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead GH |
1366 | |
1367 | ret = USB_RET_NODEV; | |
1368 | ||
0ce668bc GH |
1369 | usb_packet_setup(&q->packet, q->pid, devadr, endp); |
1370 | usb_packet_map(&q->packet, &q->sgl); | |
1371 | ||
94527ead GH |
1372 | // TO-DO: associating device with ehci port |
1373 | for(i = 0; i < NB_PORTS; i++) { | |
0122f472 | 1374 | port = &q->ehci->ports[i]; |
94527ead GH |
1375 | dev = port->dev; |
1376 | ||
0122f472 | 1377 | if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) { |
94527ead | 1378 | DPRINTF("Port %d, no exec, not connected(%08X)\n", |
0122f472 | 1379 | i, q->ehci->portsc[i]); |
94527ead GH |
1380 | continue; |
1381 | } | |
1382 | ||
0122f472 | 1383 | ret = usb_handle_packet(dev, &q->packet); |
94527ead | 1384 | |
4f4321c1 GH |
1385 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " |
1386 | "(total %d) endp %x ret %d\n", | |
0122f472 | 1387 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
4f4321c1 | 1388 | q->packet.iov.size, q->tbytes, endp, ret); |
94527ead GH |
1389 | |
1390 | if (ret != USB_RET_NODEV) { | |
1391 | break; | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | if (ret > BUFF_SIZE) { | |
1396 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1397 | return USB_RET_PROCERR; | |
1398 | } | |
1399 | ||
94527ead GH |
1400 | return ret; |
1401 | } | |
1402 | ||
1403 | /* 4.7.2 | |
1404 | */ | |
1405 | ||
1406 | static int ehci_process_itd(EHCIState *ehci, | |
1407 | EHCIitd *itd) | |
1408 | { | |
1409 | USBPort *port; | |
1410 | USBDevice *dev; | |
1411 | int ret; | |
0ce668bc | 1412 | uint32_t i, j, len, pid, dir, devaddr, endp; |
e654887f | 1413 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1414 | |
1415 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1416 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1417 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1418 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1419 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1420 | |
1421 | for(i = 0; i < 8; i++) { | |
1422 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1423 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1424 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1425 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1426 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1427 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1428 | ||
1429 | if (len > max * mult) { | |
1430 | len = max * mult; | |
1431 | } | |
94527ead GH |
1432 | |
1433 | if (len > BUFF_SIZE) { | |
1434 | return USB_RET_PROCERR; | |
1435 | } | |
1436 | ||
68d55358 | 1437 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1438 | if (off + len > 4096) { |
1439 | /* transfer crosses page border */ | |
0ce668bc GH |
1440 | uint32_t len2 = off + len - 4096; |
1441 | uint32_t len1 = len - len2; | |
1442 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1443 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1444 | } else { |
0ce668bc | 1445 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1446 | } |
94527ead | 1447 | |
0ce668bc | 1448 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1449 | |
0ce668bc GH |
1450 | usb_packet_setup(&ehci->ipacket, pid, devaddr, endp); |
1451 | usb_packet_map(&ehci->ipacket, &ehci->isgl); | |
94527ead | 1452 | |
0ce668bc | 1453 | ret = USB_RET_NODEV; |
94527ead GH |
1454 | for (j = 0; j < NB_PORTS; j++) { |
1455 | port = &ehci->ports[j]; | |
1456 | dev = port->dev; | |
1457 | ||
94527ead | 1458 | if (!(ehci->portsc[j] &(PORTSC_CONNECT))) { |
94527ead GH |
1459 | continue; |
1460 | } | |
1461 | ||
0122f472 | 1462 | ret = usb_handle_packet(dev, &ehci->ipacket); |
94527ead GH |
1463 | |
1464 | if (ret != USB_RET_NODEV) { | |
1465 | break; | |
1466 | } | |
1467 | } | |
1468 | ||
0ce668bc GH |
1469 | usb_packet_unmap(&ehci->ipacket); |
1470 | qemu_sglist_destroy(&ehci->isgl); | |
1471 | ||
e654887f | 1472 | #if 0 |
94527ead GH |
1473 | /* In isoch, there is no facility to indicate a NAK so let's |
1474 | * instead just complete a zero-byte transaction. Setting | |
1475 | * DBERR seems too draconian. | |
1476 | */ | |
1477 | ||
1478 | if (ret == USB_RET_NAK) { | |
1479 | if (ehci->isoch_pause > 0) { | |
1480 | DPRINTF("ISOCH: received a NAK but paused so returning\n"); | |
1481 | ehci->isoch_pause--; | |
1482 | return 0; | |
1483 | } else if (ehci->isoch_pause == -1) { | |
1484 | DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n"); | |
1485 | // Pause frindex for up to 50 msec waiting for data from | |
1486 | // remote | |
1487 | ehci->isoch_pause = 50; | |
1488 | return 0; | |
1489 | } else { | |
1490 | DPRINTF("ISOCH: isoch pause timeout! return 0\n"); | |
1491 | ret = 0; | |
1492 | } | |
1493 | } else { | |
1494 | DPRINTF("ISOCH: received ACK, clearing pause\n"); | |
1495 | ehci->isoch_pause = -1; | |
1496 | } | |
e654887f GH |
1497 | #else |
1498 | if (ret == USB_RET_NAK) { | |
1499 | ret = 0; | |
1500 | } | |
1501 | #endif | |
94527ead GH |
1502 | |
1503 | if (ret >= 0) { | |
e654887f GH |
1504 | if (!dir) { |
1505 | /* OUT */ | |
1506 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1507 | } else { | |
1508 | /* IN */ | |
e654887f GH |
1509 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); |
1510 | } | |
94527ead GH |
1511 | |
1512 | if (itd->transact[i] & ITD_XACT_IOC) { | |
1513 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1514 | } | |
1515 | } | |
e654887f | 1516 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1517 | } |
1518 | } | |
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | /* This state is the entry point for asynchronous schedule | |
1523 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1524 | */ | |
26d53979 | 1525 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1526 | { |
0122f472 | 1527 | EHCIqh qh; |
94527ead GH |
1528 | int i = 0; |
1529 | int again = 0; | |
1530 | uint32_t entry = ehci->asynclistaddr; | |
1531 | ||
1532 | /* set reclamation flag at start event (4.8.6) */ | |
1533 | if (async) { | |
439a97cc | 1534 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1535 | } |
1536 | ||
8ac6d699 GH |
1537 | ehci_queues_rip_unused(ehci); |
1538 | ||
94527ead GH |
1539 | /* Find the head of the list (4.9.1.1) */ |
1540 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1541 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1542 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1543 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1544 | |
0122f472 | 1545 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1546 | if (async) { |
1547 | entry |= (NLPTR_TYPE_QH << 1); | |
1548 | } | |
1549 | ||
0122f472 | 1550 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1551 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1552 | again = 1; |
1553 | goto out; | |
1554 | } | |
1555 | ||
0122f472 | 1556 | entry = qh.next; |
94527ead | 1557 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1558 | break; |
1559 | } | |
1560 | } | |
1561 | ||
1562 | /* no head found for list. */ | |
1563 | ||
26d53979 | 1564 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1565 | |
1566 | out: | |
1567 | return again; | |
1568 | } | |
1569 | ||
1570 | ||
1571 | /* This state is the entry point for periodic schedule processing as | |
1572 | * well as being a continuation state for async processing. | |
1573 | */ | |
26d53979 | 1574 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1575 | { |
1576 | int again = 0; | |
0122f472 | 1577 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1578 | |
94527ead GH |
1579 | if (entry < 0x1000) { |
1580 | DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry); | |
26d53979 | 1581 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1582 | goto out; |
1583 | } | |
1584 | ||
1585 | /* section 4.8, only QH in async schedule */ | |
1586 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1587 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1588 | return -1; | |
1589 | } | |
1590 | ||
1591 | switch (NLPTR_TYPE_GET(entry)) { | |
1592 | case NLPTR_TYPE_QH: | |
26d53979 | 1593 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1594 | again = 1; |
1595 | break; | |
1596 | ||
1597 | case NLPTR_TYPE_ITD: | |
26d53979 | 1598 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1599 | again = 1; |
1600 | break; | |
1601 | ||
2fe80192 GH |
1602 | case NLPTR_TYPE_STITD: |
1603 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1604 | again = 1; | |
1605 | break; | |
1606 | ||
94527ead | 1607 | default: |
2fe80192 | 1608 | /* TODO: handle FSTN type */ |
94527ead GH |
1609 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1610 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1611 | return -1; | |
1612 | } | |
1613 | ||
1614 | out: | |
1615 | return again; | |
1616 | } | |
1617 | ||
0122f472 | 1618 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1619 | { |
0122f472 GH |
1620 | uint32_t entry; |
1621 | EHCIQueue *q; | |
94527ead | 1622 | int reload; |
94527ead | 1623 | |
0122f472 | 1624 | entry = ehci_get_fetch_addr(ehci, async); |
8ac6d699 GH |
1625 | q = ehci_find_queue_by_qh(ehci, entry); |
1626 | if (NULL == q) { | |
1627 | q = ehci_alloc_queue(ehci, async); | |
1628 | } | |
0122f472 | 1629 | q->qhaddr = entry; |
8ac6d699 GH |
1630 | q->seen++; |
1631 | ||
1632 | if (q->seen > 1) { | |
1633 | /* we are going in circles -- stop processing */ | |
1634 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1635 | q = NULL; | |
1636 | goto out; | |
1637 | } | |
94527ead | 1638 | |
68d55358 DG |
1639 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1640 | (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
8ac6d699 GH |
1641 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1642 | ||
1643 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1644 | /* I/O still in progress -- skip queue */ | |
1645 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1646 | goto out; | |
1647 | } | |
1648 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1649 | /* I/O finished -- continue processing queue */ | |
1650 | trace_usb_ehci_queue_action(q, "resume"); | |
1651 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1652 | goto out; | |
1653 | } | |
0122f472 GH |
1654 | |
1655 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1656 | |
1657 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1658 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1659 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1660 | } else { |
1661 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1662 | " - done processing\n", q->qhaddr); |
26d53979 | 1663 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1664 | q = NULL; |
94527ead GH |
1665 | goto out; |
1666 | } | |
1667 | } | |
1668 | ||
1669 | #if EHCI_DEBUG | |
0122f472 | 1670 | if (q->qhaddr != q->qh.next) { |
94527ead | 1671 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1672 | q->qhaddr, |
1673 | q->qh.epchar & QH_EPCHAR_H, | |
1674 | q->qh.token & QTD_TOKEN_HALT, | |
1675 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1676 | q->qh.next); | |
94527ead GH |
1677 | } |
1678 | #endif | |
1679 | ||
0122f472 | 1680 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1681 | if (reload) { |
0122f472 | 1682 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1683 | } |
1684 | ||
0122f472 | 1685 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1686 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1687 | |
0122f472 GH |
1688 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) { |
1689 | q->qtdaddr = q->qh.current_qtd; | |
26d53979 | 1690 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1691 | |
1692 | } else { | |
1693 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1694 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1695 | } |
1696 | ||
1697 | out: | |
0122f472 | 1698 | return q; |
94527ead GH |
1699 | } |
1700 | ||
26d53979 | 1701 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1702 | { |
0122f472 | 1703 | uint32_t entry; |
94527ead GH |
1704 | EHCIitd itd; |
1705 | ||
0122f472 GH |
1706 | assert(!async); |
1707 | entry = ehci_get_fetch_addr(ehci, async); | |
1708 | ||
68d55358 | 1709 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1710 | sizeof(EHCIitd) >> 2); |
0122f472 | 1711 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1712 | |
1713 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1714 | return -1; | |
1715 | } | |
1716 | ||
68d55358 DG |
1717 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1718 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1719 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1720 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1721 | |
1722 | return 1; | |
1723 | } | |
1724 | ||
2fe80192 GH |
1725 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1726 | { | |
1727 | uint32_t entry; | |
1728 | EHCIsitd sitd; | |
1729 | ||
1730 | assert(!async); | |
1731 | entry = ehci_get_fetch_addr(ehci, async); | |
1732 | ||
68d55358 | 1733 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1734 | sizeof(EHCIsitd) >> 2); |
1735 | ehci_trace_sitd(ehci, entry, &sitd); | |
1736 | ||
1737 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1738 | /* siTD is not active, nothing to do */; | |
1739 | } else { | |
1740 | /* TODO: split transfers are not implemented */ | |
1741 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1742 | } | |
1743 | ||
1744 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1745 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1746 | return 1; | |
1747 | } | |
1748 | ||
94527ead | 1749 | /* Section 4.10.2 - paragraph 3 */ |
0122f472 | 1750 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1751 | { |
1752 | #if 0 | |
1753 | /* TO-DO: 4.10.2 - paragraph 2 | |
1754 | * if I-bit is set to 1 and QH is not active | |
1755 | * go to horizontal QH | |
1756 | */ | |
1757 | if (I-bit set) { | |
26d53979 | 1758 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1759 | goto out; |
1760 | } | |
1761 | #endif | |
1762 | ||
1763 | /* | |
1764 | * want data and alt-next qTD is valid | |
1765 | */ | |
0122f472 GH |
1766 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1767 | (q->qh.altnext_qtd > 0x1000) && | |
1768 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { | |
1769 | q->qtdaddr = q->qh.altnext_qtd; | |
1770 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1771 | |
1772 | /* | |
1773 | * next qTD is valid | |
1774 | */ | |
0122f472 GH |
1775 | } else if ((q->qh.next_qtd > 0x1000) && |
1776 | (NLPTR_TBIT(q->qh.next_qtd) == 0)) { | |
1777 | q->qtdaddr = q->qh.next_qtd; | |
1778 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1779 | |
1780 | /* | |
1781 | * no valid qTD, try next QH | |
1782 | */ | |
1783 | } else { | |
0122f472 | 1784 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1785 | } |
1786 | ||
1787 | return 1; | |
1788 | } | |
1789 | ||
1790 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1791 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1792 | { |
94527ead GH |
1793 | int again = 0; |
1794 | ||
68d55358 DG |
1795 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd, |
1796 | sizeof(EHCIqtd) >> 2); | |
8ac6d699 | 1797 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); |
94527ead | 1798 | |
0122f472 GH |
1799 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { |
1800 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
94527ead GH |
1801 | again = 1; |
1802 | } else { | |
0122f472 | 1803 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1804 | again = 1; |
1805 | } | |
1806 | ||
1807 | return again; | |
1808 | } | |
1809 | ||
0122f472 | 1810 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1811 | { |
1812 | int again = 0; | |
1813 | ||
0122f472 GH |
1814 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1815 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1816 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1817 | again = 1; |
1818 | } else { | |
0122f472 | 1819 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1820 | } |
1821 | ||
1822 | return again; | |
1823 | } | |
1824 | ||
8ac6d699 GH |
1825 | /* |
1826 | * Write the qh back to guest physical memory. This step isn't | |
1827 | * in the EHCI spec but we need to do it since we don't share | |
1828 | * physical memory with our guest VM. | |
1829 | * | |
1830 | * The first three dwords are read-only for the EHCI, so skip them | |
1831 | * when writing back the qh. | |
1832 | */ | |
1833 | static void ehci_flush_qh(EHCIQueue *q) | |
1834 | { | |
1835 | uint32_t *qh = (uint32_t *) &q->qh; | |
1836 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1837 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1838 | ||
68d55358 | 1839 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
8ac6d699 GH |
1840 | } |
1841 | ||
0122f472 | 1842 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1843 | { |
94527ead GH |
1844 | int again = 0; |
1845 | int reload, nakcnt; | |
1846 | int smask; | |
1847 | ||
0122f472 | 1848 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1849 | return -1; |
1850 | } | |
1851 | ||
0122f472 | 1852 | smask = get_field(q->qh.epcap, QH_EPCAP_SMASK); |
94527ead GH |
1853 | |
1854 | if (!smask) { | |
0122f472 GH |
1855 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1856 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1857 | if (reload && !nakcnt) { |
0122f472 | 1858 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1859 | again = 1; |
1860 | goto out; | |
1861 | } | |
1862 | } | |
1863 | ||
1864 | // TODO verify enough time remains in the uframe as in 4.4.1.1 | |
1865 | // TODO write back ptr to async list when done or out of time | |
1866 | // TODO Windows does not seem to ever set the MULT field | |
1867 | ||
1868 | if (!async) { | |
0122f472 | 1869 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1870 | if (!transactCtr) { |
0122f472 | 1871 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1872 | again = 1; |
1873 | goto out; | |
1874 | } | |
1875 | } | |
1876 | ||
1877 | if (async) { | |
0122f472 | 1878 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1879 | } |
1880 | ||
0122f472 GH |
1881 | q->usb_status = ehci_execute(q); |
1882 | if (q->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1883 | again = -1; |
1884 | goto out; | |
1885 | } | |
8ac6d699 GH |
1886 | if (q->usb_status == USB_RET_ASYNC) { |
1887 | ehci_flush_qh(q); | |
1888 | trace_usb_ehci_queue_action(q, "suspend"); | |
1889 | q->async = EHCI_ASYNC_INFLIGHT; | |
1890 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1891 | again = 1; |
8ac6d699 | 1892 | goto out; |
94527ead GH |
1893 | } |
1894 | ||
8ac6d699 GH |
1895 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1896 | again = 1; | |
1897 | ||
94527ead GH |
1898 | out: |
1899 | return again; | |
1900 | } | |
1901 | ||
0122f472 | 1902 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1903 | { |
94527ead GH |
1904 | int again = 0; |
1905 | int reload, nakcnt; | |
1906 | ||
0122f472 GH |
1907 | ehci_execute_complete(q); |
1908 | if (q->usb_status == USB_RET_ASYNC) { | |
94527ead GH |
1909 | goto out; |
1910 | } | |
0122f472 | 1911 | if (q->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1912 | again = -1; |
1913 | goto out; | |
1914 | } | |
1915 | ||
1916 | // 4.10.3 | |
1917 | if (!async) { | |
0122f472 | 1918 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1919 | transactCtr--; |
0122f472 | 1920 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1921 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1922 | // counter decrements to 0 | |
1923 | } | |
1924 | ||
0122f472 | 1925 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1926 | if (reload) { |
0122f472 GH |
1927 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); |
1928 | if (q->usb_status == USB_RET_NAK) { | |
94527ead GH |
1929 | if (nakcnt) { |
1930 | nakcnt--; | |
1931 | } | |
94527ead GH |
1932 | } else { |
1933 | nakcnt = reload; | |
94527ead | 1934 | } |
0122f472 | 1935 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1936 | } |
1937 | ||
94527ead | 1938 | /* 4.10.5 */ |
0122f472 GH |
1939 | if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) { |
1940 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1941 | } else { |
0122f472 | 1942 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1943 | } |
1944 | ||
1945 | again = 1; | |
1946 | ||
1947 | out: | |
8ac6d699 | 1948 | ehci_flush_qh(q); |
94527ead GH |
1949 | return again; |
1950 | } | |
1951 | ||
1952 | ||
0122f472 | 1953 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1954 | { |
94527ead GH |
1955 | int again = 0; |
1956 | ||
1957 | /* Write back the QTD from the QH area */ | |
8ac6d699 | 1958 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); |
68d55358 DG |
1959 | put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd, |
1960 | sizeof(EHCIqtd) >> 2); | |
94527ead | 1961 | |
d2bd525f GH |
1962 | /* |
1963 | * EHCI specs say go horizontal here. | |
1964 | * | |
1965 | * We can also advance the queue here for performance reasons. We | |
1966 | * need to take care to only take that shortcut in case we've | |
1967 | * processed the qtd just written back without errors, i.e. halt | |
1968 | * bit is clear. | |
94527ead | 1969 | */ |
d2bd525f GH |
1970 | if (q->qh.token & QTD_TOKEN_HALT) { |
1971 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1972 | again = 1; | |
1973 | } else { | |
0122f472 | 1974 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 1975 | again = 1; |
d2bd525f | 1976 | } |
94527ead GH |
1977 | return again; |
1978 | } | |
1979 | ||
1980 | /* | |
1981 | * This is the state machine that is common to both async and periodic | |
1982 | */ | |
1983 | ||
26d53979 GH |
1984 | static void ehci_advance_state(EHCIState *ehci, |
1985 | int async) | |
94527ead | 1986 | { |
0122f472 | 1987 | EHCIQueue *q = NULL; |
94527ead GH |
1988 | int again; |
1989 | int iter = 0; | |
1990 | ||
1991 | do { | |
26d53979 | 1992 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { |
94527ead GH |
1993 | iter++; |
1994 | /* if we are roaming a lot of QH without executing a qTD | |
1995 | * something is wrong with the linked list. TO-DO: why is | |
1996 | * this hack needed? | |
1997 | */ | |
8ac6d699 GH |
1998 | assert(iter < MAX_ITERATIONS); |
1999 | #if 0 | |
94527ead GH |
2000 | if (iter > MAX_ITERATIONS) { |
2001 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
26d53979 | 2002 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2003 | break; |
2004 | } | |
8ac6d699 | 2005 | #endif |
94527ead | 2006 | } |
26d53979 | 2007 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2008 | case EST_WAITLISTHEAD: |
26d53979 | 2009 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
2010 | break; |
2011 | ||
2012 | case EST_FETCHENTRY: | |
26d53979 | 2013 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2014 | break; |
2015 | ||
2016 | case EST_FETCHQH: | |
0122f472 GH |
2017 | q = ehci_state_fetchqh(ehci, async); |
2018 | again = q ? 1 : 0; | |
94527ead GH |
2019 | break; |
2020 | ||
2021 | case EST_FETCHITD: | |
26d53979 | 2022 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2023 | break; |
2024 | ||
2fe80192 GH |
2025 | case EST_FETCHSITD: |
2026 | again = ehci_state_fetchsitd(ehci, async); | |
2027 | break; | |
2028 | ||
94527ead | 2029 | case EST_ADVANCEQUEUE: |
0122f472 | 2030 | again = ehci_state_advqueue(q, async); |
94527ead GH |
2031 | break; |
2032 | ||
2033 | case EST_FETCHQTD: | |
0122f472 | 2034 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
2035 | break; |
2036 | ||
2037 | case EST_HORIZONTALQH: | |
0122f472 | 2038 | again = ehci_state_horizqh(q, async); |
94527ead GH |
2039 | break; |
2040 | ||
2041 | case EST_EXECUTE: | |
2042 | iter = 0; | |
0122f472 | 2043 | again = ehci_state_execute(q, async); |
94527ead GH |
2044 | break; |
2045 | ||
2046 | case EST_EXECUTING: | |
8ac6d699 | 2047 | assert(q != NULL); |
0122f472 | 2048 | again = ehci_state_executing(q, async); |
94527ead GH |
2049 | break; |
2050 | ||
2051 | case EST_WRITEBACK: | |
b2467216 | 2052 | assert(q != NULL); |
0122f472 | 2053 | again = ehci_state_writeback(q, async); |
94527ead GH |
2054 | break; |
2055 | ||
2056 | default: | |
2057 | fprintf(stderr, "Bad state!\n"); | |
2058 | again = -1; | |
8ac6d699 | 2059 | assert(0); |
94527ead GH |
2060 | break; |
2061 | } | |
2062 | ||
2063 | if (again < 0) { | |
2064 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2065 | ehci_reset(ehci); | |
2066 | again = 0; | |
8ac6d699 | 2067 | assert(0); |
94527ead GH |
2068 | } |
2069 | } | |
2070 | while (again); | |
2071 | ||
2072 | ehci_commit_interrupt(ehci); | |
94527ead GH |
2073 | } |
2074 | ||
2075 | static void ehci_advance_async_state(EHCIState *ehci) | |
2076 | { | |
26d53979 | 2077 | int async = 1; |
94527ead | 2078 | |
26d53979 | 2079 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2080 | case EST_INACTIVE: |
2081 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
2082 | break; | |
2083 | } | |
439a97cc | 2084 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2085 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2086 | // No break, fall through to ACTIVE |
2087 | ||
2088 | case EST_ACTIVE: | |
2089 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
439a97cc | 2090 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2091 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2092 | break; |
2093 | } | |
2094 | ||
2095 | /* If the doorbell is set, the guest wants to make a change to the | |
2096 | * schedule. The host controller needs to release cached data. | |
2097 | * (section 4.8.2) | |
2098 | */ | |
2099 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2100 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2101 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2102 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2103 | break; | |
2104 | } | |
2105 | ||
2106 | /* make sure guest has acknowledged */ | |
2107 | /* TO-DO: is this really needed? */ | |
2108 | if (ehci->usbsts & USBSTS_IAA) { | |
2109 | DPRINTF("IAA status bit still set.\n"); | |
2110 | break; | |
2111 | } | |
2112 | ||
94527ead GH |
2113 | /* check that address register has been set */ |
2114 | if (ehci->asynclistaddr == 0) { | |
2115 | break; | |
2116 | } | |
2117 | ||
26d53979 | 2118 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2119 | ehci_advance_state(ehci, async); |
94527ead GH |
2120 | break; |
2121 | ||
2122 | default: | |
2123 | /* this should only be due to a developer mistake */ | |
2124 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2125 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2126 | assert(0); |
94527ead GH |
2127 | } |
2128 | } | |
2129 | ||
2130 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2131 | { | |
2132 | uint32_t entry; | |
2133 | uint32_t list; | |
26d53979 | 2134 | int async = 0; |
94527ead GH |
2135 | |
2136 | // 4.6 | |
2137 | ||
26d53979 | 2138 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2139 | case EST_INACTIVE: |
2140 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2141 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2142 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2143 | // No break, fall through to ACTIVE |
2144 | } else | |
2145 | break; | |
2146 | ||
2147 | case EST_ACTIVE: | |
2148 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2149 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2150 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2151 | break; |
2152 | } | |
2153 | ||
2154 | list = ehci->periodiclistbase & 0xfffff000; | |
2155 | /* check that register has been set */ | |
2156 | if (list == 0) { | |
2157 | break; | |
2158 | } | |
2159 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2160 | ||
4bf80119 | 2161 | pci_dma_read(&ehci->dev, list, &entry, sizeof entry); |
94527ead GH |
2162 | entry = le32_to_cpu(entry); |
2163 | ||
2164 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2165 | ehci->frindex / 8, list, entry); | |
0122f472 | 2166 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2167 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2168 | ehci_advance_state(ehci, async); | |
94527ead GH |
2169 | break; |
2170 | ||
94527ead GH |
2171 | default: |
2172 | /* this should only be due to a developer mistake */ | |
2173 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2174 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2175 | assert(0); |
94527ead GH |
2176 | } |
2177 | } | |
2178 | ||
2179 | static void ehci_frame_timer(void *opaque) | |
2180 | { | |
2181 | EHCIState *ehci = opaque; | |
2182 | int64_t expire_time, t_now; | |
adddecb1 | 2183 | uint64_t ns_elapsed; |
94527ead | 2184 | int frames; |
94527ead GH |
2185 | int i; |
2186 | int skipped_frames = 0; | |
2187 | ||
94527ead | 2188 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2189 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2190 | |
adddecb1 GH |
2191 | ns_elapsed = t_now - ehci->last_run_ns; |
2192 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2193 | |
2194 | for (i = 0; i < frames; i++) { | |
2195 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
2196 | if (ehci->isoch_pause <= 0) { | |
2197 | ehci->frindex += 8; | |
2198 | } | |
2199 | ||
2200 | if (ehci->frindex > 0x00001fff) { | |
2201 | ehci->frindex = 0; | |
2202 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2203 | } | |
2204 | ||
2205 | ehci->sofv = (ehci->frindex - 1) >> 3; | |
2206 | ehci->sofv &= 0x000003ff; | |
2207 | } | |
2208 | ||
16a2dee6 | 2209 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2210 | skipped_frames++; |
2211 | } else { | |
d0539307 | 2212 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2213 | } |
2214 | ||
adddecb1 | 2215 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2216 | } |
2217 | ||
2218 | #if 0 | |
2219 | if (skipped_frames) { | |
2220 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2221 | } | |
2222 | #endif | |
2223 | ||
2224 | /* Async is not inside loop since it executes everything it can once | |
2225 | * called | |
2226 | */ | |
d0539307 | 2227 | ehci_advance_async_state(ehci); |
94527ead GH |
2228 | |
2229 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2230 | } | |
2231 | ||
94527ead | 2232 | |
e57964f5 AK |
2233 | static const MemoryRegionOps ehci_mem_ops = { |
2234 | .old_mmio = { | |
2235 | .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, | |
2236 | .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, | |
2237 | }, | |
2238 | .endianness = DEVICE_LITTLE_ENDIAN, | |
94527ead GH |
2239 | }; |
2240 | ||
94527ead GH |
2241 | static int usb_ehci_initfn(PCIDevice *dev); |
2242 | ||
2243 | static USBPortOps ehci_port_ops = { | |
2244 | .attach = ehci_attach, | |
2245 | .detach = ehci_detach, | |
4706ab6c | 2246 | .child_detach = ehci_child_detach, |
a0a3167a | 2247 | .wakeup = ehci_wakeup, |
94527ead GH |
2248 | .complete = ehci_async_complete_packet, |
2249 | }; | |
2250 | ||
07771f6f | 2251 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2252 | .register_companion = ehci_register_companion, |
07771f6f GH |
2253 | }; |
2254 | ||
9490fb06 GH |
2255 | static const VMStateDescription vmstate_ehci = { |
2256 | .name = "ehci", | |
2257 | .unmigratable = 1, | |
2258 | }; | |
2259 | ||
3028376e GH |
2260 | static Property ehci_properties[] = { |
2261 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2262 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2263 | DEFINE_PROP_END_OF_LIST(), | |
2264 | }; | |
2265 | ||
40021f08 AL |
2266 | static void ehci_class_init(ObjectClass *klass, void *data) |
2267 | { | |
39bffca2 | 2268 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2269 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2270 | ||
2271 | k->init = usb_ehci_initfn; | |
2272 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2273 | k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ | |
2274 | k->revision = 0x10; | |
2275 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2276 | dc->vmsd = &vmstate_ehci; |
2277 | dc->props = ehci_properties; | |
40021f08 AL |
2278 | } |
2279 | ||
39bffca2 AL |
2280 | static TypeInfo ehci_info = { |
2281 | .name = "usb-ehci", | |
2282 | .parent = TYPE_PCI_DEVICE, | |
2283 | .instance_size = sizeof(EHCIState), | |
2284 | .class_init = ehci_class_init, | |
e855761c AL |
2285 | }; |
2286 | ||
40021f08 AL |
2287 | static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2288 | { | |
39bffca2 | 2289 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2290 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2291 | ||
2292 | k->init = usb_ehci_initfn; | |
2293 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2294 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; | |
2295 | k->revision = 0x03; | |
2296 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2297 | dc->vmsd = &vmstate_ehci; |
2298 | dc->props = ehci_properties; | |
40021f08 AL |
2299 | } |
2300 | ||
39bffca2 AL |
2301 | static TypeInfo ich9_ehci_info = { |
2302 | .name = "ich9-usb-ehci1", | |
2303 | .parent = TYPE_PCI_DEVICE, | |
2304 | .instance_size = sizeof(EHCIState), | |
2305 | .class_init = ich9_ehci_class_init, | |
94527ead GH |
2306 | }; |
2307 | ||
2308 | static int usb_ehci_initfn(PCIDevice *dev) | |
2309 | { | |
2310 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2311 | uint8_t *pci_conf = s->dev.config; | |
2312 | int i; | |
2313 | ||
94527ead | 2314 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2315 | |
2316 | /* capabilities pointer */ | |
2317 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2318 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2319 | ||
817e0b6f | 2320 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2321 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2322 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2323 | ||
2324 | // pci_conf[0x50] = 0x01; // power management caps | |
2325 | ||
4001f22f | 2326 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2327 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2328 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2329 | ||
2330 | pci_conf[0x64] = 0x00; | |
2331 | pci_conf[0x65] = 0x00; | |
2332 | pci_conf[0x66] = 0x00; | |
2333 | pci_conf[0x67] = 0x00; | |
2334 | pci_conf[0x68] = 0x01; | |
2335 | pci_conf[0x69] = 0x00; | |
2336 | pci_conf[0x6a] = 0x00; | |
2337 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2338 | pci_conf[0x6c] = 0x00; | |
2339 | pci_conf[0x6d] = 0x00; | |
2340 | pci_conf[0x6e] = 0x00; | |
2341 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2342 | ||
2343 | // 2.2 host controller interface version | |
2344 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2345 | s->mmio[0x01] = 0x00; | |
2346 | s->mmio[0x02] = 0x00; | |
2347 | s->mmio[0x03] = 0x01; // HC version | |
2348 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2349 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2350 | s->mmio[0x06] = 0x00; | |
2351 | s->mmio[0x07] = 0x00; | |
2352 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2353 | s->mmio[0x09] = 0x68; // EECP | |
2354 | s->mmio[0x0a] = 0x00; | |
2355 | s->mmio[0x0b] = 0x00; | |
2356 | ||
2357 | s->irq = s->dev.irq[3]; | |
2358 | ||
07771f6f | 2359 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2360 | for(i = 0; i < NB_PORTS; i++) { |
2361 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2362 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2363 | s->ports[i].dev = 0; |
2364 | } | |
2365 | ||
2366 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
8ac6d699 | 2367 | QTAILQ_INIT(&s->queues); |
94527ead GH |
2368 | |
2369 | qemu_register_reset(ehci_reset, s); | |
2370 | ||
e57964f5 | 2371 | memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); |
e824b2cc | 2372 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead GH |
2373 | |
2374 | fprintf(stderr, "*** EHCI support is under development ***\n"); | |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
83f7d43a | 2379 | static void ehci_register_types(void) |
94527ead | 2380 | { |
39bffca2 AL |
2381 | type_register_static(&ehci_info); |
2382 | type_register_static(&ich9_ehci_info); | |
94527ead | 2383 | } |
83f7d43a AF |
2384 | |
2385 | type_init(ehci_register_types) | |
94527ead GH |
2386 | |
2387 | /* | |
2388 | * vim: expandtab ts=4 | |
2389 | */ |