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usb-ehci: trace buffer copy
[qemu.git] / hw / usb-ehci.c
CommitLineData
94527ead
GH		 1/*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28#include "hw.h"
29#include "qemu-timer.h"
30#include "usb.h"
31#include "pci.h"
32#include "monitor.h"
439a97cc 33#include "trace.h"
94527ead
GH		 34
35#define EHCI_DEBUG 0
94527ead 36
26d53979 37#if EHCI_DEBUG
94527ead
GH		 38#define DPRINTF printf
39#else
40#define DPRINTF(...)
41#endif
42
94527ead
GH		 43/* internal processing - reset HC to try and recover */
44#define USB_RET_PROCERR (-99)
45
46#define MMIO_SIZE 0x1000
47
48/* Capability Registers Base Address - section 2.2 */
49#define CAPREGBASE 0x0000
50#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54#define EECP HCCPARAMS + 1
55#define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56#define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58#define OPREGBASE 0x0020 // Operational Registers Base Address
59
60#define USBCMD OPREGBASE + 0x0000
61#define USBCMD_RUNSTOP (1 << 0) // run / Stop
62#define USBCMD_HCRESET (1 << 1) // HC Reset
63#define USBCMD_FLS (3 << 2) // Frame List Size
64#define USBCMD_FLS_SH 2 // Frame List Size Shift
65#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71#define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72#define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74#define USBSTS OPREGBASE + 0x0004
75#define USBSTS_RO_MASK 0x0000003f
76#define USBSTS_INT (1 << 0) // USB Interrupt
77#define USBSTS_ERRINT (1 << 1) // Error Interrupt
78#define USBSTS_PCD (1 << 2) // Port Change Detect
79#define USBSTS_FLR (1 << 3) // Frame List Rollover
80#define USBSTS_HSE (1 << 4) // Host System Error
81#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82#define USBSTS_HALT (1 << 12) // HC Halted
83#define USBSTS_REC (1 << 13) // Reclamation
84#define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87/*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91#define USBINTR OPREGBASE + 0x0008
92#define USBINTR_MASK 0x0000003f
93
94#define FRINDEX OPREGBASE + 0x000c
95#define CTRLDSSEGMENT OPREGBASE + 0x0010
96#define PERIODICLISTBASE OPREGBASE + 0x0014
97#define ASYNCLISTADDR OPREGBASE + 0x0018
98#define ASYNCLISTADDR_MASK 0xffffffe0
99
100#define CONFIGFLAG OPREGBASE + 0x0040
101
102#define PORTSC (OPREGBASE + 0x0044)
103#define PORTSC_BEGIN PORTSC
104#define PORTSC_END (PORTSC + 4 * NB_PORTS)
105/*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109#define PORTSC_RO_MASK 0x007021c5
110#define PORTSC_RWC_MASK 0x0000002a
111#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114#define PORTSC_PTC (15 << 16) // Port Test Control
115#define PORTSC_PTC_SH 16 // Port Test Control shift
116#define PORTSC_PIC (3 << 14) // Port Indicator Control
117#define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118#define PORTSC_POWNER (1 << 13) // Port Owner
119#define PORTSC_PPOWER (1 << 12) // Port Power
120#define PORTSC_LINESTAT (3 << 10) // Port Line Status
121#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122#define PORTSC_PRESET (1 << 8) // Port Reset
123#define PORTSC_SUSPEND (1 << 7) // Port Suspend
124#define PORTSC_FPRES (1 << 6) // Force Port Resume
125#define PORTSC_OCC (1 << 5) // Over Current Change
126#define PORTSC_OCA (1 << 4) // Over Current Active
127#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128#define PORTSC_PED (1 << 2) // Port Enable/Disable
129#define PORTSC_CSC (1 << 1) // Connect Status Change
130#define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132#define FRAME_TIMER_FREQ 1000
133#define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135#define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136#define NB_PORTS 4 // Number of downstream ports
137#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138#define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139#define MAX_QH 100 // Max allowable queue heads in a chain
140
141/* Internal periodic / asynchronous schedule state machine states
142 */
143typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159} EHCI_STATES;
160
161/* macros for accessing fields within next link pointer entry */
162#define NLPTR_GET(x) ((x) & 0xffffffe0)
163#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166/* link pointer types */
167#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168#define NLPTR_TYPE_QH 1 // queue head
169#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170#define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173/* EHCI spec version 1.0 Section 3.3
174 */
175typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179#define ITD_XACT_ACTIVE (1 << 31)
180#define ITD_XACT_DBERROR (1 << 30)
181#define ITD_XACT_BABBLE (1 << 29)
182#define ITD_XACT_XACTERR (1 << 28)
183#define ITD_XACT_LENGTH_MASK 0x0fff0000
184#define ITD_XACT_LENGTH_SH 16
185#define ITD_XACT_IOC (1 << 15)
186#define ITD_XACT_PGSEL_MASK 0x00007000
187#define ITD_XACT_PGSEL_SH 12
188#define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191#define ITD_BUFPTR_MASK 0xfffff000
192#define ITD_BUFPTR_SH 12
193#define ITD_BUFPTR_EP_MASK 0x00000f00
194#define ITD_BUFPTR_EP_SH 8
195#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196#define ITD_BUFPTR_DEVADDR_SH 0
197#define ITD_BUFPTR_DIRECTION (1 << 11)
198#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199#define ITD_BUFPTR_MAXPKT_SH 0
200#define ITD_BUFPTR_MULT_MASK 0x00000003
201} EHCIitd;
202
203/* EHCI spec version 1.0 Section 3.4
204 */
205typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208#define SITD_EPCHAR_IO (1 << 31)
209#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210#define SITD_EPCHAR_PORTNUM_SH 24
211#define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212#define SITD_EPCHAR_HUBADDR_SH 16
213#define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214#define SITD_EPCHAR_EPNUM_SH 8
215#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218#define SITD_UFRAME_CMASK_MASK 0x0000ff00
219#define SITD_UFRAME_CMASK_SH 8
220#define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223#define SITD_RESULTS_IOC (1 << 31)
224#define SITD_RESULTS_PGSEL (1 << 30)
225#define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226#define SITD_RESULTS_TYBYTES_SH 16
227#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228#define SITD_RESULTS_CPROGMASK_SH 8
229#define SITD_RESULTS_ACTIVE (1 << 7)
230#define SITD_RESULTS_ERR (1 << 6)
231#define SITD_RESULTS_DBERR (1 << 5)
232#define SITD_RESULTS_BABBLE (1 << 4)
233#define SITD_RESULTS_XACTERR (1 << 3)
234#define SITD_RESULTS_MISSEDUF (1 << 2)
235#define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238#define SITD_BUFPTR_MASK 0xfffff000
239#define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240#define SITD_BUFPTR_TPOS_MASK 0x00000018
241#define SITD_BUFPTR_TPOS_SH 3
242#define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245} EHCIsitd;
246
247/* EHCI spec version 1.0 Section 3.5
248 */
249typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253#define QTD_TOKEN_DTOGGLE (1 << 31)
254#define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255#define QTD_TOKEN_TBYTES_SH 16
256#define QTD_TOKEN_IOC (1 << 15)
257#define QTD_TOKEN_CPAGE_MASK 0x00007000
258#define QTD_TOKEN_CPAGE_SH 12
259#define QTD_TOKEN_CERR_MASK 0x00000c00
260#define QTD_TOKEN_CERR_SH 10
261#define QTD_TOKEN_PID_MASK 0x00000300
262#define QTD_TOKEN_PID_SH 8
263#define QTD_TOKEN_ACTIVE (1 << 7)
264#define QTD_TOKEN_HALT (1 << 6)
265#define QTD_TOKEN_DBERR (1 << 5)
266#define QTD_TOKEN_BABBLE (1 << 4)
267#define QTD_TOKEN_XACTERR (1 << 3)
268#define QTD_TOKEN_MISSEDUF (1 << 2)
269#define QTD_TOKEN_SPLITXSTATE (1 << 1)
270#define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273#define QTD_BUFPTR_MASK 0xfffff000
274} EHCIqtd;
275
276/* EHCI spec version 1.0 Section 3.6
277 */
278typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283#define QH_EPCHAR_RL_MASK 0xf0000000
284#define QH_EPCHAR_RL_SH 28
285#define QH_EPCHAR_C (1 << 27)
286#define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287#define QH_EPCHAR_MPLEN_SH 16
288#define QH_EPCHAR_H (1 << 15)
289#define QH_EPCHAR_DTC (1 << 14)
290#define QH_EPCHAR_EPS_MASK 0x00003000
291#define QH_EPCHAR_EPS_SH 12
292#define EHCI_QH_EPS_FULL 0
293#define EHCI_QH_EPS_LOW 1
294#define EHCI_QH_EPS_HIGH 2
295#define EHCI_QH_EPS_RESERVED 3
296
297#define QH_EPCHAR_EP_MASK 0x00000f00
298#define QH_EPCHAR_EP_SH 8
299#define QH_EPCHAR_I (1 << 7)
300#define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301#define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305#define QH_EPCAP_MULT_MASK 0xc0000000
306#define QH_EPCAP_MULT_SH 30
307#define QH_EPCAP_PORTNUM_MASK 0x3f800000
308#define QH_EPCAP_PORTNUM_SH 23
309#define QH_EPCAP_HUBADDR_MASK 0x007f0000
310#define QH_EPCAP_HUBADDR_SH 16
311#define QH_EPCAP_CMASK_MASK 0x0000ff00
312#define QH_EPCAP_CMASK_SH 8
313#define QH_EPCAP_SMASK_MASK 0x000000ff
314#define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320#define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324#define BUFPTR_CPROGMASK_MASK 0x000000ff
325#define BUFPTR_FRAMETAG_MASK 0x0000001f
326#define BUFPTR_SBYTES_MASK 0x00000fe0
327#define BUFPTR_SBYTES_SH 5
328} EHCIqh;
329
330/* EHCI spec version 1.0 Section 3.7
331 */
332typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335} EHCIfstn;
336
337typedef struct {
338 PCIDevice dev;
339 qemu_irq irq;
340 target_phys_addr_t mem_base;
341 int mem;
342 int num_ports;
343 /*
344 * EHCI spec version 1.0 Section 2.3
345 * Host Controller Operational Registers
346 */
347 union {
348 uint8_t mmio[MMIO_SIZE];
349 struct {
350 uint8_t cap[OPREGBASE];
351 uint32_t usbcmd;
352 uint32_t usbsts;
353 uint32_t usbintr;
354 uint32_t frindex;
355 uint32_t ctrldssegment;
356 uint32_t periodiclistbase;
357 uint32_t asynclistaddr;
358 uint32_t notused[9];
359 uint32_t configflag;
360 uint32_t portsc[NB_PORTS];
361 };
362 };
363 /*
364 * Internal states, shadow registers, etc
365 */
366 uint32_t sofv;
367 QEMUTimer *frame_timer;
368 int attach_poll_counter;
369 int astate; // Current state in asynchronous schedule
370 int pstate; // Current state in periodic schedule
371 USBPort ports[NB_PORTS];
372 uint8_t buffer[BUFF_SIZE];
373 uint32_t usbsts_pending;
374
375 /* cached data from guest - needs to be flushed
376 * when guest removes an entry (doorbell, handshake sequence)
377 */
378 EHCIqh qh; // copy of current QH (being worked on)
379 uint32_t qhaddr; // address QH read from
380
381 EHCIqtd qtd; // copy of current QTD (being worked on)
382 uint32_t qtdaddr; // address QTD read from
383
384 uint32_t itdaddr; // current ITD
385
386 uint32_t fetch_addr; // which address to look at next
387
388 USBBus bus;
389 USBPacket usb_packet;
390 int async_complete;
391 uint32_t tbytes;
392 int pid;
393 int exec_status;
394 int isoch_pause;
395 uint32_t last_run_usec;
396 uint32_t frame_end_usec;
397} EHCIState;
398
399#define SET_LAST_RUN_CLOCK(s) \
400 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
401
402/* nifty macros from Arnon's EHCI version */
403#define get_field(data, field) \
404 (((data) & field##_MASK) >> field##_SH)
405
406#define set_field(data, newval, field) do { \
407 uint32_t val = *data; \
408 val &= ~ field##_MASK; \
409 val |= ((newval) << field##_SH) & field##_MASK; \
410 *data = val; \
411 } while(0)
412
26d53979
GH		 413static const char *ehci_state_names[] = {
414 [ EST_INACTIVE ] = "INACTIVE",
415 [ EST_ACTIVE ] = "ACTIVE",
416 [ EST_EXECUTING ] = "EXECUTING",
417 [ EST_SLEEPING ] = "SLEEPING",
418 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
419 [ EST_FETCHENTRY ] = "FETCH ENTRY",
420 [ EST_FETCHQH ] = "FETCH QH",
421 [ EST_FETCHITD ] = "FETCH ITD",
422 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
423 [ EST_FETCHQTD ] = "FETCH QTD",
424 [ EST_EXECUTE ] = "EXECUTE",
425 [ EST_WRITEBACK ] = "WRITEBACK",
426 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
427};
428
429static const char *ehci_mmio_names[] = {
430 [ CAPLENGTH ] = "CAPLENGTH",
431 [ HCIVERSION ] = "HCIVERSION",
432 [ HCSPARAMS ] = "HCSPARAMS",
433 [ HCCPARAMS ] = "HCCPARAMS",
434 [ USBCMD ] = "USBCMD",
435 [ USBSTS ] = "USBSTS",
436 [ USBINTR ] = "USBINTR",
437 [ FRINDEX ] = "FRINDEX",
438 [ PERIODICLISTBASE ] = "P-LIST BASE",
439 [ ASYNCLISTADDR ] = "A-LIST ADDR",
440 [ PORTSC_BEGIN ] = "PORTSC #0",
441 [ PORTSC_BEGIN + 4] = "PORTSC #1",
442 [ PORTSC_BEGIN + 8] = "PORTSC #2",
443 [ PORTSC_BEGIN + 12] = "PORTSC #3",
444 [ CONFIGFLAG ] = "CONFIGFLAG",
445};
94527ead 446
26d53979 447static const char *nr2str(const char **n, size_t len, uint32_t nr)
94527ead 448{
26d53979
GH		 449 if (nr < len && n[nr] != NULL) {
450 return n[nr];
94527ead 451 } else {
26d53979 452 return "unknown";
94527ead
GH		 453 }
454}
94527ead 455
26d53979
GH		 456static const char *state2str(uint32_t state)
457{
458 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
459}
460
461static const char *addr2str(target_phys_addr_t addr)
462{
463 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
464}
465
439a97cc
GH		 466static void ehci_trace_usbsts(uint32_t mask, int state)
467{
468 /* interrupts */
469 if (mask & USBSTS_INT) {
470 trace_usb_ehci_usbsts("INT", state);
471 }
472 if (mask & USBSTS_ERRINT) {
473 trace_usb_ehci_usbsts("ERRINT", state);
474 }
475 if (mask & USBSTS_PCD) {
476 trace_usb_ehci_usbsts("PCD", state);
477 }
478 if (mask & USBSTS_FLR) {
479 trace_usb_ehci_usbsts("FLR", state);
480 }
481 if (mask & USBSTS_HSE) {
482 trace_usb_ehci_usbsts("HSE", state);
483 }
484 if (mask & USBSTS_IAA) {
485 trace_usb_ehci_usbsts("IAA", state);
486 }
487
488 /* status */
489 if (mask & USBSTS_HALT) {
490 trace_usb_ehci_usbsts("HALT", state);
491 }
492 if (mask & USBSTS_REC) {
493 trace_usb_ehci_usbsts("REC", state);
494 }
495 if (mask & USBSTS_PSS) {
496 trace_usb_ehci_usbsts("PSS", state);
497 }
498 if (mask & USBSTS_ASS) {
499 trace_usb_ehci_usbsts("ASS", state);
500 }
501}
502
503static inline void ehci_set_usbsts(EHCIState *s, int mask)
504{
505 if ((s->usbsts & mask) == mask) {
506 return;
507 }
508 ehci_trace_usbsts(mask, 1);
509 s->usbsts |= mask;
510}
511
512static inline void ehci_clear_usbsts(EHCIState *s, int mask)
513{
514 if ((s->usbsts & mask) == 0) {
515 return;
516 }
517 ehci_trace_usbsts(mask, 0);
518 s->usbsts &= ~mask;
519}
94527ead
GH		 520
521static inline void ehci_set_interrupt(EHCIState *s, int intr)
522{
523 int level = 0;
524
525 // TODO honour interrupt threshold requests
526
439a97cc 527 ehci_set_usbsts(s, intr);
94527ead
GH		 528
529 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
530 level = 1;
531 }
532
533 qemu_set_irq(s->irq, level);
534}
535
536static inline void ehci_record_interrupt(EHCIState *s, int intr)
537{
538 s->usbsts_pending |= intr;
539}
540
541static inline void ehci_commit_interrupt(EHCIState *s)
542{
543 if (!s->usbsts_pending) {
544 return;
545 }
546 ehci_set_interrupt(s, s->usbsts_pending);
547 s->usbsts_pending = 0;
548}
549
26d53979
GH		 550static void ehci_set_state(EHCIState *s, int async, int state)
551{
552 if (async) {
553 trace_usb_ehci_state("async", state2str(state));
554 s->astate = state;
555 } else {
556 trace_usb_ehci_state("periodic", state2str(state));
557 s->pstate = state;
558 }
559}
560
561static int ehci_get_state(EHCIState *s, int async)
562{
563 return async ? s->astate : s->pstate;
564}
565
566static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)
567{
568 trace_usb_ehci_qh(addr, qh->next,
569 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
570 get_field(qh->epchar, QH_EPCHAR_RL),
571 get_field(qh->epchar, QH_EPCHAR_MPLEN),
572 get_field(qh->epchar, QH_EPCHAR_EPS),
573 get_field(qh->epchar, QH_EPCHAR_EP),
574 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
575 (bool)(qh->epchar & QH_EPCHAR_C),
576 (bool)(qh->epchar & QH_EPCHAR_H),
577 (bool)(qh->epchar & QH_EPCHAR_DTC),
578 (bool)(qh->epchar & QH_EPCHAR_I));
579}
580
581static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)
582{
583 trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,
584 get_field(qtd->token, QTD_TOKEN_TBYTES),
585 get_field(qtd->token, QTD_TOKEN_CPAGE),
586 get_field(qtd->token, QTD_TOKEN_CERR),
587 get_field(qtd->token, QTD_TOKEN_PID),
588 (bool)(qtd->token & QTD_TOKEN_IOC),
589 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
590 (bool)(qtd->token & QTD_TOKEN_HALT),
591 (bool)(qtd->token & QTD_TOKEN_BABBLE),
592 (bool)(qtd->token & QTD_TOKEN_XACTERR));
593}
594
595static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
596{
597 trace_usb_ehci_itd(addr, itd->next);
598}
599
94527ead
GH		 600/* Attach or detach a device on root hub */
601
602static void ehci_attach(USBPort *port)
603{
604 EHCIState *s = port->opaque;
605 uint32_t *portsc = &s->portsc[port->index];
606
dcbd0b5c 607 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
94527ead
GH		 608
609 *portsc |= PORTSC_CONNECT;
610 *portsc |= PORTSC_CSC;
611
612 /*
613 * If a high speed device is attached then we own this port(indicated
614 * by zero in the PORTSC_POWNER bit field) so set the status bit
615 * and set an interrupt if enabled.
616 */
617 if ( !(*portsc & PORTSC_POWNER)) {
618 ehci_set_interrupt(s, USBSTS_PCD);
619 }
620}
621
622static void ehci_detach(USBPort *port)
623{
624 EHCIState *s = port->opaque;
625 uint32_t *portsc = &s->portsc[port->index];
626
dcbd0b5c 627 trace_usb_ehci_port_detach(port->index);
94527ead
GH		 628
629 *portsc &= ~PORTSC_CONNECT;
630 *portsc |= PORTSC_CSC;
631
632 /*
633 * If a high speed device is attached then we own this port(indicated
634 * by zero in the PORTSC_POWNER bit field) so set the status bit
635 * and set an interrupt if enabled.
636 */
637 if ( !(*portsc & PORTSC_POWNER)) {
638 ehci_set_interrupt(s, USBSTS_PCD);
639 }
640}
641
642/* 4.1 host controller initialization */
643static void ehci_reset(void *opaque)
644{
645 EHCIState *s = opaque;
646 uint8_t *pci_conf;
647 int i;
648
439a97cc 649 trace_usb_ehci_reset();
94527ead
GH		 650 pci_conf = s->dev.config;
651
652 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
653
654 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
655 s->usbsts = USBSTS_HALT;
656
657 s->astate = EST_INACTIVE;
658 s->pstate = EST_INACTIVE;
659 s->async_complete = 0;
660 s->isoch_pause = -1;
661 s->attach_poll_counter = 0;
662
663 for(i = 0; i < NB_PORTS; i++) {
664 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
665
666 if (s->ports[i].dev) {
667 usb_attach(&s->ports[i], s->ports[i].dev);
668 }
669 }
670}
671
672static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
673{
674 EHCIState *s = ptr;
675 uint32_t val;
676
677 val = s->mmio[addr];
678
679 return val;
680}
681
682static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
683{
684 EHCIState *s = ptr;
685 uint32_t val;
686
687 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
688
689 return val;
690}
691
692static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
693{
694 EHCIState *s = ptr;
695 uint32_t val;
696
697 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
698 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
699
439a97cc 700 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
94527ead
GH		 701 return val;
702}
703
704static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
705{
706 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
707 exit(1);
708}
709
710static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
711{
712 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
713 exit(1);
714}
715
716static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
717{
718 uint32_t *portsc = &s->portsc[port];
719 int rwc;
720 USBDevice *dev = s->ports[port].dev;
721
94527ead
GH		 722 rwc = val & PORTSC_RWC_MASK;
723 val &= PORTSC_RO_MASK;
724
725 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
726
727 *portsc &= ~rwc;
728
729 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
dcbd0b5c 730 trace_usb_ehci_port_reset(port, 1);
94527ead
GH		 731 }
732
733 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
dcbd0b5c 734 trace_usb_ehci_port_reset(port, 0);
94527ead
GH		 735 usb_attach(&s->ports[port], dev);
736
737 // TODO how to handle reset of ports with no device
738 if (dev) {
739 usb_send_msg(dev, USB_MSG_RESET);
740 }
741
742 if (s->ports[port].dev) {
94527ead
GH		 743 *portsc &= ~PORTSC_CSC;
744 }
745
746 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
747 * to SW that this port has a high speed device attached
748 *
749 * TODO - when to disable?
750 */
751 val |= PORTSC_PED;
752 val |= PORTSC_PEDC;
753 }
754
755 *portsc &= ~PORTSC_RO_MASK;
756 *portsc |= val;
94527ead
GH		 757}
758
759static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
760{
761 EHCIState *s = ptr;
c4f8e211
GH		 762 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
763 uint32_t old = *mmio;
94527ead 764 int i;
439a97cc 765
c4f8e211 766 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
94527ead
GH		 767
768 /* Only aligned reads are allowed on OHCI */
769 if (addr & 3) {
770 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
771 TARGET_FMT_plx "\n", addr);
772 return;
773 }
774
775 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
776 handle_port_status_write(s, (addr-PORTSC)/4, val);
c4f8e211 777 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
94527ead
GH		 778 return;
779 }
780
781 if (addr < OPREGBASE) {
782 fprintf(stderr, "usb-ehci: write attempt to read-only register"
783 TARGET_FMT_plx "\n", addr);
784 return;
785 }
786
787
788 /* Do any register specific pre-write processing here. */
94527ead
GH		 789 switch(addr) {
790 case USBCMD:
94527ead 791 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
94527ead
GH		 792 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
793 SET_LAST_RUN_CLOCK(s);
439a97cc 794 ehci_clear_usbsts(s, USBSTS_HALT);
94527ead
GH		 795 }
796
797 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
94527ead
GH		 798 qemu_del_timer(s->frame_timer);
799 // TODO - should finish out some stuff before setting halt
439a97cc 800 ehci_set_usbsts(s, USBSTS_HALT);
94527ead
GH		 801 }
802
803 if (val & USBCMD_HCRESET) {
94527ead
GH		 804 ehci_reset(s);
805 val &= ~USBCMD_HCRESET;
806 }
807
808 /* not supporting dynamic frame list size at the moment */
809 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
810 fprintf(stderr, "attempt to set frame list size -- value %d\n",
811 val & USBCMD_FLS);
812 val &= ~USBCMD_FLS;
813 }
94527ead
GH		 814 break;
815
94527ead
GH		 816 case USBSTS:
817 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
439a97cc
GH		 818 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
819 val = s->usbsts;
94527ead
GH		 820 ehci_set_interrupt(s, 0);
821 break;
822
94527ead
GH		 823 case USBINTR:
824 val &= USBINTR_MASK;
94527ead
GH		 825 break;
826
827 case FRINDEX:
828 s->sofv = val >> 3;
94527ead
GH		 829 break;
830
831 case CONFIGFLAG:
94527ead
GH		 832 val &= 0x1;
833 if (val) {
834 for(i = 0; i < NB_PORTS; i++)
835 s->portsc[i] &= ~PORTSC_POWNER;
836 }
837 break;
838
839 case PERIODICLISTBASE:
840 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
841 fprintf(stderr,
842 "ehci: PERIODIC list base register set while periodic schedule\n"
843 " is enabled and HC is enabled\n");
844 }
94527ead
GH		 845 break;
846
847 case ASYNCLISTADDR:
848 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
849 fprintf(stderr,
850 "ehci: ASYNC list address register set while async schedule\n"
851 " is enabled and HC is enabled\n");
852 }
94527ead
GH		 853 break;
854 }
855
c4f8e211
GH		 856 *mmio = val;
857 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
94527ead
GH		 858}
859
860
861// TODO : Put in common header file, duplication from usb-ohci.c
862
863/* Get an array of dwords from main memory */
864static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
865{
866 int i;
867
868 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
869 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
870 *buf = le32_to_cpu(*buf);
871 }
872
873 return 1;
874}
875
876/* Put an array of dwords in to main memory */
877static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
878{
879 int i;
880
881 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
882 uint32_t tmp = cpu_to_le32(*buf);
883 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
884 }
885
886 return 1;
887}
888
889// 4.10.2
890
891static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
892{
893 int i;
894 int dtoggle;
895 int ping;
896 int eps;
897 int reload;
898
899 // remember values in fields to preserve in qh after overlay
900
901 dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
902 ping = qh->token & QTD_TOKEN_PING;
903
94527ead
GH		 904 qh->current_qtd = ehci->qtdaddr;
905 qh->next_qtd = qtd->next;
906 qh->altnext_qtd = qtd->altnext;
907 qh->token = qtd->token;
908
909
910 eps = get_field(qh->epchar, QH_EPCHAR_EPS);
911 if (eps == EHCI_QH_EPS_HIGH) {
912 qh->token &= ~QTD_TOKEN_PING;
913 qh->token |= ping;
914 }
915
916 reload = get_field(qh->epchar, QH_EPCHAR_RL);
917 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
918
919 for (i = 0; i < 5; i++) {
920 qh->bufptr[i] = qtd->bufptr[i];
921 }
922
923 if (!(qh->epchar & QH_EPCHAR_DTC)) {
924 // preserve QH DT bit
925 qh->token &= ~QTD_TOKEN_DTOGGLE;
926 qh->token |= dtoggle;
927 }
928
929 qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
930 qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
931
932 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
933
934 return 0;
935}
936
937static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
938{
939 int bufpos = 0;
940 int cpage, offset;
941 uint32_t head;
942 uint32_t tail;
943
944
945 if (!bytes) {
946 return 0;
947 }
948
949 cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
950 if (cpage > 4) {
951 fprintf(stderr, "cpage out of range (%d)\n", cpage);
952 return USB_RET_PROCERR;
953 }
954
955 offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
94527ead
GH		 956
957 do {
958 /* start and end of this page */
959 head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
960 tail = head + ~QTD_BUFPTR_MASK + 1;
961 /* add offset into page */
962 head |= offset;
963
964 if (bytes <= (tail - head)) {
965 tail = head + bytes;
966 }
967
f2c88dc1 968 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
94527ead
GH		 969 cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
970
971 bufpos += (tail - head);
972 bytes -= (tail - head);
973
974 if (bytes > 0) {
975 cpage++;
976 offset = 0;
977 }
978 } while (bytes > 0);
979
980 /* save cpage */
981 set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
982
983 /* save offset into cpage */
984 offset = tail - head;
985 qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
986 qh->bufptr[0] |= offset;
987
988 return 0;
989}
990
991static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
992{
993 EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
994
995 DPRINTF("Async packet complete\n");
996 ehci->async_complete = 1;
997 ehci->exec_status = packet->len;
998}
999
1000static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
1001{
1002 int c_err, reload;
1003
1004 if (ret == USB_RET_ASYNC && !ehci->async_complete) {
1005 DPRINTF("not done yet\n");
1006 return ret;
1007 }
1008
1009 ehci->async_complete = 0;
1010
1011 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1012 ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
1013
1014 if (ret < 0) {
1015err:
1016 /* TO-DO: put this is in a function that can be invoked below as well */
1017 c_err = get_field(qh->token, QTD_TOKEN_CERR);
1018 c_err--;
1019 set_field(&qh->token, c_err, QTD_TOKEN_CERR);
1020
1021 switch(ret) {
1022 case USB_RET_NODEV:
1023 fprintf(stderr, "USB no device\n");
1024 break;
1025 case USB_RET_STALL:
1026 fprintf(stderr, "USB stall\n");
1027 qh->token |= QTD_TOKEN_HALT;
1028 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1029 break;
1030 case USB_RET_NAK:
1031 /* 4.10.3 */
1032 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1033 if ((ehci->pid == USB_TOKEN_IN) && reload) {
1034 int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1035 nakcnt--;
1036 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1037 } else if (!reload) {
1038 return USB_RET_NAK;
1039 }
1040 break;
1041 case USB_RET_BABBLE:
1042 fprintf(stderr, "USB babble TODO\n");
1043 qh->token |= QTD_TOKEN_BABBLE;
1044 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1045 break;
1046 default:
1047 fprintf(stderr, "USB invalid response %d to handle\n", ret);
1048 /* TO-DO: transaction error */
1049 ret = USB_RET_PROCERR;
1050 break;
1051 }
1052 } else {
1053 // DPRINTF("Short packet condition\n");
1054 // TODO check 4.12 for splits
1055
1056 if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
1057 ret = USB_RET_BABBLE;
1058 goto err;
1059 }
1060
1061 if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
1062 if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
1063 return USB_RET_PROCERR;
1064 }
1065 ehci->tbytes -= ret;
1066 } else {
1067 ehci->tbytes = 0;
1068 }
1069
1070 DPRINTF("updating tbytes to %d\n", ehci->tbytes);
1071 set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
1072 }
1073
1074 qh->token ^= QTD_TOKEN_DTOGGLE;
1075 qh->token &= ~QTD_TOKEN_ACTIVE;
1076
1077 if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
1078 ehci_record_interrupt(ehci, USBSTS_INT);
1079 }
1080
1081 return ret;
1082}
1083
1084// 4.10.3
1085
1086static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
1087{
1088 USBPort *port;
1089 USBDevice *dev;
1090 int ret;
1091 int i;
1092 int endp;
1093 int devadr;
1094
1095 if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
1096 fprintf(stderr, "Attempting to execute inactive QH\n");
1097 return USB_RET_PROCERR;
1098 }
1099
1100 ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1101 if (ehci->tbytes > BUFF_SIZE) {
1102 fprintf(stderr, "Request for more bytes than allowed\n");
1103 return USB_RET_PROCERR;
1104 }
1105
1106 ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1107 switch(ehci->pid) {
1108 case 0: ehci->pid = USB_TOKEN_OUT; break;
1109 case 1: ehci->pid = USB_TOKEN_IN; break;
1110 case 2: ehci->pid = USB_TOKEN_SETUP; break;
1111 default: fprintf(stderr, "bad token\n"); break;
1112 }
1113
1114 if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
1115 (ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
1116 return USB_RET_PROCERR;
1117 }
1118
1119 endp = get_field(qh->epchar, QH_EPCHAR_EP);
1120 devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
1121
1122 ret = USB_RET_NODEV;
1123
1124 // TO-DO: associating device with ehci port
1125 for(i = 0; i < NB_PORTS; i++) {
1126 port = &ehci->ports[i];
1127 dev = port->dev;
1128
1129 // TODO sometime we will also need to check if we are the port owner
1130
1131 if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
1132 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1133 i, ehci->portsc[i]);
1134 continue;
1135 }
1136
1137 ehci->usb_packet.pid = ehci->pid;
1138 ehci->usb_packet.devaddr = devadr;
1139 ehci->usb_packet.devep = endp;
1140 ehci->usb_packet.data = ehci->buffer;
1141 ehci->usb_packet.len = ehci->tbytes;
1142
1143 ret = usb_handle_packet(dev, &ehci->usb_packet);
1144
1145 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1146 ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
1147 ehci->usb_packet.len, ehci->tbytes, endp, ret);
1148
1149 if (ret != USB_RET_NODEV) {
1150 break;
1151 }
1152 }
1153
1154 if (ret > BUFF_SIZE) {
1155 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1156 return USB_RET_PROCERR;
1157 }
1158
1159 if (ret == USB_RET_ASYNC) {
1160 ehci->async_complete = 0;
1161 }
1162
1163 return ret;
1164}
1165
1166/* 4.7.2
1167 */
1168
1169static int ehci_process_itd(EHCIState *ehci,
1170 EHCIitd *itd)
1171{
1172 USBPort *port;
1173 USBDevice *dev;
1174 int ret;
1175 int i, j;
1176 int ptr;
1177 int pid;
1178 int pg;
1179 int len;
1180 int dir;
1181 int devadr;
1182 int endp;
1183 int maxpkt;
1184
1185 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1186 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1187 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1188 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1189
1190 for(i = 0; i < 8; i++) {
1191 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1192 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1193 ehci->frindex >> 3, i);
1194
1195 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1196 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1197 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1198 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1199
1200 if (len > BUFF_SIZE) {
1201 return USB_RET_PROCERR;
1202 }
1203
1204 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1205
1206 if (!dir) {
1207 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
1208 pid = USB_TOKEN_OUT;
1209 } else
1210 pid = USB_TOKEN_IN;
1211
1212 ret = USB_RET_NODEV;
1213
1214 for (j = 0; j < NB_PORTS; j++) {
1215 port = &ehci->ports[j];
1216 dev = port->dev;
1217
1218 // TODO sometime we will also need to check if we are the port owner
1219
1220 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1221 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1222 j, ehci->portsc[j]);
1223 continue;
1224 }
1225
1226 ehci->usb_packet.pid = ehci->pid;
1227 ehci->usb_packet.devaddr = devadr;
1228 ehci->usb_packet.devep = endp;
1229 ehci->usb_packet.data = ehci->buffer;
1230 ehci->usb_packet.len = len;
1231
1232 DPRINTF("calling usb_handle_packet\n");
1233 ret = usb_handle_packet(dev, &ehci->usb_packet);
1234
1235 if (ret != USB_RET_NODEV) {
1236 break;
1237 }
1238 }
1239
1240 /* In isoch, there is no facility to indicate a NAK so let's
1241 * instead just complete a zero-byte transaction. Setting
1242 * DBERR seems too draconian.
1243 */
1244
1245 if (ret == USB_RET_NAK) {
1246 if (ehci->isoch_pause > 0) {
1247 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1248 ehci->isoch_pause--;
1249 return 0;
1250 } else if (ehci->isoch_pause == -1) {
1251 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1252 // Pause frindex for up to 50 msec waiting for data from
1253 // remote
1254 ehci->isoch_pause = 50;
1255 return 0;
1256 } else {
1257 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1258 ret = 0;
1259 }
1260 } else {
1261 DPRINTF("ISOCH: received ACK, clearing pause\n");
1262 ehci->isoch_pause = -1;
1263 }
1264
1265 if (ret >= 0) {
1266 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1267
1268 if (itd->transact[i] & ITD_XACT_IOC) {
1269 ehci_record_interrupt(ehci, USBSTS_INT);
1270 }
1271 }
1272
1273 if (ret >= 0 && dir) {
1274 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
1275
1276 if (ret != len) {
1277 DPRINTF("ISOCH IN expected %d, got %d\n",
1278 len, ret);
1279 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1280 }
1281 }
1282 }
1283 }
1284 return 0;
1285}
1286
1287/* This state is the entry point for asynchronous schedule
1288 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1289 */
26d53979 1290static int ehci_state_waitlisthead(EHCIState *ehci, int async)
94527ead
GH		 1291{
1292 EHCIqh *qh = &ehci->qh;
1293 int i = 0;
1294 int again = 0;
1295 uint32_t entry = ehci->asynclistaddr;
1296
1297 /* set reclamation flag at start event (4.8.6) */
1298 if (async) {
439a97cc 1299 ehci_set_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1300 }
1301
1302 /* Find the head of the list (4.9.1.1) */
1303 for(i = 0; i < MAX_QH; i++) {
1304 get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
26d53979 1305 ehci_trace_qh(ehci, NLPTR_GET(entry), qh);
94527ead
GH		 1306
1307 if (qh->epchar & QH_EPCHAR_H) {
94527ead
GH		 1308 if (async) {
1309 entry |= (NLPTR_TYPE_QH << 1);
1310 }
1311
1312 ehci->fetch_addr = entry;
26d53979 1313 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1314 again = 1;
1315 goto out;
1316 }
1317
94527ead
GH		 1318 entry = qh->next;
1319 if (entry == ehci->asynclistaddr) {
94527ead
GH		 1320 break;
1321 }
1322 }
1323
1324 /* no head found for list. */
1325
26d53979 1326 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1327
1328out:
1329 return again;
1330}
1331
1332
1333/* This state is the entry point for periodic schedule processing as
1334 * well as being a continuation state for async processing.
1335 */
26d53979 1336static int ehci_state_fetchentry(EHCIState *ehci, int async)
94527ead
GH		 1337{
1338 int again = 0;
1339 uint32_t entry = ehci->fetch_addr;
1340
1341#if EHCI_DEBUG == 0
1342 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1343 if (async) {
1344 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1345 goto out;
1346 } else {
1347 DPRINTF("FETCHENTRY: WARNING "
1348 "- frame timer elapsed during periodic\n");
1349 }
1350 }
1351#endif
1352 if (entry < 0x1000) {
1353 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
26d53979 1354 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1355 goto out;
1356 }
1357
1358 /* section 4.8, only QH in async schedule */
1359 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1360 fprintf(stderr, "non queue head request in async schedule\n");
1361 return -1;
1362 }
1363
1364 switch (NLPTR_TYPE_GET(entry)) {
1365 case NLPTR_TYPE_QH:
26d53979 1366 ehci_set_state(ehci, async, EST_FETCHQH);
94527ead
GH		 1367 ehci->qhaddr = entry;
1368 again = 1;
1369 break;
1370
1371 case NLPTR_TYPE_ITD:
26d53979 1372 ehci_set_state(ehci, async, EST_FETCHITD);
94527ead
GH		 1373 ehci->itdaddr = entry;
1374 again = 1;
1375 break;
1376
1377 default:
1378 // TODO: handle siTD and FSTN types
1379 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1380 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1381 return -1;
1382 }
1383
1384out:
1385 return again;
1386}
1387
26d53979 1388static int ehci_state_fetchqh(EHCIState *ehci, int async)
94527ead
GH		 1389{
1390 EHCIqh *qh = &ehci->qh;
1391 int reload;
1392 int again = 0;
1393
1394 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
26d53979 1395 ehci_trace_qh(ehci, NLPTR_GET(ehci->qhaddr), qh);
94527ead
GH		 1396
1397 if (async && (qh->epchar & QH_EPCHAR_H)) {
1398
1399 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1400 if (ehci->usbsts & USBSTS_REC) {
439a97cc 1401 ehci_clear_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1402 } else {
1403 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1404 " - done processing\n", ehci->qhaddr);
26d53979 1405 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1406 goto out;
1407 }
1408 }
1409
1410#if EHCI_DEBUG
1411 if (ehci->qhaddr != qh->next) {
1412 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1413 ehci->qhaddr,
1414 qh->epchar & QH_EPCHAR_H,
1415 qh->token & QTD_TOKEN_HALT,
1416 qh->token & QTD_TOKEN_ACTIVE,
1417 qh->next);
1418 }
1419#endif
1420
1421 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1422 if (reload) {
94527ead
GH		 1423 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1424 }
1425
1426 if (qh->token & QTD_TOKEN_HALT) {
26d53979 1427 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1428 again = 1;
1429
1430 } else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
94527ead 1431 ehci->qtdaddr = qh->current_qtd;
26d53979 1432 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1433 again = 1;
1434
1435 } else {
1436 /* EHCI spec version 1.0 Section 4.10.2 */
26d53979 1437 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
94527ead
GH		 1438 again = 1;
1439 }
1440
1441out:
1442 return again;
1443}
1444
26d53979 1445static int ehci_state_fetchitd(EHCIState *ehci, int async)
94527ead
GH		 1446{
1447 EHCIitd itd;
1448
1449 get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
1450 sizeof(EHCIitd) >> 2);
26d53979 1451 ehci_trace_itd(ehci, ehci->itdaddr, &itd);
94527ead
GH		 1452
1453 if (ehci_process_itd(ehci, &itd) != 0) {
1454 return -1;
1455 }
1456
1457 put_dwords(NLPTR_GET(ehci->itdaddr), (uint32_t *) &itd,
1458 sizeof(EHCIitd) >> 2);
1459 ehci->fetch_addr = itd.next;
26d53979 1460 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1461
1462 return 1;
1463}
1464
1465/* Section 4.10.2 - paragraph 3 */
26d53979 1466static int ehci_state_advqueue(EHCIState *ehci, int async)
94527ead
GH		 1467{
1468#if 0
1469 /* TO-DO: 4.10.2 - paragraph 2
1470 * if I-bit is set to 1 and QH is not active
1471 * go to horizontal QH
1472 */
1473 if (I-bit set) {
26d53979 1474 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1475 goto out;
1476 }
1477#endif
1478
1479 /*
1480 * want data and alt-next qTD is valid
1481 */
1482 if (((ehci->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1483 (ehci->qh.altnext_qtd > 0x1000) &&
1484 (NLPTR_TBIT(ehci->qh.altnext_qtd) == 0)) {
94527ead 1485 ehci->qtdaddr = ehci->qh.altnext_qtd;
26d53979 1486 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1487
1488 /*
1489 * next qTD is valid
1490 */
1491 } else if ((ehci->qh.next_qtd > 0x1000) &&
1492 (NLPTR_TBIT(ehci->qh.next_qtd) == 0)) {
94527ead 1493 ehci->qtdaddr = ehci->qh.next_qtd;
26d53979 1494 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1495
1496 /*
1497 * no valid qTD, try next QH
1498 */
1499 } else {
26d53979 1500 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1501 }
1502
1503 return 1;
1504}
1505
1506/* Section 4.10.2 - paragraph 4 */
26d53979 1507static int ehci_state_fetchqtd(EHCIState *ehci, int async)
94527ead
GH		 1508{
1509 EHCIqtd *qtd = &ehci->qtd;
1510 int again = 0;
1511
1512 get_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) qtd, sizeof(EHCIqtd) >> 2);
26d53979 1513 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), qtd);
94527ead
GH		 1514
1515 if (qtd->token & QTD_TOKEN_ACTIVE) {
26d53979 1516 ehci_set_state(ehci, async, EST_EXECUTE);
94527ead
GH		 1517 again = 1;
1518 } else {
26d53979 1519 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1520 again = 1;
1521 }
1522
1523 return again;
1524}
1525
26d53979 1526static int ehci_state_horizqh(EHCIState *ehci, int async)
94527ead
GH		 1527{
1528 int again = 0;
1529
1530 if (ehci->fetch_addr != ehci->qh.next) {
1531 ehci->fetch_addr = ehci->qh.next;
26d53979 1532 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1533 again = 1;
1534 } else {
26d53979 1535 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1536 }
1537
1538 return again;
1539}
1540
26d53979 1541static int ehci_state_execute(EHCIState *ehci, int async)
94527ead
GH		 1542{
1543 EHCIqh *qh = &ehci->qh;
1544 EHCIqtd *qtd = &ehci->qtd;
1545 int again = 0;
1546 int reload, nakcnt;
1547 int smask;
1548
94527ead
GH		 1549 if (ehci_qh_do_overlay(ehci, qh, qtd) != 0) {
1550 return -1;
1551 }
1552
1553 smask = get_field(qh->epcap, QH_EPCAP_SMASK);
1554
1555 if (!smask) {
1556 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1557 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1558 if (reload && !nakcnt) {
26d53979 1559 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1560 again = 1;
1561 goto out;
1562 }
1563 }
1564
1565 // TODO verify enough time remains in the uframe as in 4.4.1.1
1566 // TODO write back ptr to async list when done or out of time
1567 // TODO Windows does not seem to ever set the MULT field
1568
1569 if (!async) {
1570 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1571 if (!transactCtr) {
26d53979 1572 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1573 again = 1;
1574 goto out;
1575 }
1576 }
1577
1578 if (async) {
439a97cc 1579 ehci_set_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1580 }
1581
1582 ehci->exec_status = ehci_execute(ehci, qh);
1583 if (ehci->exec_status == USB_RET_PROCERR) {
1584 again = -1;
1585 goto out;
1586 }
26d53979 1587 ehci_set_state(ehci, async, EST_EXECUTING);
94527ead
GH		 1588
1589 if (ehci->exec_status != USB_RET_ASYNC) {
1590 again = 1;
1591 }
1592
1593out:
1594 return again;
1595}
1596
26d53979 1597static int ehci_state_executing(EHCIState *ehci, int async)
94527ead
GH		 1598{
1599 EHCIqh *qh = &ehci->qh;
1600 int again = 0;
1601 int reload, nakcnt;
1602
1603 ehci->exec_status = ehci_execute_complete(ehci, qh, ehci->exec_status);
1604 if (ehci->exec_status == USB_RET_ASYNC) {
1605 goto out;
1606 }
1607 if (ehci->exec_status == USB_RET_PROCERR) {
1608 again = -1;
1609 goto out;
1610 }
1611
1612 // 4.10.3
1613 if (!async) {
1614 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1615 transactCtr--;
1616 set_field(&qh->epcap, transactCtr, QH_EPCAP_MULT);
1617 // 4.10.3, bottom of page 82, should exit this state when transaction
1618 // counter decrements to 0
1619 }
1620
1621
1622 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1623 if (reload) {
1624 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1625 if (ehci->exec_status == USB_RET_NAK) {
1626 if (nakcnt) {
1627 nakcnt--;
1628 }
94527ead
GH		 1629 } else {
1630 nakcnt = reload;
94527ead
GH		 1631 }
1632 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1633 }
1634
1635 /*
1636 * Write the qh back to guest physical memory. This step isn't
1637 * in the EHCI spec but we need to do it since we don't share
1638 * physical memory with our guest VM.
1639 */
94527ead
GH		 1640 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1641
1642 /* 4.10.5 */
1643 if ((ehci->exec_status == USB_RET_NAK) || (qh->token & QTD_TOKEN_ACTIVE)) {
26d53979 1644 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead 1645 } else {
26d53979 1646 ehci_set_state(ehci, async, EST_WRITEBACK);
94527ead
GH		 1647 }
1648
1649 again = 1;
1650
1651out:
1652 return again;
1653}
1654
1655
26d53979 1656static int ehci_state_writeback(EHCIState *ehci, int async)
94527ead
GH		 1657{
1658 EHCIqh *qh = &ehci->qh;
1659 int again = 0;
1660
1661 /* Write back the QTD from the QH area */
26d53979 1662 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), (EHCIqtd*) &qh->next_qtd);
94527ead
GH		 1663 put_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) &qh->next_qtd,
1664 sizeof(EHCIqtd) >> 2);
1665
1666 /* TODO confirm next state. For now, keep going if async
1667 * but stop after one qtd if periodic
1668 */
1669 //if (async) {
26d53979 1670 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
94527ead
GH		 1671 again = 1;
1672 //} else {
26d53979 1673 // ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1674 //}
1675 return again;
1676}
1677
1678/*
1679 * This is the state machine that is common to both async and periodic
1680 */
1681
26d53979
GH		 1682static void ehci_advance_state(EHCIState *ehci,
1683 int async)
94527ead
GH		 1684{
1685 int again;
1686 int iter = 0;
1687
1688 do {
26d53979 1689 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
94527ead
GH		 1690 iter++;
1691 /* if we are roaming a lot of QH without executing a qTD
1692 * something is wrong with the linked list. TO-DO: why is
1693 * this hack needed?
1694 */
1695 if (iter > MAX_ITERATIONS) {
1696 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
26d53979 1697 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1698 break;
1699 }
1700 }
26d53979 1701 switch(ehci_get_state(ehci, async)) {
94527ead 1702 case EST_WAITLISTHEAD:
26d53979 1703 again = ehci_state_waitlisthead(ehci, async);
94527ead
GH		 1704 break;
1705
1706 case EST_FETCHENTRY:
26d53979 1707 again = ehci_state_fetchentry(ehci, async);
94527ead
GH		 1708 break;
1709
1710 case EST_FETCHQH:
26d53979 1711 again = ehci_state_fetchqh(ehci, async);
94527ead
GH		 1712 break;
1713
1714 case EST_FETCHITD:
26d53979 1715 again = ehci_state_fetchitd(ehci, async);
94527ead
GH		 1716 break;
1717
1718 case EST_ADVANCEQUEUE:
26d53979 1719 again = ehci_state_advqueue(ehci, async);
94527ead
GH		 1720 break;
1721
1722 case EST_FETCHQTD:
26d53979 1723 again = ehci_state_fetchqtd(ehci, async);
94527ead
GH		 1724 break;
1725
1726 case EST_HORIZONTALQH:
26d53979 1727 again = ehci_state_horizqh(ehci, async);
94527ead
GH		 1728 break;
1729
1730 case EST_EXECUTE:
1731 iter = 0;
26d53979 1732 again = ehci_state_execute(ehci, async);
94527ead
GH		 1733 break;
1734
1735 case EST_EXECUTING:
26d53979 1736 again = ehci_state_executing(ehci, async);
94527ead
GH		 1737 break;
1738
1739 case EST_WRITEBACK:
26d53979 1740 again = ehci_state_writeback(ehci, async);
94527ead
GH		 1741 break;
1742
1743 default:
1744 fprintf(stderr, "Bad state!\n");
1745 again = -1;
1746 break;
1747 }
1748
1749 if (again < 0) {
1750 fprintf(stderr, "processing error - resetting ehci HC\n");
1751 ehci_reset(ehci);
1752 again = 0;
1753 }
1754 }
1755 while (again);
1756
1757 ehci_commit_interrupt(ehci);
94527ead
GH		 1758}
1759
1760static void ehci_advance_async_state(EHCIState *ehci)
1761{
1762 EHCIqh qh;
26d53979 1763 int async = 1;
94527ead 1764
26d53979 1765 switch(ehci_get_state(ehci, async)) {
94527ead
GH		 1766 case EST_INACTIVE:
1767 if (!(ehci->usbcmd & USBCMD_ASE)) {
1768 break;
1769 }
439a97cc 1770 ehci_set_usbsts(ehci, USBSTS_ASS);
26d53979 1771 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1772 // No break, fall through to ACTIVE
1773
1774 case EST_ACTIVE:
1775 if ( !(ehci->usbcmd & USBCMD_ASE)) {
439a97cc 1776 ehci_clear_usbsts(ehci, USBSTS_ASS);
26d53979 1777 ehci_set_state(ehci, async, EST_INACTIVE);
94527ead
GH		 1778 break;
1779 }
1780
1781 /* If the doorbell is set, the guest wants to make a change to the
1782 * schedule. The host controller needs to release cached data.
1783 * (section 4.8.2)
1784 */
1785 if (ehci->usbcmd & USBCMD_IAAD) {
1786 DPRINTF("ASYNC: doorbell request acknowledged\n");
1787 ehci->usbcmd &= ~USBCMD_IAAD;
1788 ehci_set_interrupt(ehci, USBSTS_IAA);
1789 break;
1790 }
1791
1792 /* make sure guest has acknowledged */
1793 /* TO-DO: is this really needed? */
1794 if (ehci->usbsts & USBSTS_IAA) {
1795 DPRINTF("IAA status bit still set.\n");
1796 break;
1797 }
1798
94527ead
GH		 1799 /* check that address register has been set */
1800 if (ehci->asynclistaddr == 0) {
1801 break;
1802 }
1803
26d53979 1804 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
94527ead
GH		 1805 /* fall through */
1806
1807 case EST_FETCHENTRY:
1808 /* fall through */
1809
1810 case EST_EXECUTING:
1811 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) &qh,
1812 sizeof(EHCIqh) >> 2);
26d53979 1813 ehci_advance_state(ehci, async);
94527ead
GH		 1814 break;
1815
1816 default:
1817 /* this should only be due to a developer mistake */
1818 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1819 "Resetting to active\n", ehci->astate);
26d53979 1820 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1821 }
1822}
1823
1824static void ehci_advance_periodic_state(EHCIState *ehci)
1825{
1826 uint32_t entry;
1827 uint32_t list;
26d53979 1828 int async = 0;
94527ead
GH		 1829
1830 // 4.6
1831
26d53979 1832 switch(ehci_get_state(ehci, async)) {
94527ead
GH		 1833 case EST_INACTIVE:
1834 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
439a97cc 1835 ehci_set_usbsts(ehci, USBSTS_PSS);
26d53979 1836 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1837 // No break, fall through to ACTIVE
1838 } else
1839 break;
1840
1841 case EST_ACTIVE:
1842 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
439a97cc 1843 ehci_clear_usbsts(ehci, USBSTS_PSS);
26d53979 1844 ehci_set_state(ehci, async, EST_INACTIVE);
94527ead
GH		 1845 break;
1846 }
1847
1848 list = ehci->periodiclistbase & 0xfffff000;
1849 /* check that register has been set */
1850 if (list == 0) {
1851 break;
1852 }
1853 list |= ((ehci->frindex & 0x1ff8) >> 1);
1854
1855 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1856 entry = le32_to_cpu(entry);
1857
1858 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1859 ehci->frindex / 8, list, entry);
1860 ehci->fetch_addr = entry;
26d53979
GH		 1861 ehci_set_state(ehci, async, EST_FETCHENTRY);
1862 ehci_advance_state(ehci, async);
94527ead
GH		 1863 break;
1864
1865 case EST_EXECUTING:
1866 DPRINTF("PERIODIC state adv for executing\n");
26d53979 1867 ehci_advance_state(ehci, async);
94527ead
GH		 1868 break;
1869
1870 default:
1871 /* this should only be due to a developer mistake */
1872 fprintf(stderr, "ehci: Bad periodic state %d. "
1873 "Resetting to active\n", ehci->pstate);
26d53979 1874 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1875 }
1876}
1877
1878static void ehci_frame_timer(void *opaque)
1879{
1880 EHCIState *ehci = opaque;
1881 int64_t expire_time, t_now;
1882 int usec_elapsed;
1883 int frames;
1884 int usec_now;
1885 int i;
1886 int skipped_frames = 0;
1887
1888
1889 t_now = qemu_get_clock_ns(vm_clock);
1890 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1891 if (expire_time == t_now) {
1892 expire_time++;
1893 }
1894
1895 usec_now = t_now / 1000;
1896 usec_elapsed = usec_now - ehci->last_run_usec;
1897 frames = usec_elapsed / FRAME_TIMER_USEC;
1898 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1899
1900 for (i = 0; i < frames; i++) {
1901 if ( !(ehci->usbsts & USBSTS_HALT)) {
1902 if (ehci->isoch_pause <= 0) {
1903 ehci->frindex += 8;
1904 }
1905
1906 if (ehci->frindex > 0x00001fff) {
1907 ehci->frindex = 0;
1908 ehci_set_interrupt(ehci, USBSTS_FLR);
1909 }
1910
1911 ehci->sofv = (ehci->frindex - 1) >> 3;
1912 ehci->sofv &= 0x000003ff;
1913 }
1914
1915 if (frames - i > 10) {
1916 skipped_frames++;
1917 } else {
1918 // TODO could this cause periodic frames to get skipped if async
1919 // active?
26d53979 1920 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
94527ead
GH		 1921 ehci_advance_periodic_state(ehci);
1922 }
1923 }
1924
1925 ehci->last_run_usec += FRAME_TIMER_USEC;
1926 }
1927
1928#if 0
1929 if (skipped_frames) {
1930 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1931 }
1932#endif
1933
1934 /* Async is not inside loop since it executes everything it can once
1935 * called
1936 */
26d53979 1937 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
94527ead
GH		 1938 ehci_advance_async_state(ehci);
1939 }
1940
1941 qemu_mod_timer(ehci->frame_timer, expire_time);
1942}
1943
1944static CPUReadMemoryFunc *ehci_readfn[3]={
1945 ehci_mem_readb,
1946 ehci_mem_readw,
1947 ehci_mem_readl
1948};
1949
1950static CPUWriteMemoryFunc *ehci_writefn[3]={
1951 ehci_mem_writeb,
1952 ehci_mem_writew,
1953 ehci_mem_writel
1954};
1955
1956static void ehci_map(PCIDevice *pci_dev, int region_num,
1957 pcibus_t addr, pcibus_t size, int type)
1958{
1959 EHCIState *s =(EHCIState *)pci_dev;
1960
1961 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1962 region_num, addr, size, s->mem);
1963 s->mem_base = addr;
1964 cpu_register_physical_memory(addr, size, s->mem);
1965}
1966
1967static int usb_ehci_initfn(PCIDevice *dev);
1968
1969static USBPortOps ehci_port_ops = {
1970 .attach = ehci_attach,
1971 .detach = ehci_detach,
1972 .complete = ehci_async_complete_packet,
1973};
1974
1975static PCIDeviceInfo ehci_info = {
1976 .qdev.name = "usb-ehci",
1977 .qdev.size = sizeof(EHCIState),
1978 .init = usb_ehci_initfn,
1979};
1980
1981static int usb_ehci_initfn(PCIDevice *dev)
1982{
1983 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
1984 uint8_t *pci_conf = s->dev.config;
1985 int i;
1986
1987 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1988 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
1989 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
1990 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
1991 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1992 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
1993
1994 /* capabilities pointer */
1995 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
1996 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
1997
1998 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
1999 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2000 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2001
2002 // pci_conf[0x50] = 0x01; // power management caps
2003
2004 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2005 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2006 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2007
2008 pci_conf[0x64] = 0x00;
2009 pci_conf[0x65] = 0x00;
2010 pci_conf[0x66] = 0x00;
2011 pci_conf[0x67] = 0x00;
2012 pci_conf[0x68] = 0x01;
2013 pci_conf[0x69] = 0x00;
2014 pci_conf[0x6a] = 0x00;
2015 pci_conf[0x6b] = 0x00; // USBLEGSUP
2016 pci_conf[0x6c] = 0x00;
2017 pci_conf[0x6d] = 0x00;
2018 pci_conf[0x6e] = 0x00;
2019 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2020
2021 // 2.2 host controller interface version
2022 s->mmio[0x00] = (uint8_t) OPREGBASE;
2023 s->mmio[0x01] = 0x00;
2024 s->mmio[0x02] = 0x00;
2025 s->mmio[0x03] = 0x01; // HC version
2026 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2027 s->mmio[0x05] = 0x00; // No companion ports at present
2028 s->mmio[0x06] = 0x00;
2029 s->mmio[0x07] = 0x00;
2030 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2031 s->mmio[0x09] = 0x68; // EECP
2032 s->mmio[0x0a] = 0x00;
2033 s->mmio[0x0b] = 0x00;
2034
2035 s->irq = s->dev.irq[3];
2036
2037 usb_bus_new(&s->bus, &s->dev.qdev);
2038 for(i = 0; i < NB_PORTS; i++) {
2039 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2040 USB_SPEED_MASK_HIGH);
2041 usb_port_location(&s->ports[i], NULL, i+1);
2042 s->ports[i].dev = 0;
2043 }
2044
2045 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2046
2047 qemu_register_reset(ehci_reset, s);
2048
2049 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2050 DEVICE_LITTLE_ENDIAN);
2051
2052 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2053 ehci_map);
2054
2055 fprintf(stderr, "*** EHCI support is under development ***\n");
2056
2057 return 0;
2058}
2059
2060static void ehci_register(void)
2061{
2062 pci_qdev_register(&ehci_info);
2063}
2064device_init(ehci_register);
2065
2066/*
2067 * vim: expandtab ts=4
2068 */
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