[qemu.git] / hw / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "hw.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "net.h"
#include "sysemu.h"
#include "pci.h"
#include "boards.h"

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  uint32_t base;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  qemu_irq *parent;
  int irq;
} vpb_sic_state;

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    offset -= s->base;
    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    offset -= s->base;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static CPUReadMemoryFunc *vpb_sic_readfn[] = {
   vpb_sic_read,
   vpb_sic_read,
   vpb_sic_read
};

static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
   vpb_sic_write,
   vpb_sic_write,
   vpb_sic_write
};

static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
{
    vpb_sic_state *s;
    qemu_irq *qi;
    int iomemtype;

    s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
    if (!s)
        return NULL;
    qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
    s->base = base;
    s->parent = parent;
    s->irq = irq;
    iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
                                       vpb_sic_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    /* ??? Save/restore.  */
    return qi;
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherans and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(int ram_size, int vga_ram_size,
                     const char *boot_device, DisplayState *ds,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     int board_id)
{
    CPUState *env;
    qemu_irq *pic;
    qemu_irq *sic;
    void *scsi_hba;
    PCIBus *pci_bus;
    NICInfo *nd;
    int n;
    int done_smc = 0;
    int index;

    if (!cpu_model)
        cpu_model = "arm926";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    /* ??? RAM shoud repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    arm_sysctl_init(0x10000000, 0x41007004);
    pic = arm_pic_init_cpu(env);
    pic = pl190_init(0x10140000, pic[0], pic[1]);
    sic = vpb_sic_init(0x10003000, pic, 31);
    pl050_init(0x10006000, sic[3], 0);
    pl050_init(0x10007000, sic[4], 1);

    pci_bus = pci_vpb_init(sic, 27, 0);
    /* The Versatile PCI bridge does not provide access to PCI IO space,
       so many of the qemu PCI devices are not useable.  */
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
            nd->model = done_smc ? "rtl8139" : "smc91c111";
        if (strcmp(nd->model, "smc91c111") == 0) {
            smc91c111_init(nd, 0x10010000, sic[25]);
        } else {
            pci_nic_init(pci_bus, nd, -1);
        }
    }
    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, 3, -1);
    }
    if (drive_get_max_bus(IF_SCSI) > 0) {
        fprintf(stderr, "qemu: too many SCSI bus\n");
        exit(1);
    }
    scsi_hba = lsi_scsi_init(pci_bus, -1);
    for (n = 0; n < LSI_MAX_DEVS; n++) {
        index = drive_get_index(IF_SCSI, 0, n);
        if (index == -1)
            continue;
        lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n);
    }

    pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM);
    pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM);
    pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM);
    pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM);

    pl080_init(0x10130000, pic[17], 8);
    sp804_init(0x101e2000, pic[4]);
    sp804_init(0x101e3000, pic[5]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    pl110_init(ds, 0x10120000, pic[16], 1);

    index = drive_get_index(IF_SD, 0, 0);
    if (index == -1) {
        fprintf(stderr, "qemu: missing SecureDigital card\n");
        exit(1);
    }

    pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]);
#if 0
    /* Disabled because there's no way of specifying a block device.  */
    pl181_init(0x1000b000, NULL, sic, 23, 2);
#endif

    /* Add PL031 Real Time Clock. */
    pl031_init(0x101e8000,pic[10]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */

    versatile_binfo.ram_size = ram_size;
    versatile_binfo.kernel_filename = kernel_filename;
    versatile_binfo.kernel_cmdline = kernel_cmdline;
    versatile_binfo.initrd_filename = initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(env, &versatile_binfo);
}

static void vpb_init(int ram_size, int vga_ram_size,
                     const char *boot_device, DisplayState *ds,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size, vga_ram_size,
                   boot_device, ds,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x183);
}

static void vab_init(int ram_size, int vga_ram_size,
                     const char *boot_device, DisplayState *ds,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size, vga_ram_size,
                   boot_device, ds,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x25e);
}

QEMUMachine versatilepb_machine = {
    "versatilepb",
    "ARM Versatile/PB (ARM926EJ-S)",
    vpb_init,
};

QEMUMachine versatileab_machine = {
    "versatileab",
    "ARM Versatile/AB (ARM926EJ-S)",
    vab_init,
};
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
87ecb68b PB	10	#include "hw.h"
	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "net.h"
	15	#include "sysemu.h"
	16	#include "pci.h"
	17	#include "boards.h"
cdbdb648	18
cdbdb648 PB	19	/* Primary interrupt controller. */
	20
	21	typedef struct vpb_sic_state
	22	{
cdbdb648 PB	23	uint32_t base;
	24	uint32_t level;
	25	uint32_t mask;
	26	uint32_t pic_enable;
d537cf6c	27	qemu_irq *parent;
cdbdb648 PB	28	int irq;
	29	} vpb_sic_state;
	30
	31	static void vpb_sic_update(vpb_sic_state *s)
	32	{
	33	uint32_t flags;
	34
	35	flags = s->level & s->mask;
d537cf6c	36	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	37	}
	38
	39	static void vpb_sic_update_pic(vpb_sic_state *s)
	40	{
	41	int i;
	42	uint32_t mask;
	43
	44	for (i = 21; i <= 30; i++) {
	45	mask = 1u << i;
	46	if (!(s->pic_enable & mask))
	47	continue;
d537cf6c	48	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	49	}
	50	}
	51
	52	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	53	{
	54	vpb_sic_state s = (vpb_sic_state )opaque;
	55	if (level)
	56	s->level \|= 1u << irq;
	57	else
	58	s->level &= ~(1u << irq);
	59	if (s->pic_enable & (1u << irq))
d537cf6c	60	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	61	vpb_sic_update(s);
	62	}
	63
	64	static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
	65	{
	66	vpb_sic_state s = (vpb_sic_state )opaque;
	67
	68	offset -= s->base;
	69	switch (offset >> 2) {
	70	case 0: /* STATUS */
	71	return s->level & s->mask;
	72	case 1: /* RAWSTAT */
	73	return s->level;
	74	case 2: /* ENABLE */
	75	return s->mask;
	76	case 4: /* SOFTINT */
	77	return s->level & 1;
	78	case 8: /* PICENABLE */
	79	return s->pic_enable;
	80	default:
e69954b9	81	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	82	return 0;
	83	}
	84	}
	85
	86	static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
	87	uint32_t value)
	88	{
	89	vpb_sic_state s = (vpb_sic_state )opaque;
	90	offset -= s->base;
	91
	92	switch (offset >> 2) {
	93	case 2: /* ENSET */
	94	s->mask \|= value;
	95	break;
	96	case 3: /* ENCLR */
	97	s->mask &= ~value;
	98	break;
	99	case 4: /* SOFTINTSET */
	100	if (value)
	101	s->mask \|= 1;
	102	break;
	103	case 5: /* SOFTINTCLR */
	104	if (value)
	105	s->mask &= ~1u;
	106	break;
	107	case 8: /* PICENSET */
	108	s->pic_enable \|= (value & 0x7fe00000);
	109	vpb_sic_update_pic(s);
	110	break;
	111	case 9: /* PICENCLR */
	112	s->pic_enable &= ~value;
	113	vpb_sic_update_pic(s);
	114	break;
	115	default:
e69954b9	116	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	117	return;
	118	}
	119	vpb_sic_update(s);
	120	}
	121
	122	static CPUReadMemoryFunc *vpb_sic_readfn[] = {
	123	vpb_sic_read,
	124	vpb_sic_read,
	125	vpb_sic_read
	126	};
	127
	128	static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
	129	vpb_sic_write,
	130	vpb_sic_write,
	131	vpb_sic_write
	132	};
	133
d537cf6c	134	static qemu_irq vpb_sic_init(uint32_t base, qemu_irq parent, int irq)
cdbdb648 PB	135	{
cdbdb648 PB	136	vpb_sic_state *s;
d537cf6c	137	qemu_irq *qi;
cdbdb648 PB	138	int iomemtype;
	139
	140	s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
	141	if (!s)
	142	return NULL;
d537cf6c	143	qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
cdbdb648 PB	144	s->base = base;
	145	s->parent = parent;
	146	s->irq = irq;
	147	iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
	148	vpb_sic_writefn, s);
187337f8	149	cpu_register_physical_memory(base, 0x00001000, iomemtype);
cdbdb648	150	/* ??? Save/restore. */
d537cf6c	151	return qi;
cdbdb648 PB	152	}
	153
	154	/* Board init. */
	155
16406950 PB	156	/* The AB and PB boards both use the same core, just with different
	157	peripherans and expansion busses. For now we emulate a subset of the
	158	PB peripherals and just change the board ID. */
cdbdb648	159
f93eb9ff AZ	160	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	161
6ac0e82d AZ	162	static void versatile_init(int ram_size, int vga_ram_size,
6ac0e82d AZ	163	const char boot_device, DisplayState ds,
cdbdb648	164	const char kernel_filename, const char kernel_cmdline,
3371d272 PB	165	const char initrd_filename, const char cpu_model,
3371d272 PB	166	int board_id)
cdbdb648 PB	167	{
cdbdb648 PB	168	CPUState *env;
d537cf6c PB	169	qemu_irq *pic;
d537cf6c PB	170	qemu_irq *sic;
7d8406be	171	void *scsi_hba;
502a5395 PB	172	PCIBus *pci_bus;
	173	NICInfo *nd;
	174	int n;
	175	int done_smc = 0;
e4bcb14c	176	int index;
cdbdb648	177
3371d272 PB	178	if (!cpu_model)
3371d272 PB	179	cpu_model = "arm926";
aaed909a FB	180	env = cpu_init(cpu_model);
	181	if (!env) {
	182	fprintf(stderr, "Unable to find CPU definition\n");
	183	exit(1);
	184	}
cdbdb648 PB	185	/* ??? RAM shoud repeat to fill physical memory space. */
	186	/* SDRAM at address zero. */
	187	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	188
e69954b9	189	arm_sysctl_init(0x10000000, 0x41007004);
cdbdb648	190	pic = arm_pic_init_cpu(env);
d537cf6c	191	pic = pl190_init(0x10140000, pic[0], pic[1]);
cdbdb648	192	sic = vpb_sic_init(0x10003000, pic, 31);
d537cf6c PB	193	pl050_init(0x10006000, sic[3], 0);
d537cf6c PB	194	pl050_init(0x10007000, sic[4], 1);
cdbdb648	195
e69954b9	196	pci_bus = pci_vpb_init(sic, 27, 0);
502a5395 PB	197	/* The Versatile PCI bridge does not provide access to PCI IO space,
	198	so many of the qemu PCI devices are not useable. */
	199	for(n = 0; n < nb_nics; n++) {
	200	nd = &nd_table[n];
	201	if (!nd->model)
	202	nd->model = done_smc ? "rtl8139" : "smc91c111";
	203	if (strcmp(nd->model, "smc91c111") == 0) {
d537cf6c	204	smc91c111_init(nd, 0x10010000, sic[25]);
cdbdb648	205	} else {
abcebc7e	206	pci_nic_init(pci_bus, nd, -1);
cdbdb648 PB	207	}
cdbdb648 PB	208	}
0d92ed30	209	if (usb_enabled) {
e24ad6f1	210	usb_ohci_init_pci(pci_bus, 3, -1);
0d92ed30	211	}
e4bcb14c TS	212	if (drive_get_max_bus(IF_SCSI) > 0) {
	213	fprintf(stderr, "qemu: too many SCSI bus\n");
	214	exit(1);
	215	}
7d8406be	216	scsi_hba = lsi_scsi_init(pci_bus, -1);
e4bcb14c TS	217	for (n = 0; n < LSI_MAX_DEVS; n++) {
	218	index = drive_get_index(IF_SCSI, 0, n);
	219	if (index == -1)
	220	continue;
	221	lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n);
7d8406be	222	}
cdbdb648	223
9ee6e8bb PB	224	pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM);
	225	pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM);
	226	pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM);
	227	pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM);
cdbdb648	228
d537cf6c PB	229	pl080_init(0x10130000, pic[17], 8);
	230	sp804_init(0x101e2000, pic[4]);
	231	sp804_init(0x101e3000, pic[5]);
cdbdb648 PB	232
	233	/* The versatile/PB actually has a modified Color LCD controller
	234	that includes hardware cursor support from the PL111. */
d537cf6c	235	pl110_init(ds, 0x10120000, pic[16], 1);
cdbdb648	236
e4bcb14c TS	237	index = drive_get_index(IF_SD, 0, 0);
	238	if (index == -1) {
	239	fprintf(stderr, "qemu: missing SecureDigital card\n");
	240	exit(1);
	241	}
	242
	243	pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]);
a1bb27b1 PB	244	#if 0
	245	/* Disabled because there's no way of specifying a block device. */
	246	pl181_init(0x1000b000, NULL, sic, 23, 2);
	247	#endif
	248
7e1543c2 PB	249	/* Add PL031 Real Time Clock. */
	250	pl031_init(0x101e8000,pic[10]);
	251
16406950	252	/* Memory map for Versatile/PB: */
cdbdb648 PB	253	/* 0x10000000 System registers. */
	254	/* 0x10001000 PCI controller config registers. */
	255	/* 0x10002000 Serial bus interface. */
	256	/* 0x10003000 Secondary interrupt controller. */
	257	/* 0x10004000 AACI (audio). */
a1bb27b1	258	/* 0x10005000 MMCI0. */
cdbdb648 PB	259	/* 0x10006000 KMI0 (keyboard). */
	260	/* 0x10007000 KMI1 (mouse). */
	261	/* 0x10008000 Character LCD Interface. */
	262	/* 0x10009000 UART3. */
	263	/* 0x1000a000 Smart card 1. */
a1bb27b1	264	/* 0x1000b000 MMCI1. */
cdbdb648 PB	265	/* 0x10010000 Ethernet. */
	266	/* 0x10020000 USB. */
	267	/* 0x10100000 SSMC. */
	268	/* 0x10110000 MPMC. */
	269	/* 0x10120000 CLCD Controller. */
	270	/* 0x10130000 DMA Controller. */
	271	/* 0x10140000 Vectored interrupt controller. */
	272	/* 0x101d0000 AHB Monitor Interface. */
	273	/* 0x101e0000 System Controller. */
	274	/* 0x101e1000 Watchdog Interface. */
	275	/* 0x101e2000 Timer 0/1. */
	276	/* 0x101e3000 Timer 2/3. */
	277	/* 0x101e4000 GPIO port 0. */
	278	/* 0x101e5000 GPIO port 1. */
	279	/* 0x101e6000 GPIO port 2. */
	280	/* 0x101e7000 GPIO port 3. */
	281	/* 0x101e8000 RTC. */
	282	/* 0x101f0000 Smart card 0. */
	283	/* 0x101f1000 UART0. */
	284	/* 0x101f2000 UART1. */
	285	/* 0x101f3000 UART2. */
	286	/* 0x101f4000 SSPI. */
	287
f93eb9ff AZ	288	versatile_binfo.ram_size = ram_size;
	289	versatile_binfo.kernel_filename = kernel_filename;
	290	versatile_binfo.kernel_cmdline = kernel_cmdline;
	291	versatile_binfo.initrd_filename = initrd_filename;
	292	versatile_binfo.board_id = board_id;
	293	arm_load_kernel(env, &versatile_binfo);
16406950 PB	294	}
16406950 PB	295
b881c2c6 BS	296	static void vpb_init(int ram_size, int vga_ram_size,
b881c2c6 BS	297	const char boot_device, DisplayState ds,
16406950	298	const char kernel_filename, const char kernel_cmdline,
94fc95cd	299	const char initrd_filename, const char cpu_model)
16406950	300	{
b881c2c6 BS	301	versatile_init(ram_size, vga_ram_size,
b881c2c6 BS	302	boot_device, ds,
16406950	303	kernel_filename, kernel_cmdline,
3371d272	304	initrd_filename, cpu_model, 0x183);
16406950 PB	305	}
16406950 PB	306
b881c2c6 BS	307	static void vab_init(int ram_size, int vga_ram_size,
b881c2c6 BS	308	const char boot_device, DisplayState ds,
16406950	309	const char kernel_filename, const char kernel_cmdline,
94fc95cd	310	const char initrd_filename, const char cpu_model)
16406950	311	{
b881c2c6 BS	312	versatile_init(ram_size, vga_ram_size,
b881c2c6 BS	313	boot_device, ds,
16406950	314	kernel_filename, kernel_cmdline,
3371d272	315	initrd_filename, cpu_model, 0x25e);
cdbdb648 PB	316	}
	317
	318	QEMUMachine versatilepb_machine = {
	319	"versatilepb",
	320	"ARM Versatile/PB (ARM926EJ-S)",
	321	vpb_init,
	322	};
16406950 PB	323
	324	QEMUMachine versatileab_machine = {
	325	"versatileab",
	326	"ARM Versatile/AB (ARM926EJ-S)",
	327	vab_init,
	328	};