[qemu.git] / hw / ioapic.c

/*
 *  ioapic.c IOAPIC emulation logic
 *
 *  Copyright (c) 2004-2005 Fabrice Bellard
 *
 *  Split the ioapic logic from apic.c
 *  Xiantao Zhang <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw.h"
#include "pc.h"
#include "apic.h"
#include "qemu-timer.h"
#include "host-utils.h"

//#define DEBUG_IOAPIC

#define IOAPIC_NUM_PINS			0x18
#define IOAPIC_LVT_MASKED 		(1<<16)

#define IOAPIC_TRIGGER_EDGE		0
#define IOAPIC_TRIGGER_LEVEL		1

/*io{apic,sapic} delivery mode*/
#define IOAPIC_DM_FIXED			0x0
#define IOAPIC_DM_LOWEST_PRIORITY	0x1
#define IOAPIC_DM_PMI			0x2
#define IOAPIC_DM_NMI			0x4
#define IOAPIC_DM_INIT			0x5
#define IOAPIC_DM_SIPI			0x5
#define IOAPIC_DM_EXTINT		0x7

struct IOAPICState {
    uint8_t id;
    uint8_t ioregsel;

    uint32_t irr;
    uint64_t ioredtbl[IOAPIC_NUM_PINS];
};

static void ioapic_service(IOAPICState *s)
{
    uint8_t i;
    uint8_t trig_mode;
    uint8_t vector;
    uint8_t delivery_mode;
    uint32_t mask;
    uint64_t entry;
    uint8_t dest;
    uint8_t dest_mode;
    uint8_t polarity;

    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
        mask = 1 << i;
        if (s->irr & mask) {
            entry = s->ioredtbl[i];
            if (!(entry & IOAPIC_LVT_MASKED)) {
                trig_mode = ((entry >> 15) & 1);
                dest = entry >> 56;
                dest_mode = (entry >> 11) & 1;
                delivery_mode = (entry >> 8) & 7;
                polarity = (entry >> 13) & 1;
                if (trig_mode == IOAPIC_TRIGGER_EDGE)
                    s->irr &= ~mask;
                if (delivery_mode == IOAPIC_DM_EXTINT)
                    vector = pic_read_irq(isa_pic);
                else
                    vector = entry & 0xff;

                apic_deliver_irq(dest, dest_mode, delivery_mode,
                                 vector, polarity, trig_mode);
            }
        }
    }
}

void ioapic_set_irq(void *opaque, int vector, int level)
{
    IOAPICState *s = opaque;

    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
     * to GSI 2.  GSI maps to ioapic 1-1.  This is not
     * the cleanest way of doing it but it should work. */

    if (vector == 0)
        vector = 2;

    if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
        uint32_t mask = 1 << vector;
        uint64_t entry = s->ioredtbl[vector];

        if ((entry >> 15) & 1) {
            /* level triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            } else {
                s->irr &= ~mask;
            }
        } else {
            /* edge triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            }
        }
    }
}

static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
{
    IOAPICState *s = opaque;
    int index;
    uint32_t val = 0;

    addr &= 0xff;
    if (addr == 0x00) {
        val = s->ioregsel;
    } else if (addr == 0x10) {
        switch (s->ioregsel) {
            case 0x00:
                val = s->id << 24;
                break;
            case 0x01:
                val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
                break;
            case 0x02:
                val = 0;
                break;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1)
                        val = s->ioredtbl[index] >> 32;
                    else
                        val = s->ioredtbl[index] & 0xffffffff;
                }
        }
#ifdef DEBUG_IOAPIC
        printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
#endif
    }
    return val;
}

static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    IOAPICState *s = opaque;
    int index;

    addr &= 0xff;
    if (addr == 0x00)  {
        s->ioregsel = val;
        return;
    } else if (addr == 0x10) {
#ifdef DEBUG_IOAPIC
        printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
#endif
        switch (s->ioregsel) {
            case 0x00:
                s->id = (val >> 24) & 0xff;
                return;
            case 0x01:
            case 0x02:
                return;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1) {
                        s->ioredtbl[index] &= 0xffffffff;
                        s->ioredtbl[index] |= (uint64_t)val << 32;
                    } else {
                        s->ioredtbl[index] &= ~0xffffffffULL;
                        s->ioredtbl[index] |= val;
                    }
                    ioapic_service(s);
                }
        }
    }
}

static const VMStateDescription vmstate_ioapic = {
    .name = "ioapic",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(id, IOAPICState),
        VMSTATE_UINT8(ioregsel, IOAPICState),
        VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
        VMSTATE_END_OF_LIST()
    }
};

static void ioapic_reset(void *opaque)
{
    IOAPICState *s = opaque;
    int i;

    memset(s, 0, sizeof(*s));
    for(i = 0; i < IOAPIC_NUM_PINS; i++)
        s->ioredtbl[i] = 1 << 16; /* mask LVT */
}

static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
    ioapic_mem_readl,
    ioapic_mem_readl,
    ioapic_mem_readl,
};

static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
    ioapic_mem_writel,
    ioapic_mem_writel,
    ioapic_mem_writel,
};

qemu_irq *ioapic_init(void)
{
    IOAPICState *s;
    qemu_irq *irq;
    int io_memory;

    s = qemu_mallocz(sizeof(IOAPICState));
    ioapic_reset(s);

    io_memory = cpu_register_io_memory(ioapic_mem_read,
                                       ioapic_mem_write, s);
    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

    vmstate_register(0, &vmstate_ioapic, s);
    qemu_register_reset(ioapic_reset, s);
    irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);

    return irq;
}
Commit	Line	Data
610626af AL	1	/*
	2	* ioapic.c IOAPIC emulation logic
	3	*
	4	* Copyright (c) 2004-2005 Fabrice Bellard
	5	*
	6	* Split the ioapic logic from apic.c
	7	* Xiantao Zhang <[email protected]>
	8	*
	9	* This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU Lesser General Public
	11	* License as published by the Free Software Foundation; either
	12	* version 2 of the License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* Lesser General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU Lesser General Public
8167ee88	20	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
610626af AL	21	*/
	22
	23	#include "hw.h"
	24	#include "pc.h"
aa28b9bf	25	#include "apic.h"
610626af AL	26	#include "qemu-timer.h"
	27	#include "host-utils.h"
	28
	29	//#define DEBUG_IOAPIC
	30
	31	#define IOAPIC_NUM_PINS 0x18
	32	#define IOAPIC_LVT_MASKED (1<<16)
	33
	34	#define IOAPIC_TRIGGER_EDGE 0
	35	#define IOAPIC_TRIGGER_LEVEL 1
	36
	37	/io{apic,sapic} delivery mode/
	38	#define IOAPIC_DM_FIXED 0x0
	39	#define IOAPIC_DM_LOWEST_PRIORITY 0x1
	40	#define IOAPIC_DM_PMI 0x2
	41	#define IOAPIC_DM_NMI 0x4
	42	#define IOAPIC_DM_INIT 0x5
	43	#define IOAPIC_DM_SIPI 0x5
	44	#define IOAPIC_DM_EXTINT 0x7
	45
	46	struct IOAPICState {
	47	uint8_t id;
	48	uint8_t ioregsel;
	49
	50	uint32_t irr;
	51	uint64_t ioredtbl[IOAPIC_NUM_PINS];
	52	};
	53
	54	static void ioapic_service(IOAPICState *s)
	55	{
	56	uint8_t i;
	57	uint8_t trig_mode;
	58	uint8_t vector;
	59	uint8_t delivery_mode;
	60	uint32_t mask;
	61	uint64_t entry;
	62	uint8_t dest;
	63	uint8_t dest_mode;
	64	uint8_t polarity;
	65
	66	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	67	mask = 1 << i;
	68	if (s->irr & mask) {
	69	entry = s->ioredtbl[i];
	70	if (!(entry & IOAPIC_LVT_MASKED)) {
	71	trig_mode = ((entry >> 15) & 1);
	72	dest = entry >> 56;
	73	dest_mode = (entry >> 11) & 1;
	74	delivery_mode = (entry >> 8) & 7;
	75	polarity = (entry >> 13) & 1;
	76	if (trig_mode == IOAPIC_TRIGGER_EDGE)
	77	s->irr &= ~mask;
	78	if (delivery_mode == IOAPIC_DM_EXTINT)
	79	vector = pic_read_irq(isa_pic);
	80	else
	81	vector = entry & 0xff;
	82
	83	apic_deliver_irq(dest, dest_mode, delivery_mode,
	84	vector, polarity, trig_mode);
	85	}
	86	}
	87	}
	88	}
	89
90	void ioapic_set_irq(void *opaque, int vector, int level)
91	{
92	IOAPICState *s = opaque;
93
94	/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
95	* to GSI 2. GSI maps to ioapic 1-1. This is not
96	* the cleanest way of doing it but it should work. */
97
98	if (vector == 0)
99	vector = 2;
100
101	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
102	uint32_t mask = 1 << vector;
103	uint64_t entry = s->ioredtbl[vector];
104
105	if ((entry >> 15) & 1) {
106	/* level triggered */
107	if (level) {
108	s->irr \|= mask;
109	ioapic_service(s);
110	} else {
111	s->irr &= ~mask;
112	}
113	} else {
114	/* edge triggered */
115	if (level) {
116	s->irr \|= mask;
117	ioapic_service(s);
118	}
119	}
120	}
121	}
122
c227f099	123	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
610626af AL	124	{
	125	IOAPICState *s = opaque;
	126	int index;
	127	uint32_t val = 0;
	128
	129	addr &= 0xff;
	130	if (addr == 0x00) {
	131	val = s->ioregsel;
	132	} else if (addr == 0x10) {
	133	switch (s->ioregsel) {
	134	case 0x00:
	135	val = s->id << 24;
	136	break;
	137	case 0x01:
	138	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
	139	break;
	140	case 0x02:
	141	val = 0;
	142	break;
	143	default:
	144	index = (s->ioregsel - 0x10) >> 1;
	145	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	146	if (s->ioregsel & 1)
	147	val = s->ioredtbl[index] >> 32;
	148	else
	149	val = s->ioredtbl[index] & 0xffffffff;
	150	}
	151	}
	152	#ifdef DEBUG_IOAPIC
	153	printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
	154	#endif
	155	}
	156	return val;
	157	}
	158
c227f099	159	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
610626af AL	160	{
	161	IOAPICState *s = opaque;
	162	int index;
	163
	164	addr &= 0xff;
	165	if (addr == 0x00) {
	166	s->ioregsel = val;
	167	return;
	168	} else if (addr == 0x10) {
	169	#ifdef DEBUG_IOAPIC
	170	printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
	171	#endif
	172	switch (s->ioregsel) {
	173	case 0x00:
	174	s->id = (val >> 24) & 0xff;
	175	return;
	176	case 0x01:
	177	case 0x02:
	178	return;
	179	default:
	180	index = (s->ioregsel - 0x10) >> 1;
	181	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	182	if (s->ioregsel & 1) {
	183	s->ioredtbl[index] &= 0xffffffff;
	184	s->ioredtbl[index] \|= (uint64_t)val << 32;
	185	} else {
	186	s->ioredtbl[index] &= ~0xffffffffULL;
	187	s->ioredtbl[index] \|= val;
	188	}
	189	ioapic_service(s);
	190	}
	191	}
	192	}
	193	}
	194
3e9e9888 JQ	195	static const VMStateDescription vmstate_ioapic = {
	196	.name = "ioapic",
	197	.version_id = 1,
	198	.minimum_version_id = 1,
	199	.minimum_version_id_old = 1,
	200	.fields = (VMStateField []) {
	201	VMSTATE_UINT8(id, IOAPICState),
	202	VMSTATE_UINT8(ioregsel, IOAPICState),
	203	VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
	204	VMSTATE_END_OF_LIST()
610626af	205	}
3e9e9888	206	};
610626af AL	207
	208	static void ioapic_reset(void *opaque)
	209	{
	210	IOAPICState *s = opaque;
	211	int i;
	212
	213	memset(s, 0, sizeof(*s));
	214	for(i = 0; i < IOAPIC_NUM_PINS; i++)
	215	s->ioredtbl[i] = 1 << 16; /* mask LVT */
	216	}
	217
d60efc6b	218	static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
610626af AL	219	ioapic_mem_readl,
	220	ioapic_mem_readl,
	221	ioapic_mem_readl,
	222	};
	223
d60efc6b	224	static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
610626af AL	225	ioapic_mem_writel,
	226	ioapic_mem_writel,
	227	ioapic_mem_writel,
	228	};
	229
1632dc6a	230	qemu_irq *ioapic_init(void)
610626af AL	231	{
610626af AL	232	IOAPICState *s;
1632dc6a	233	qemu_irq *irq;
610626af AL	234	int io_memory;
	235
	236	s = qemu_mallocz(sizeof(IOAPICState));
	237	ioapic_reset(s);
	238
1eed09cb	239	io_memory = cpu_register_io_memory(ioapic_mem_read,
610626af AL	240	ioapic_mem_write, s);
	241	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
	242
3e9e9888	243	vmstate_register(0, &vmstate_ioapic, s);
a08d4367	244	qemu_register_reset(ioapic_reset, s);
1632dc6a	245	irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);
610626af	246
1632dc6a	247	return irq;
610626af	248	}