[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "dyngen-exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    TranslationBlock *tb;
    CPUCRISState *saved_env;
    int ret;

    saved_env = env;
    env = env1;

    D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
          env->pc, env->debug1, (void *)retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            tb = tb_find_pc(retaddr);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, retaddr);

		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags();
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}

#endif

void helper_raise_exception(uint32_t index)
{
	env->exception_index = index;
        cpu_loop_exit(env);
}

void helper_tlb_flush_pid(uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
				tlb_flush_page(env, vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUCRISState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

    /* Always set the M flag.  */
    env->pregs[PR_CCS] |= M_FLAG;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void  helper_evaluate_flags(void)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(void)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
			env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
			env->pregs[PR_CCS] = helper_evaluate_flags_muls(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
			env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_4(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_2(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
					helper_evaluate_flags_sub_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
				helper_evaluate_flags();
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_alu_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
786c02f1	23	#include "mmu.h"
30abcfc7	24	#include "helper.h"
c38ac98d	25	#include "host-utils.h"
81fdc5f8	26
d12d51d5 AL	27	//#define CRIS_OP_HELPER_DEBUG
	28
	29
	30	#ifdef CRIS_OP_HELPER_DEBUG
	31	#define D(x) x
93fcfe39	32	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	33	#else
e2eef170	34	#define D(x)
d12d51d5 AL	35	#define D_LOG(...) do { } while (0)
d12d51d5 AL	36	#endif
e2eef170 PB	37
e2eef170 PB	38	#if !defined(CONFIG_USER_ONLY)
3e457172	39	#include "softmmu_exec.h"
e2eef170	40
81fdc5f8	41	#define MMUSUFFIX _mmu
81fdc5f8 TS	42
	43	#define SHIFT 0
	44	#include "softmmu_template.h"
	45
	46	#define SHIFT 1
	47	#include "softmmu_template.h"
	48
	49	#define SHIFT 2
	50	#include "softmmu_template.h"
	51
	52	#define SHIFT 3
	53	#include "softmmu_template.h"
	54
	55	/* Try to fill the TLB and return an exception if error. If retaddr is
	56	NULL, it means that the function was called in C code (i.e. not
	57	from generated code or from helper.c) */
	58	/* XXX: fix it to restore all registers */
a1170bfd	59	void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
20503968	60	uintptr_t retaddr)
81fdc5f8 TS	61	{
81fdc5f8 TS	62	TranslationBlock *tb;
a1170bfd	63	CPUCRISState *saved_env;
81fdc5f8 TS	64	int ret;
81fdc5f8 TS	65
81fdc5f8	66	saved_env = env;
bccd9ec5	67	env = env1;
b41f7df0	68
20503968 BS	69	D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
20503968 BS	70	env->pc, env->debug1, (void *)retaddr);
97b348e7	71	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
551bd27f	72	if (unlikely(ret)) {
81fdc5f8 TS	73	if (retaddr) {
81fdc5f8 TS	74	/* now we have a real cpu fault */
20503968	75	tb = tb_find_pc(retaddr);
81fdc5f8 TS	76	if (tb) {
	77	/* the PC is inside the translated code. It means that we have
	78	a virtual CPU fault */
20503968	79	cpu_restore_state(tb, env, retaddr);
30abcfc7 EI	80
	81	/* Evaluate flags after retranslation. */
	82	helper_top_evaluate_flags();
81fdc5f8 TS	83	}
81fdc5f8 TS	84	}
1162c041	85	cpu_loop_exit(env);
81fdc5f8 TS	86	}
	87	env = saved_env;
	88	}
	89
e2eef170 PB	90	#endif
e2eef170 PB	91
dceaf394	92	void helper_raise_exception(uint32_t index)
786c02f1	93	{
dceaf394	94	env->exception_index = index;
1162c041	95	cpu_loop_exit(env);
786c02f1 EI	96	}
786c02f1 EI	97
cf1d97f0 EI	98	void helper_tlb_flush_pid(uint32_t pid)
	99	{
	100	#if !defined(CONFIG_USER_ONLY)
28de16da EI	101	pid &= 0xff;
	102	if (pid != (env->pregs[PR_PID] & 0xff))
	103	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	104	#endif
	105	}
	106
a1aebcb8 EI	107	void helper_spc_write(uint32_t new_spc)
	108	{
	109	#if !defined(CONFIG_USER_ONLY)
	110	tlb_flush_page(env, env->pregs[PR_SPC]);
	111	tlb_flush_page(env, new_spc);
	112	#endif
	113	}
	114
30abcfc7	115	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	116	{
93fcfe39	117	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	118	}
b41f7df0 EI	119
cf1d97f0 EI	120	/* Used by the tlb decoder. */
	121	#define EXTRACT_FIELD(src, start, end) \
	122	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	123
dceaf394 EI	124	void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
	125	{
	126	uint32_t srs;
	127	srs = env->pregs[PR_SRS];
	128	srs &= 3;
	129	env->sregs[srs][sreg] = env->regs[reg];
	130
	131	#if !defined(CONFIG_USER_ONLY)
	132	if (srs == 1 \|\| srs == 2) {
	133	if (sreg == 6) {
	134	/* Writes to tlb-hi write to mm_cause as a side
	135	effect. */
6913ba56 EI	136	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	137	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	138	}
	139	else if (sreg == 5) {
	140	uint32_t set;
	141	uint32_t idx;
	142	uint32_t lo, hi;
	143	uint32_t vaddr;
cf1d97f0	144	int tlb_v;
dceaf394 EI	145
	146	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	147	set >>= 4;
	148	set &= 3;
	149
	150	idx &= 15;
	151	/* We've just made a write to tlb_lo. */
	152	lo = env->sregs[SFR_RW_MM_TLB_LO];
	153	/* Writes are done via r_mm_cause. */
	154	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	155
	156	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	157	13, 31);
	158	vaddr <<= TARGET_PAGE_BITS;
	159	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	160	3, 3);
dceaf394 EI	161	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	162	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	163
d12d51d5 AL	164	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	165	vaddr, tlb_v, env->pc);
3e18c6bf EI	166	if (tlb_v) {
	167	tlb_flush_page(env, vaddr);
	168	}
dceaf394 EI	169	}
	170	}
	171	#endif
	172	}
	173
	174	void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
	175	{
	176	uint32_t srs;
	177	env->pregs[PR_SRS] &= 3;
	178	srs = env->pregs[PR_SRS];
	179
	180	#if !defined(CONFIG_USER_ONLY)
	181	if (srs == 1 \|\| srs == 2)
	182	{
	183	uint32_t set;
	184	uint32_t idx;
	185	uint32_t lo, hi;
	186
	187	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	188	set >>= 4;
	189	set &= 3;
	190	idx &= 15;
	191
	192	/* Update the mirror regs. */
	193	hi = env->tlbsets[srs - 1][set][idx].hi;
	194	lo = env->tlbsets[srs - 1][set][idx].lo;
	195	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	196	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	197	}
	198	#endif
	199	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	200	}
dceaf394 EI	201
a1170bfd	202	static void cris_ccs_rshift(CPUCRISState *env)
dceaf394 EI	203	{
	204	uint32_t ccs;
	205
	206	/* Apply the ccs shift. */
	207	ccs = env->pregs[PR_CCS];
	208	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	209	if (ccs & U_FLAG)
	210	{
	211	/* Enter user mode. */
	212	env->ksp = env->regs[R_SP];
	213	env->regs[R_SP] = env->pregs[PR_USP];
	214	}
	215
	216	env->pregs[PR_CCS] = ccs;
	217	}
	218
b41f7df0 EI	219	void helper_rfe(void)
b41f7df0 EI	220	{
bf443337 EI	221	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	222
d12d51d5	223	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	224	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	225	env->pregs[PR_CCS],
d12d51d5	226	env->btarget);
dceaf394 EI	227
	228	cris_ccs_rshift(env);
	229
	230	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	231	if (!rflag)
dceaf394	232	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	233	}
b41f7df0 EI	234
5bf8f1ab EI	235	void helper_rfn(void)
	236	{
	237	int rflag = env->pregs[PR_CCS] & R_FLAG;
	238
d12d51d5	239	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	240	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	241	env->pregs[PR_CCS],
d12d51d5	242	env->btarget);
5bf8f1ab EI	243
	244	cris_ccs_rshift(env);
	245
	246	/* Set the P_FLAG only if the R_FLAG is not set. */
	247	if (!rflag)
	248	env->pregs[PR_CCS] \|= P_FLAG;
	249
	250	/* Always set the M flag. */
	251	env->pregs[PR_CCS] \|= M_FLAG;
	252	}
	253
c38ac98d EI	254	uint32_t helper_lz(uint32_t t0)
	255	{
	256	return clz32(t0);
	257	}
	258
abd5c94e EI	259	uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
	260	{
	261	/* FIXME: clean this up. */
	262
	263	/* des ref:
	264	The N flag is set according to the selected bit in the dest reg.
	265	The Z flag is set if the selected bit and all bits to the right are
	266	zero.
	267	The X flag is cleared.
	268	Other flags are left untouched.
	269	The destination reg is not affected.*/
	270	unsigned int fz, sbit, bset, mask, masked_t0;
	271
	272	sbit = t1 & 31;
	273	bset = !!(t0 & (1 << sbit));
	274	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	275	masked_t0 = t0 & mask;
	276	fz = !(masked_t0 \| bset);
	277
	278	/* Clear the X, N and Z flags. */
	279	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	280	if (env->pregs[PR_VR] < 32)
95475216 EI	281	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	282	/* Set the N and Z flags accordingly. */
	283	ccs \|= (bset << 3) \| (fz << 2);
	284	return ccs;
	285	}
	286
6231868b	287	static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
b41f7df0	288	{
a8cf66bb	289	unsigned int x, z, mask;
b41f7df0 EI	290
b41f7df0 EI	291	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	292	x = env->cc_x;
a8cf66bb EI	293	mask = env->cc_mask \| X_FLAG;
	294	if (x) {
	295	z = flags & Z_FLAG;
	296	mask = mask & ~z;
	297	}
	298	flags &= mask;
b41f7df0 EI	299
b41f7df0 EI	300	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	301	ccs &= ~mask;
	302	ccs \|= flags;
	303	return ccs;
b41f7df0 EI	304	}
b41f7df0 EI	305
6231868b	306	uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	307	{
b41f7df0	308	uint32_t flags = 0;
dceaf394	309	int64_t tmp;
b41f7df0 EI	310	int dneg;
b41f7df0 EI	311
b41f7df0 EI	312	dneg = ((int32_t)res) < 0;
b41f7df0 EI	313
dceaf394 EI	314	tmp = mof;
	315	tmp <<= 32;
	316	tmp \|= res;
b41f7df0 EI	317	if (tmp == 0)
	318	flags \|= Z_FLAG;
	319	else if (tmp < 0)
	320	flags \|= N_FLAG;
	321	if ((dneg && mof != -1)
	322	\|\| (!dneg && mof != 0))
	323	flags \|= V_FLAG;
6231868b	324	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	325	}
b41f7df0 EI	326
6231868b	327	uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	328	{
b41f7df0	329	uint32_t flags = 0;
dceaf394	330	uint64_t tmp;
b41f7df0	331
dceaf394 EI	332	tmp = mof;
	333	tmp <<= 32;
	334	tmp \|= res;
b41f7df0 EI	335	if (tmp == 0)
	336	flags \|= Z_FLAG;
	337	else if (tmp >> 63)
	338	flags \|= N_FLAG;
	339	if (mof)
	340	flags \|= V_FLAG;
	341
6231868b	342	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	343	}
b41f7df0 EI	344
6231868b EI	345	uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
6231868b EI	346	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	347	{
b41f7df0 EI	348	uint32_t flags = 0;
b41f7df0 EI	349
6231868b EI	350	src = src & 0x80000000;
6231868b EI	351	dst = dst & 0x80000000;
b41f7df0 EI	352
	353	if ((res & 0x80000000L) != 0L)
	354	{
	355	flags \|= N_FLAG;
a8cf66bb	356	if (!src && !dst)
b41f7df0	357	flags \|= V_FLAG;
a8cf66bb	358	else if (src & dst)
b41f7df0	359	flags \|= R_FLAG;
b41f7df0 EI	360	}
	361	else
	362	{
	363	if (res == 0L)
	364	flags \|= Z_FLAG;
a8cf66bb	365	if (src & dst)
b41f7df0	366	flags \|= V_FLAG;
a8cf66bb	367	if (dst \| src)
b41f7df0 EI	368	flags \|= R_FLAG;
	369	}
	370
6231868b	371	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	372	}
b41f7df0 EI	373
6231868b EI	374	uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
6231868b EI	375	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	376	{
b41f7df0 EI	377	uint32_t flags = 0;
b41f7df0 EI	378
6231868b EI	379	src = src & 0x80000000;
6231868b EI	380	dst = dst & 0x80000000;
30abcfc7	381
a8cf66bb	382	if ((res & 0x80000000L) != 0L)
30abcfc7	383	{
a8cf66bb EI	384	flags \|= N_FLAG;
	385	if (!src && !dst)
	386	flags \|= V_FLAG;
	387	else if (src & dst)
	388	flags \|= C_FLAG;
	389	}
	390	else
	391	{
	392	if (res == 0L)
	393	flags \|= Z_FLAG;
	394	if (src & dst)
	395	flags \|= V_FLAG;
	396	if (dst \| src)
	397	flags \|= C_FLAG;
30abcfc7 EI	398	}
30abcfc7 EI	399
6231868b	400	return evaluate_flags_writeback(flags, ccs);
a8cf66bb EI	401	}
a8cf66bb EI	402
6231868b EI	403	uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
6231868b EI	404	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	405	{
a8cf66bb EI	406	uint32_t flags = 0;
a8cf66bb EI	407
6231868b EI	408	src = (~src) & 0x80000000;
6231868b EI	409	dst = dst & 0x80000000;
b41f7df0 EI	410
	411	if ((res & 0x80000000L) != 0L)
	412	{
	413	flags \|= N_FLAG;
a8cf66bb	414	if (!src && !dst)
b41f7df0	415	flags \|= V_FLAG;
a8cf66bb	416	else if (src & dst)
b41f7df0	417	flags \|= C_FLAG;
b41f7df0 EI	418	}
	419	else
	420	{
	421	if (res == 0L)
	422	flags \|= Z_FLAG;
a8cf66bb	423	if (src & dst)
b41f7df0	424	flags \|= V_FLAG;
a8cf66bb	425	if (dst \| src)
b41f7df0 EI	426	flags \|= C_FLAG;
	427	}
	428
a8cf66bb	429	flags ^= C_FLAG;
6231868b	430	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	431	}
b41f7df0 EI	432
6231868b	433	uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
b41f7df0	434	{
b41f7df0 EI	435	uint32_t flags = 0;
b41f7df0 EI	436
b41f7df0 EI	437	if ((int32_t)res < 0)
	438	flags \|= N_FLAG;
	439	else if (res == 0L)
	440	flags \|= Z_FLAG;
	441
6231868b	442	return evaluate_flags_writeback(flags, ccs);
b41f7df0	443	}
6231868b	444	uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
b41f7df0	445	{
b41f7df0	446	uint32_t flags = 0;
b41f7df0 EI	447
	448	if ((int16_t)res < 0L)
	449	flags \|= N_FLAG;
	450	else if (res == 0)
	451	flags \|= Z_FLAG;
	452
6231868b	453	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	454	}
	455
	456	/* TODO: This is expensive. We could split things up and only evaluate part of
	457	CCR on a need to know basis. For now, we simply re-evaluate everything. */
6231868b	458	void helper_evaluate_flags(void)
b41f7df0	459	{
6231868b	460	uint32_t src, dst, res;
b41f7df0 EI	461	uint32_t flags = 0;
	462
	463	src = env->cc_src;
	464	dst = env->cc_dest;
	465	res = env->cc_result;
	466
30abcfc7 EI	467	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	468	src = ~src;
b41f7df0 EI	469
	470	/* Now, evaluate the flags. This stuff is based on
	471	Per Zander's CRISv10 simulator. */
	472	switch (env->cc_size)
	473	{
	474	case 1:
	475	if ((res & 0x80L) != 0L)
	476	{
	477	flags \|= N_FLAG;
	478	if (((src & 0x80L) == 0L)
	479	&& ((dst & 0x80L) == 0L))
	480	{
	481	flags \|= V_FLAG;
	482	}
	483	else if (((src & 0x80L) != 0L)
	484	&& ((dst & 0x80L) != 0L))
	485	{
	486	flags \|= C_FLAG;
	487	}
	488	}
	489	else
	490	{
	491	if ((res & 0xFFL) == 0L)
	492	{
	493	flags \|= Z_FLAG;
	494	}
	495	if (((src & 0x80L) != 0L)
	496	&& ((dst & 0x80L) != 0L))
	497	{
	498	flags \|= V_FLAG;
	499	}
	500	if ((dst & 0x80L) != 0L
	501	\|\| (src & 0x80L) != 0L)
	502	{
	503	flags \|= C_FLAG;
	504	}
	505	}
	506	break;
	507	case 2:
	508	if ((res & 0x8000L) != 0L)
	509	{
	510	flags \|= N_FLAG;
	511	if (((src & 0x8000L) == 0L)
	512	&& ((dst & 0x8000L) == 0L))
	513	{
	514	flags \|= V_FLAG;
	515	}
	516	else if (((src & 0x8000L) != 0L)
	517	&& ((dst & 0x8000L) != 0L))
	518	{
	519	flags \|= C_FLAG;
	520	}
	521	}
	522	else
	523	{
	524	if ((res & 0xFFFFL) == 0L)
	525	{
	526	flags \|= Z_FLAG;
	527	}
	528	if (((src & 0x8000L) != 0L)
	529	&& ((dst & 0x8000L) != 0L))
	530	{
	531	flags \|= V_FLAG;
	532	}
533	if ((dst & 0x8000L) != 0L
534	\|\| (src & 0x8000L) != 0L)
535	{
536	flags \|= C_FLAG;
537	}
538	}
539	break;
540	case 4:
541	if ((res & 0x80000000L) != 0L)
542	{
543	flags \|= N_FLAG;
544	if (((src & 0x80000000L) == 0L)
545	&& ((dst & 0x80000000L) == 0L))
546	{
547	flags \|= V_FLAG;
548	}
549	else if (((src & 0x80000000L) != 0L) &&
550	((dst & 0x80000000L) != 0L))
551	{
552	flags \|= C_FLAG;
553	}
554	}
555	else
556	{
557	if (res == 0L)
558	flags \|= Z_FLAG;
559	if (((src & 0x80000000L) != 0L)
560	&& ((dst & 0x80000000L) != 0L))
561	flags \|= V_FLAG;
562	if ((dst & 0x80000000L) != 0L
563	\|\| (src & 0x80000000L) != 0L)
564	flags \|= C_FLAG;
565	}
566	break;
567	default:
568	break;
569	}
570
6231868b	571	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	572	flags ^= C_FLAG;
6231868b EI	573
6231868b EI	574	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
b41f7df0	575	}
30abcfc7 EI	576
	577	void helper_top_evaluate_flags(void)
	578	{
	579	switch (env->cc_op)
	580	{
	581	case CC_OP_MCP:
6231868b EI	582	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
	583	env->pregs[PR_CCS], env->cc_src,
	584	env->cc_dest, env->cc_result);
30abcfc7 EI	585	break;
30abcfc7 EI	586	case CC_OP_MULS:
6231868b EI	587	env->pregs[PR_CCS] = helper_evaluate_flags_muls(
	588	env->pregs[PR_CCS], env->cc_result,
	589	env->pregs[PR_MOF]);
30abcfc7 EI	590	break;
30abcfc7 EI	591	case CC_OP_MULU:
6231868b EI	592	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
	593	env->pregs[PR_CCS], env->cc_result,
	594	env->pregs[PR_MOF]);
30abcfc7 EI	595	break;
	596	case CC_OP_MOVE:
	597	case CC_OP_AND:
	598	case CC_OP_OR:
	599	case CC_OP_XOR:
	600	case CC_OP_ASR:
	601	case CC_OP_LSR:
	602	case CC_OP_LSL:
6231868b EI	603	switch (env->cc_size)
	604	{
	605	case 4:
	606	env->pregs[PR_CCS] =
	607	helper_evaluate_flags_move_4(
	608	env->pregs[PR_CCS],
	609	env->cc_result);
	610	break;
	611	case 2:
	612	env->pregs[PR_CCS] =
	613	helper_evaluate_flags_move_2(
	614	env->pregs[PR_CCS],
	615	env->cc_result);
	616	break;
	617	default:
	618	helper_evaluate_flags();
	619	break;
	620	}
	621	break;
30abcfc7 EI	622	case CC_OP_FLAGS:
	623	/* live. */
	624	break;
a8cf66bb EI	625	case CC_OP_SUB:
	626	case CC_OP_CMP:
	627	if (env->cc_size == 4)
6231868b EI	628	env->pregs[PR_CCS] =
	629	helper_evaluate_flags_sub_4(
	630	env->pregs[PR_CCS],
	631	env->cc_src, env->cc_dest,
	632	env->cc_result);
a8cf66bb EI	633	else
	634	helper_evaluate_flags();
	635	break;
30abcfc7 EI	636	default:
	637	{
	638	switch (env->cc_size)
	639	{
6231868b EI	640	case 4:
	641	env->pregs[PR_CCS] =
	642	helper_evaluate_flags_alu_4(
	643	env->pregs[PR_CCS],
	644	env->cc_src, env->cc_dest,
	645	env->cc_result);
	646	break;
	647	default:
	648	helper_evaluate_flags();
	649	break;
30abcfc7 EI	650	}
	651	}
	652	break;
	653	}
	654	}