[qemu.git] / hw / ppc.c

/*
 * QEMU generic PPC hardware System Emulator
 * 
 * Copyright (c) 2003-2007 Jocelyn Mayer
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"

/*****************************************************************************/
/* PPC time base and decrementer emulation */
//#define DEBUG_TB

struct ppc_tb_t {
    /* Time base management */
    int64_t  tb_offset;    /* Compensation               */
    uint32_t tb_freq;      /* TB frequency               */
    /* Decrementer management */
    uint64_t decr_next;    /* Tick for next decr interrupt  */
    struct QEMUTimer *decr_timer;
};

static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
{
    /* TB time in tb periods */
    return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
                    tb_env->tb_freq, ticks_per_sec);
}

uint32_t cpu_ppc_load_tbl (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env);
#ifdef DEBUG_TB
    {
        static int last_time;
        int now;
        now = time(NULL);
        if (last_time != now) {
            last_time = now;
            printf("%s: tb=0x%016lx %d %08lx\n",
                   __func__, tb, now, tb_env->tb_offset);
        }
    }
#endif

    return tb & 0xFFFFFFFF;
}

uint32_t cpu_ppc_load_tbu (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env);
#ifdef DEBUG_TB
    printf("%s: tb=0x%016lx\n", __func__, tb);
#endif

    return tb >> 32;
}

static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
{
    tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
        - qemu_get_clock(vm_clock);
#ifdef DEBUG_TB
    printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
#endif
}

void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
{
    ppc_tb_t *tb_env = env->tb_env;

    cpu_ppc_store_tb(tb_env,
                     ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
}

void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
{
    ppc_tb_t *tb_env = env->tb_env;

    cpu_ppc_store_tb(tb_env,
                     ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
}

uint32_t cpu_ppc_load_decr (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint32_t decr;
    int64_t diff;

    diff = tb_env->decr_next - qemu_get_clock(vm_clock);
    if (diff >= 0)
        decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
    else
        decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
#if defined(DEBUG_TB)
    printf("%s: 0x%08x\n", __func__, decr);
#endif

    return decr;
}

/* When decrementer expires,
 * all we need to do is generate or queue a CPU exception
 */
static inline void cpu_ppc_decr_excp (CPUState *env)
{
    /* Raise it */
#ifdef DEBUG_TB
    printf("raise decrementer exception\n");
#endif
    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
                                 uint32_t value, int is_excp)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t now, next;

#ifdef DEBUG_TB
    printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
#endif
    now = qemu_get_clock(vm_clock);
    next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
    if (is_excp)
        next += tb_env->decr_next - now;
    if (next == now)
        next++;
    tb_env->decr_next = next;
    /* Adjust timer */
    qemu_mod_timer(tb_env->decr_timer, next);
    /* If we set a negative value and the decrementer was positive,
     * raise an exception.
     */
    if ((value & 0x80000000) && !(decr & 0x80000000))
        cpu_ppc_decr_excp(env);
}

void cpu_ppc_store_decr (CPUState *env, uint32_t value)
{
    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
}

static void cpu_ppc_decr_cb (void *opaque)
{
    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}

/* Set up (once) timebase frequency (in Hz) */
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
{
    ppc_tb_t *tb_env;

    tb_env = qemu_mallocz(sizeof(ppc_tb_t));
    if (tb_env == NULL)
        return NULL;
    env->tb_env = tb_env;
    if (tb_env->tb_freq == 0 || 1) {
        tb_env->tb_freq = freq;
        /* Create new timer */
        tb_env->decr_timer =
            qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
        /* There is a bug in Linux 2.4 kernels:
         * if a decrementer exception is pending when it enables msr_ee,
         * it's not ready to handle it...
         */
        _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
    }

    return tb_env;
}

/* Specific helpers for POWER & PowerPC 601 RTC */
ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
{
    return cpu_ppc_tb_init(env, 7812500);
}

void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
__attribute__ (( alias ("cpu_ppc_store_tbu") ));

uint32_t cpu_ppc601_load_rtcu (CPUState *env)
__attribute__ (( alias ("cpu_ppc_load_tbu") ));

void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
{
    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
}

uint32_t cpu_ppc601_load_rtcl (CPUState *env)
{
    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}

/* Embedded PowerPC timers */
target_ulong load_40x_pit (CPUState *env)
{
    /* XXX: TODO */
    return 0;
}

void store_40x_pit (CPUState *env, target_ulong val)
{
    /* XXX: TODO */
}

void store_booke_tcr (CPUState *env, target_ulong val)
{
    /* XXX: TODO */
}

void store_booke_tsr (CPUState *env, target_ulong val)
{
    /* XXX: TODO */
}

#if 0
/*****************************************************************************/
/* Handle system reset (for now, just stop emulation) */
void cpu_ppc_reset (CPUState *env)
{
    printf("Reset asked... Stop emulation\n");
    abort();
}
#endif

/*****************************************************************************/
/* Debug port */
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 0xF;
    switch (addr) {
    case 0:
        printf("%c", val);
        break;
    case 1:
        printf("\n");
        fflush(stdout);
        break;
    case 2:
        printf("Set loglevel to %04x\n", val);
        cpu_set_log(val | 0x100);
        break;
    }
}

/*****************************************************************************/
/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
    m48t59_write(nvram, addr, value);
}

uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
    return m48t59_read(nvram, addr);
}

void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
    m48t59_write(nvram, addr, value >> 8);
    m48t59_write(nvram, addr + 1, value & 0xFF);
}

uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
    uint16_t tmp;

    tmp = m48t59_read(nvram, addr) << 8;
    tmp |= m48t59_read(nvram, addr + 1);
    return tmp;
}

void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
    m48t59_write(nvram, addr, value >> 24);
    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
    m48t59_write(nvram, addr + 3, value & 0xFF);
}

uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
    uint32_t tmp;

    tmp = m48t59_read(nvram, addr) << 24;
    tmp |= m48t59_read(nvram, addr + 1) << 16;
    tmp |= m48t59_read(nvram, addr + 2) << 8;
    tmp |= m48t59_read(nvram, addr + 3);

    return tmp;
}

void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
                       const unsigned char *str, uint32_t max)
{
    int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {
        m48t59_write(nvram, addr + i, str[i]);
    }
    m48t59_write(nvram, addr + max - 1, '\0');
}

int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
    int i;

    memset(dst, 0, max);
    for (i = 0; i < max; i++) {
        dst[i] = NVRAM_get_byte(nvram, addr + i);
        if (dst[i] == '\0')
            break;
    }

    return i;
}

static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
{
    uint16_t tmp;
    uint16_t pd, pd1, pd2;

    tmp = prev >> 8;
    pd = prev ^ value;
    pd1 = pd & 0x000F;
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
    tmp ^= (pd1 << 3) | (pd1 << 8);
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);

    return tmp;
}

uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
{
    uint32_t i;
    uint16_t crc = 0xFFFF;
    int odd;

    odd = count & 1;
    count &= ~1;
    for (i = 0; i != count; i++) {
        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
    }
    if (odd) {
        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
    }

    return crc;
}

#define CMDLINE_ADDR 0x017ff000

int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                          const unsigned char *arch,
                          uint32_t RAM_size, int boot_device,
                          uint32_t kernel_image, uint32_t kernel_size,
                          const char *cmdline,
                          uint32_t initrd_image, uint32_t initrd_size,
                          uint32_t NVRAM_image,
                          int width, int height, int depth)
{
    uint16_t crc;

    /* Set parameters for Open Hack'Ware BIOS */
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
    NVRAM_set_string(nvram, 0x20, arch, 16);
    NVRAM_set_lword(nvram,  0x30, RAM_size);
    NVRAM_set_byte(nvram,   0x34, boot_device);
    NVRAM_set_lword(nvram,  0x38, kernel_image);
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
    if (cmdline) {
        /* XXX: put the cmdline in NVRAM too ? */
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
    } else {
        NVRAM_set_lword(nvram,  0x40, 0);
        NVRAM_set_lword(nvram,  0x44, 0);
    }
    NVRAM_set_lword(nvram,  0x48, initrd_image);
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);

    NVRAM_set_word(nvram,   0x54, width);
    NVRAM_set_word(nvram,   0x56, height);
    NVRAM_set_word(nvram,   0x58, depth);
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
    NVRAM_set_word(nvram,  0xFC, crc);

    return 0;
}
Commit	Line	Data
a541f297 FB	1	/*
	2	* QEMU generic PPC hardware System Emulator
	3	*
76a66253	4	* Copyright (c) 2003-2007 Jocelyn Mayer
a541f297 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
a541f297	24	#include "vl.h"
fd0bbb12	25	#include "m48t59.h"
a541f297	26
9fddaa0c FB	27	/*****************************************************************************/
	28	/* PPC time base and decrementer emulation */
	29	//#define DEBUG_TB
	30
	31	struct ppc_tb_t {
	32	/* Time base management */
	33	int64_t tb_offset; /* Compensation */
	34	uint32_t tb_freq; /* TB frequency */
	35	/* Decrementer management */
	36	uint64_t decr_next; /* Tick for next decr interrupt */
	37	struct QEMUTimer *decr_timer;
	38	};
	39
	40	static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
	41	{
	42	/* TB time in tb periods */
	43	return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
76a66253	44	tb_env->tb_freq, ticks_per_sec);
9fddaa0c FB	45	}
	46
	47	uint32_t cpu_ppc_load_tbl (CPUState *env)
	48	{
	49	ppc_tb_t *tb_env = env->tb_env;
	50	uint64_t tb;
	51
	52	tb = cpu_ppc_get_tb(tb_env);
	53	#ifdef DEBUG_TB
	54	{
76a66253 JM	55	static int last_time;
	56	int now;
	57	now = time(NULL);
	58	if (last_time != now) {
	59	last_time = now;
	60	printf("%s: tb=0x%016lx %d %08lx\n",
	61	__func__, tb, now, tb_env->tb_offset);
	62	}
9fddaa0c FB	63	}
	64	#endif
	65
	66	return tb & 0xFFFFFFFF;
	67	}
	68
	69	uint32_t cpu_ppc_load_tbu (CPUState *env)
	70	{
	71	ppc_tb_t *tb_env = env->tb_env;
	72	uint64_t tb;
	73
	74	tb = cpu_ppc_get_tb(tb_env);
	75	#ifdef DEBUG_TB
	76	printf("%s: tb=0x%016lx\n", __func__, tb);
	77	#endif
76a66253	78
9fddaa0c FB	79	return tb >> 32;
	80	}
	81
	82	static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
	83	{
	84	tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
	85	- qemu_get_clock(vm_clock);
	86	#ifdef DEBUG_TB
	87	printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
	88	#endif
	89	}
	90
	91	void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
	92	{
	93	ppc_tb_t *tb_env = env->tb_env;
	94
	95	cpu_ppc_store_tb(tb_env,
	96	((uint64_t)value << 32) \| cpu_ppc_load_tbl(env));
	97	}
	98
	99	void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
	100	{
	101	ppc_tb_t *tb_env = env->tb_env;
	102
	103	cpu_ppc_store_tb(tb_env,
	104	((uint64_t)cpu_ppc_load_tbu(env) << 32) \| value);
	105	}
	106
	107	uint32_t cpu_ppc_load_decr (CPUState *env)
	108	{
	109	ppc_tb_t *tb_env = env->tb_env;
	110	uint32_t decr;
4e588a4d	111	int64_t diff;
9fddaa0c	112
4e588a4d FB	113	diff = tb_env->decr_next - qemu_get_clock(vm_clock);
	114	if (diff >= 0)
	115	decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
	116	else
	117	decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
fd0bbb12	118	#if defined(DEBUG_TB)
9fddaa0c FB	119	printf("%s: 0x%08x\n", __func__, decr);
9fddaa0c FB	120	#endif
76a66253	121
9fddaa0c FB	122	return decr;
	123	}
	124
	125	/* When decrementer expires,
	126	* all we need to do is generate or queue a CPU exception
	127	*/
	128	static inline void cpu_ppc_decr_excp (CPUState *env)
	129	{
	130	/* Raise it */
	131	#ifdef DEBUG_TB
	132	printf("raise decrementer exception\n");
	133	#endif
	134	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	135	}
	136
	137	static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
	138	uint32_t value, int is_excp)
	139	{
	140	ppc_tb_t *tb_env = env->tb_env;
	141	uint64_t now, next;
	142
	143	#ifdef DEBUG_TB
	144	printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
	145	#endif
	146	now = qemu_get_clock(vm_clock);
	147	next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
	148	if (is_excp)
	149	next += tb_env->decr_next - now;
	150	if (next == now)
76a66253	151	next++;
9fddaa0c FB	152	tb_env->decr_next = next;
	153	/* Adjust timer */
	154	qemu_mod_timer(tb_env->decr_timer, next);
	155	/* If we set a negative value and the decrementer was positive,
	156	* raise an exception.
	157	*/
	158	if ((value & 0x80000000) && !(decr & 0x80000000))
76a66253	159	cpu_ppc_decr_excp(env);
9fddaa0c FB	160	}
	161
	162	void cpu_ppc_store_decr (CPUState *env, uint32_t value)
	163	{
	164	_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
	165	}
	166
	167	static void cpu_ppc_decr_cb (void *opaque)
	168	{
	169	_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
	170	}
	171
	172	/* Set up (once) timebase frequency (in Hz) */
	173	ppc_tb_t cpu_ppc_tb_init (CPUState env, uint32_t freq)
	174	{
	175	ppc_tb_t *tb_env;
	176
	177	tb_env = qemu_mallocz(sizeof(ppc_tb_t));
	178	if (tb_env == NULL)
	179	return NULL;
	180	env->tb_env = tb_env;
	181	if (tb_env->tb_freq == 0 \|\| 1) {
76a66253 JM	182	tb_env->tb_freq = freq;
	183	/* Create new timer */
	184	tb_env->decr_timer =
9fddaa0c	185	qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
76a66253 JM	186	/* There is a bug in Linux 2.4 kernels:
	187	* if a decrementer exception is pending when it enables msr_ee,
	188	* it's not ready to handle it...
	189	*/
	190	_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
9fddaa0c FB	191	}
	192
	193	return tb_env;
	194	}
	195
76a66253 JM	196	/* Specific helpers for POWER & PowerPC 601 RTC */
	197	ppc_tb_t cpu_ppc601_rtc_init (CPUState env)
	198	{
	199	return cpu_ppc_tb_init(env, 7812500);
	200	}
	201
	202	void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
	203	__attribute__ (( alias ("cpu_ppc_store_tbu") ));
	204
	205	uint32_t cpu_ppc601_load_rtcu (CPUState *env)
	206	__attribute__ (( alias ("cpu_ppc_load_tbu") ));
	207
	208	void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
	209	{
	210	cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
	211	}
	212
	213	uint32_t cpu_ppc601_load_rtcl (CPUState *env)
	214	{
	215	return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
	216	}
	217
	218	/* Embedded PowerPC timers */
	219	target_ulong load_40x_pit (CPUState *env)
	220	{
	221	/* XXX: TODO */
	222	return 0;
	223	}
	224
	225	void store_40x_pit (CPUState *env, target_ulong val)
	226	{
	227	/* XXX: TODO */
	228	}
	229
	230	void store_booke_tcr (CPUState *env, target_ulong val)
	231	{
	232	/* XXX: TODO */
	233	}
	234
	235	void store_booke_tsr (CPUState *env, target_ulong val)
	236	{
	237	/* XXX: TODO */
	238	}
	239
9fddaa0c FB	240	#if 0
	241	/*****************************************************************************/
	242	/* Handle system reset (for now, just stop emulation) */
	243	void cpu_ppc_reset (CPUState *env)
	244	{
	245	printf("Reset asked... Stop emulation\n");
	246	abort();
	247	}
	248	#endif
	249
64201201 FB	250	/*****************************************************************************/
64201201 FB	251	/* Debug port */
fd0bbb12	252	void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
64201201 FB	253	{
	254	addr &= 0xF;
	255	switch (addr) {
	256	case 0:
	257	printf("%c", val);
	258	break;
	259	case 1:
	260	printf("\n");
	261	fflush(stdout);
	262	break;
	263	case 2:
	264	printf("Set loglevel to %04x\n", val);
fd0bbb12	265	cpu_set_log(val \| 0x100);
64201201 FB	266	break;
	267	}
	268	}
	269
	270	/*****************************************************************************/
	271	/* NVRAM helpers */
	272	void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
	273	{
819385c5	274	m48t59_write(nvram, addr, value);
64201201 FB	275	}
	276
	277	uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
	278	{
819385c5	279	return m48t59_read(nvram, addr);
64201201 FB	280	}
	281
	282	void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
	283	{
819385c5 FB	284	m48t59_write(nvram, addr, value >> 8);
819385c5 FB	285	m48t59_write(nvram, addr + 1, value & 0xFF);
64201201 FB	286	}
	287
	288	uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
	289	{
	290	uint16_t tmp;
	291
819385c5 FB	292	tmp = m48t59_read(nvram, addr) << 8;
819385c5 FB	293	tmp \|= m48t59_read(nvram, addr + 1);
64201201 FB	294	return tmp;
	295	}
	296
	297	void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
	298	{
819385c5 FB	299	m48t59_write(nvram, addr, value >> 24);
	300	m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
	301	m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
	302	m48t59_write(nvram, addr + 3, value & 0xFF);
64201201 FB	303	}
	304
	305	uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
	306	{
	307	uint32_t tmp;
	308
819385c5 FB	309	tmp = m48t59_read(nvram, addr) << 24;
	310	tmp \|= m48t59_read(nvram, addr + 1) << 16;
	311	tmp \|= m48t59_read(nvram, addr + 2) << 8;
	312	tmp \|= m48t59_read(nvram, addr + 3);
76a66253	313
64201201 FB	314	return tmp;
	315	}
	316
	317	void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
	318	const unsigned char *str, uint32_t max)
	319	{
	320	int i;
	321
	322	for (i = 0; i < max && str[i] != '\0'; i++) {
819385c5	323	m48t59_write(nvram, addr + i, str[i]);
64201201	324	}
819385c5	325	m48t59_write(nvram, addr + max - 1, '\0');
64201201 FB	326	}
	327
	328	int NVRAM_get_string (m48t59_t nvram, uint8_t dst, uint16_t addr, int max)
	329	{
	330	int i;
	331
	332	memset(dst, 0, max);
	333	for (i = 0; i < max; i++) {
	334	dst[i] = NVRAM_get_byte(nvram, addr + i);
	335	if (dst[i] == '\0')
	336	break;
	337	}
	338
	339	return i;
	340	}
	341
	342	static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
	343	{
	344	uint16_t tmp;
	345	uint16_t pd, pd1, pd2;
	346
	347	tmp = prev >> 8;
	348	pd = prev ^ value;
	349	pd1 = pd & 0x000F;
	350	pd2 = ((pd >> 4) & 0x000F) ^ pd1;
	351	tmp ^= (pd1 << 3) \| (pd1 << 8);
	352	tmp ^= pd2 \| (pd2 << 7) \| (pd2 << 12);
	353
	354	return tmp;
	355	}
	356
	357	uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
	358	{
	359	uint32_t i;
	360	uint16_t crc = 0xFFFF;
	361	int odd;
	362
	363	odd = count & 1;
	364	count &= ~1;
	365	for (i = 0; i != count; i++) {
76a66253	366	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
64201201 FB	367	}
64201201 FB	368	if (odd) {
76a66253	369	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
64201201 FB	370	}
	371
	372	return crc;
	373	}
	374
fd0bbb12 FB	375	#define CMDLINE_ADDR 0x017ff000
fd0bbb12 FB	376
64201201 FB	377	int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
	378	const unsigned char *arch,
	379	uint32_t RAM_size, int boot_device,
	380	uint32_t kernel_image, uint32_t kernel_size,
fd0bbb12	381	const char *cmdline,
64201201	382	uint32_t initrd_image, uint32_t initrd_size,
fd0bbb12 FB	383	uint32_t NVRAM_image,
fd0bbb12 FB	384	int width, int height, int depth)
64201201 FB	385	{
	386	uint16_t crc;
	387
	388	/* Set parameters for Open Hack'Ware BIOS */
	389	NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
	390	NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
	391	NVRAM_set_word(nvram, 0x14, NVRAM_size);
	392	NVRAM_set_string(nvram, 0x20, arch, 16);
	393	NVRAM_set_lword(nvram, 0x30, RAM_size);
	394	NVRAM_set_byte(nvram, 0x34, boot_device);
	395	NVRAM_set_lword(nvram, 0x38, kernel_image);
	396	NVRAM_set_lword(nvram, 0x3C, kernel_size);
fd0bbb12 FB	397	if (cmdline) {
	398	/* XXX: put the cmdline in NVRAM too ? */
	399	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
	400	NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
	401	NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
	402	} else {
	403	NVRAM_set_lword(nvram, 0x40, 0);
	404	NVRAM_set_lword(nvram, 0x44, 0);
	405	}
64201201 FB	406	NVRAM_set_lword(nvram, 0x48, initrd_image);
	407	NVRAM_set_lword(nvram, 0x4C, initrd_size);
	408	NVRAM_set_lword(nvram, 0x50, NVRAM_image);
fd0bbb12 FB	409
	410	NVRAM_set_word(nvram, 0x54, width);
	411	NVRAM_set_word(nvram, 0x56, height);
	412	NVRAM_set_word(nvram, 0x58, depth);
	413	crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
	414	NVRAM_set_word(nvram, 0xFC, crc);
64201201 FB	415
64201201 FB	416	return 0;
a541f297	417	}