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Fix userland ELF loader for zero sized BSS.
[qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
79aceca5 3 *
3fc6c082 4 * Copyright (c) 2003-2005 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
9fddaa0c 31//#define PPC_DEBUG_DISAS
79aceca5 32
c53be334
FB		 33#ifdef USE_DIRECT_JUMP
34#define TBPARAM(x)
35#else
36#define TBPARAM(x) (long)(x)
37#endif
38
79aceca5
FB		 39enum {
40#define DEF(s, n, copy_size) INDEX_op_ ## s,
41#include "opc.h"
42#undef DEF
43 NB_OPS,
44};
45
46static uint16_t *gen_opc_ptr;
47static uint32_t *gen_opparam_ptr;
48
49#include "gen-op.h"
28b6751f 50
28b6751f 51#define GEN8(func, NAME) \
9a64fbe4
FB		 52static GenOpFunc *NAME ## _table [8] = { \
53NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
55}; \
56static inline void func(int n) \
57{ \
58 NAME ## _table[n](); \
59}
60
61#define GEN16(func, NAME) \
62static GenOpFunc *NAME ## _table [16] = { \
63NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
64NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
65NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
66NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
67}; \
68static inline void func(int n) \
69{ \
70 NAME ## _table[n](); \
28b6751f
FB		 71}
72
73#define GEN32(func, NAME) \
9a64fbe4
FB		 74static GenOpFunc *NAME ## _table [32] = { \
75NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
76NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
77NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
78NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
79NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
80NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
81NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
82NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
83}; \
84static inline void func(int n) \
85{ \
86 NAME ## _table[n](); \
87}
88
89/* Condition register moves */
90GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
91GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
92GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
93GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 94
fb0eaffc
FB		 95/* Floating point condition and status register moves */
96GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
97GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
98GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
99static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
100 &gen_op_store_T0_fpscri_fpscr0,
101 &gen_op_store_T0_fpscri_fpscr1,
102 &gen_op_store_T0_fpscri_fpscr2,
103 &gen_op_store_T0_fpscri_fpscr3,
104 &gen_op_store_T0_fpscri_fpscr4,
105 &gen_op_store_T0_fpscri_fpscr5,
106 &gen_op_store_T0_fpscri_fpscr6,
107 &gen_op_store_T0_fpscri_fpscr7,
108};
109static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
110{
111 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
112}
113
9a64fbe4
FB		 114/* Segment register moves */
115GEN16(gen_op_load_sr, gen_op_load_sr);
116GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 117
9a64fbe4
FB		 118/* General purpose registers moves */
119GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
120GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
121GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
122
123GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
124GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
125GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 126
fb0eaffc
FB		 127/* floating point registers moves */
128GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
129GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
130GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
131GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
132GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
133GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 134
135static uint8_t spr_access[1024 / 2];
136
137/* internal defines */
138typedef struct DisasContext {
139 struct TranslationBlock *tb;
0fa85d43 140 target_ulong nip;
79aceca5 141 uint32_t opcode;
9a64fbe4 142 uint32_t exception;
3cc62370
FB		 143 /* Routine used to access memory */
144 int mem_idx;
145 /* Translation flags */
9a64fbe4 146#if !defined(CONFIG_USER_ONLY)
79aceca5 147 int supervisor;
9a64fbe4 148#endif
3cc62370 149 int fpu_enabled;
3fc6c082 150 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 151 int singlestep_enabled;
79aceca5
FB		 152} DisasContext;
153
3fc6c082 154struct opc_handler_t {
79aceca5
FB		 155 /* invalid bits */
156 uint32_t inval;
9a64fbe4
FB		 157 /* instruction type */
158 uint32_t type;
79aceca5
FB		 159 /* handler */
160 void (*handler)(DisasContext *ctx);
3fc6c082 161};
79aceca5 162
9fddaa0c 163#define RET_EXCP(ctx, excp, error) \
79aceca5 164do { \
9fddaa0c
FB		 165 if ((ctx)->exception == EXCP_NONE) { \
166 gen_op_update_nip((ctx)->nip); \
167 } \
168 gen_op_raise_exception_err((excp), (error)); \
169 ctx->exception = (excp); \
79aceca5
FB		 170} while (0)
171
9fddaa0c
FB		 172#define RET_INVAL(ctx) \
173RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
174
175#define RET_PRIVOPC(ctx) \
176RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 177
9fddaa0c
FB		 178#define RET_PRIVREG(ctx) \
179RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 180
f24e5695 181/* Stop translation */
3fc6c082
FB		 182static inline void RET_STOP (DisasContext *ctx)
183{
f24e5695
FB		 184 gen_op_update_nip((ctx)->nip);
185 ctx->exception = EXCP_MTMSR;
3fc6c082
FB		 186}
187
f24e5695 188/* No need to update nip here, as execution flow will change */
2be0071f
FB		 189static inline void RET_CHG_FLOW (DisasContext *ctx)
190{
2be0071f
FB		 191 ctx->exception = EXCP_MTMSR;
192}
193
79aceca5
FB		 194#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
195static void gen_##name (DisasContext *ctx); \
196GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
197static void gen_##name (DisasContext *ctx)
198
79aceca5
FB		 199typedef struct opcode_t {
200 unsigned char opc1, opc2, opc3;
18fba28c
FB		 201#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
202 unsigned char pad[5];
203#else
204 unsigned char pad[1];
205#endif
79aceca5 206 opc_handler_t handler;
3fc6c082 207 const unsigned char *oname;
79aceca5
FB		 208} opcode_t;
209
79aceca5
FB		 210/*** Instruction decoding ***/
211#define EXTRACT_HELPER(name, shift, nb) \
212static inline uint32_t name (uint32_t opcode) \
213{ \
214 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
215}
216
217#define EXTRACT_SHELPER(name, shift, nb) \
218static inline int32_t name (uint32_t opcode) \
219{ \
18fba28c 220 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 221}
222
223/* Opcode part 1 */
224EXTRACT_HELPER(opc1, 26, 6);
225/* Opcode part 2 */
226EXTRACT_HELPER(opc2, 1, 5);
227/* Opcode part 3 */
228EXTRACT_HELPER(opc3, 6, 5);
229/* Update Cr0 flags */
230EXTRACT_HELPER(Rc, 0, 1);
231/* Destination */
232EXTRACT_HELPER(rD, 21, 5);
233/* Source */
234EXTRACT_HELPER(rS, 21, 5);
235/* First operand */
236EXTRACT_HELPER(rA, 16, 5);
237/* Second operand */
238EXTRACT_HELPER(rB, 11, 5);
239/* Third operand */
240EXTRACT_HELPER(rC, 6, 5);
241/*** Get CRn ***/
242EXTRACT_HELPER(crfD, 23, 3);
243EXTRACT_HELPER(crfS, 18, 3);
244EXTRACT_HELPER(crbD, 21, 5);
245EXTRACT_HELPER(crbA, 16, 5);
246EXTRACT_HELPER(crbB, 11, 5);
247/* SPR / TBL */
3fc6c082
FB		 248EXTRACT_HELPER(_SPR, 11, 10);
249static inline uint32_t SPR (uint32_t opcode)
250{
251 uint32_t sprn = _SPR(opcode);
252
253 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
254}
79aceca5
FB		 255/*** Get constants ***/
256EXTRACT_HELPER(IMM, 12, 8);
257/* 16 bits signed immediate value */
258EXTRACT_SHELPER(SIMM, 0, 16);
259/* 16 bits unsigned immediate value */
260EXTRACT_HELPER(UIMM, 0, 16);
261/* Bit count */
262EXTRACT_HELPER(NB, 11, 5);
263/* Shift count */
264EXTRACT_HELPER(SH, 11, 5);
265/* Mask start */
266EXTRACT_HELPER(MB, 6, 5);
267/* Mask end */
268EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 269/* Trap operand */
270EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 271
272EXTRACT_HELPER(CRM, 12, 8);
273EXTRACT_HELPER(FM, 17, 8);
274EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 275EXTRACT_HELPER(FPIMM, 20, 4);
276
79aceca5
FB		 277/*** Jump target decoding ***/
278/* Displacement */
279EXTRACT_SHELPER(d, 0, 16);
280/* Immediate address */
281static inline uint32_t LI (uint32_t opcode)
282{
283 return (opcode >> 0) & 0x03FFFFFC;
284}
285
286static inline uint32_t BD (uint32_t opcode)
287{
288 return (opcode >> 0) & 0xFFFC;
289}
290
291EXTRACT_HELPER(BO, 21, 5);
292EXTRACT_HELPER(BI, 16, 5);
293/* Absolute/relative address */
294EXTRACT_HELPER(AA, 1, 1);
295/* Link */
296EXTRACT_HELPER(LK, 0, 1);
297
298/* Create a mask between <start> and <end> bits */
299static inline uint32_t MASK (uint32_t start, uint32_t end)
300{
301 uint32_t ret;
302
303 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
304 if (start > end)
305 return ~ret;
306
307 return ret;
308}
309
3fc6c082
FB		 310#if HOST_LONG_BITS == 64
311#define OPC_ALIGN 8
312#else
313#define OPC_ALIGN 4
314#endif
1b039c09 315#if defined(__APPLE__)
933dc6eb 316#define OPCODES_SECTION \
3fc6c082 317 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 318#else
1b039c09 319#define OPCODES_SECTION \
3fc6c082 320 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 321#endif
322
79aceca5 323#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 324OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 325 .opc1 = op1, \
326 .opc2 = op2, \
327 .opc3 = op3, \
18fba28c 328 .pad = { 0, }, \
79aceca5
FB		 329 .handler = { \
330 .inval = invl, \
9a64fbe4 331 .type = _typ, \
79aceca5
FB		 332 .handler = &gen_##name, \
333 }, \
3fc6c082 334 .oname = stringify(name), \
79aceca5
FB		 335}
336
337#define GEN_OPCODE_MARK(name) \
18fba28c 338OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 339 .opc1 = 0xFF, \
340 .opc2 = 0xFF, \
341 .opc3 = 0xFF, \
18fba28c 342 .pad = { 0, }, \
79aceca5
FB		 343 .handler = { \
344 .inval = 0x00000000, \
9a64fbe4 345 .type = 0x00, \
79aceca5
FB		 346 .handler = NULL, \
347 }, \
3fc6c082 348 .oname = stringify(name), \
79aceca5
FB		 349}
350
351/* Start opcode list */
352GEN_OPCODE_MARK(start);
353
354/* Invalid instruction */
9a64fbe4
FB		 355GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
356{
9fddaa0c 357 RET_INVAL(ctx);
9a64fbe4
FB		 358}
359
79aceca5
FB		 360static opc_handler_t invalid_handler = {
361 .inval = 0xFFFFFFFF,
9a64fbe4 362 .type = PPC_NONE,
79aceca5
FB		 363 .handler = gen_invalid,
364};
365
366/*** Integer arithmetic ***/
367#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
368GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
369{ \
370 gen_op_load_gpr_T0(rA(ctx->opcode)); \
371 gen_op_load_gpr_T1(rB(ctx->opcode)); \
372 gen_op_##name(); \
373 if (Rc(ctx->opcode) != 0) \
374 gen_op_set_Rc0(); \
375 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 376}
377
378#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
379GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
380{ \
381 gen_op_load_gpr_T0(rA(ctx->opcode)); \
382 gen_op_load_gpr_T1(rB(ctx->opcode)); \
383 gen_op_##name(); \
384 if (Rc(ctx->opcode) != 0) \
18fba28c 385 gen_op_set_Rc0(); \
79aceca5 386 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 387}
388
389#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
390GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
391{ \
392 gen_op_load_gpr_T0(rA(ctx->opcode)); \
393 gen_op_##name(); \
394 if (Rc(ctx->opcode) != 0) \
395 gen_op_set_Rc0(); \
396 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 397}
398#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
399GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
400{ \
401 gen_op_load_gpr_T0(rA(ctx->opcode)); \
402 gen_op_##name(); \
403 if (Rc(ctx->opcode) != 0) \
18fba28c 404 gen_op_set_Rc0(); \
79aceca5 405 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 406}
407
408/* Two operands arithmetic functions */
409#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
410__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
411__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
412
413/* Two operands arithmetic functions with no overflow allowed */
414#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
415__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
416
417/* One operand arithmetic functions */
418#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
419__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
420__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
421
422/* add add. addo addo. */
423GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
424/* addc addc. addco addco. */
425GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
426/* adde adde. addeo addeo. */
427GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
428/* addme addme. addmeo addmeo. */
429GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
430/* addze addze. addzeo addzeo. */
431GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
432/* divw divw. divwo divwo. */
433GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
434/* divwu divwu. divwuo divwuo. */
435GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
436/* mulhw mulhw. */
437GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
438/* mulhwu mulhwu. */
439GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
440/* mullw mullw. mullwo mullwo. */
441GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
442/* neg neg. nego nego. */
443GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
444/* subf subf. subfo subfo. */
445GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
446/* subfc subfc. subfco subfco. */
447GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
448/* subfe subfe. subfeo subfeo. */
449GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
450/* subfme subfme. subfmeo subfmeo. */
451GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
452/* subfze subfze. subfzeo subfzeo. */
453GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
454/* addi */
455GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
456{
457 int32_t simm = SIMM(ctx->opcode);
458
459 if (rA(ctx->opcode) == 0) {
460 gen_op_set_T0(simm);
461 } else {
462 gen_op_load_gpr_T0(rA(ctx->opcode));
463 gen_op_addi(simm);
464 }
465 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 466}
467/* addic */
468GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
469{
470 gen_op_load_gpr_T0(rA(ctx->opcode));
471 gen_op_addic(SIMM(ctx->opcode));
472 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 473}
474/* addic. */
475GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
476{
477 gen_op_load_gpr_T0(rA(ctx->opcode));
478 gen_op_addic(SIMM(ctx->opcode));
479 gen_op_set_Rc0();
480 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 481}
482/* addis */
483GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
484{
485 int32_t simm = SIMM(ctx->opcode);
486
487 if (rA(ctx->opcode) == 0) {
488 gen_op_set_T0(simm << 16);
489 } else {
490 gen_op_load_gpr_T0(rA(ctx->opcode));
491 gen_op_addi(simm << 16);
492 }
493 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 494}
495/* mulli */
496GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
497{
498 gen_op_load_gpr_T0(rA(ctx->opcode));
499 gen_op_mulli(SIMM(ctx->opcode));
500 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 501}
502/* subfic */
503GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
504{
505 gen_op_load_gpr_T0(rA(ctx->opcode));
506 gen_op_subfic(SIMM(ctx->opcode));
507 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 508}
509
510/*** Integer comparison ***/
511#define GEN_CMP(name, opc) \
512GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
513{ \
514 gen_op_load_gpr_T0(rA(ctx->opcode)); \
515 gen_op_load_gpr_T1(rB(ctx->opcode)); \
516 gen_op_##name(); \
517 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 518}
519
520/* cmp */
521GEN_CMP(cmp, 0x00);
522/* cmpi */
523GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
524{
525 gen_op_load_gpr_T0(rA(ctx->opcode));
526 gen_op_cmpi(SIMM(ctx->opcode));
527 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 528}
529/* cmpl */
530GEN_CMP(cmpl, 0x01);
531/* cmpli */
532GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
533{
534 gen_op_load_gpr_T0(rA(ctx->opcode));
535 gen_op_cmpli(UIMM(ctx->opcode));
536 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 537}
538
539/*** Integer logical ***/
540#define __GEN_LOGICAL2(name, opc2, opc3) \
541GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
542{ \
543 gen_op_load_gpr_T0(rS(ctx->opcode)); \
544 gen_op_load_gpr_T1(rB(ctx->opcode)); \
545 gen_op_##name(); \
546 if (Rc(ctx->opcode) != 0) \
547 gen_op_set_Rc0(); \
548 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 549}
550#define GEN_LOGICAL2(name, opc) \
551__GEN_LOGICAL2(name, 0x1C, opc)
552
553#define GEN_LOGICAL1(name, opc) \
554GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
555{ \
556 gen_op_load_gpr_T0(rS(ctx->opcode)); \
557 gen_op_##name(); \
558 if (Rc(ctx->opcode) != 0) \
559 gen_op_set_Rc0(); \
560 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 561}
562
563/* and & and. */
564GEN_LOGICAL2(and, 0x00);
565/* andc & andc. */
566GEN_LOGICAL2(andc, 0x01);
567/* andi. */
568GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
569{
570 gen_op_load_gpr_T0(rS(ctx->opcode));
571 gen_op_andi_(UIMM(ctx->opcode));
572 gen_op_set_Rc0();
573 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 574}
575/* andis. */
576GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
577{
578 gen_op_load_gpr_T0(rS(ctx->opcode));
579 gen_op_andi_(UIMM(ctx->opcode) << 16);
580 gen_op_set_Rc0();
581 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 582}
583
584/* cntlzw */
585GEN_LOGICAL1(cntlzw, 0x00);
586/* eqv & eqv. */
587GEN_LOGICAL2(eqv, 0x08);
588/* extsb & extsb. */
589GEN_LOGICAL1(extsb, 0x1D);
590/* extsh & extsh. */
591GEN_LOGICAL1(extsh, 0x1C);
592/* nand & nand. */
593GEN_LOGICAL2(nand, 0x0E);
594/* nor & nor. */
595GEN_LOGICAL2(nor, 0x03);
9a64fbe4 596
79aceca5 597/* or & or. */
9a64fbe4
FB		 598GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
599{
600 gen_op_load_gpr_T0(rS(ctx->opcode));
601 /* Optimisation for mr case */
602 if (rS(ctx->opcode) != rB(ctx->opcode)) {
603 gen_op_load_gpr_T1(rB(ctx->opcode));
604 gen_op_or();
605 }
606 if (Rc(ctx->opcode) != 0)
607 gen_op_set_Rc0();
608 gen_op_store_T0_gpr(rA(ctx->opcode));
609}
610
79aceca5
FB		 611/* orc & orc. */
612GEN_LOGICAL2(orc, 0x0C);
613/* xor & xor. */
9a64fbe4
FB		 614GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
615{
616 gen_op_load_gpr_T0(rS(ctx->opcode));
617 /* Optimisation for "set to zero" case */
618 if (rS(ctx->opcode) != rB(ctx->opcode)) {
619 gen_op_load_gpr_T1(rB(ctx->opcode));
620 gen_op_xor();
621 } else {
622 gen_op_set_T0(0);
623 }
624 if (Rc(ctx->opcode) != 0)
625 gen_op_set_Rc0();
626 gen_op_store_T0_gpr(rA(ctx->opcode));
627}
79aceca5
FB		 628/* ori */
629GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
630{
631 uint32_t uimm = UIMM(ctx->opcode);
632
9a64fbe4
FB		 633 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
634 /* NOP */
635 return;
79aceca5 636 }
79aceca5 637 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 638 if (uimm != 0)
79aceca5
FB		 639 gen_op_ori(uimm);
640 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 641}
642/* oris */
643GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
644{
645 uint32_t uimm = UIMM(ctx->opcode);
646
9a64fbe4
FB		 647 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
648 /* NOP */
649 return;
79aceca5 650 }
79aceca5 651 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 652 if (uimm != 0)
79aceca5
FB		 653 gen_op_ori(uimm << 16);
654 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 655}
656/* xori */
657GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
658{
9a64fbe4
FB		 659 uint32_t uimm = UIMM(ctx->opcode);
660
661 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
662 /* NOP */
663 return;
664 }
79aceca5 665 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 666 if (uimm != 0)
4b3686fa 667 gen_op_xori(uimm);
79aceca5 668 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 669}
670
671/* xoris */
672GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
673{
9a64fbe4
FB		 674 uint32_t uimm = UIMM(ctx->opcode);
675
676 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
677 /* NOP */
678 return;
679 }
79aceca5 680 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 681 if (uimm != 0)
4b3686fa 682 gen_op_xori(uimm << 16);
79aceca5 683 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 684}
685
686/*** Integer rotate ***/
687/* rlwimi & rlwimi. */
688GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
689{
690 uint32_t mb, me;
691
692 mb = MB(ctx->opcode);
693 me = ME(ctx->opcode);
694 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 695 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 696 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
697 if (Rc(ctx->opcode) != 0)
698 gen_op_set_Rc0();
699 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 700}
701/* rlwinm & rlwinm. */
702GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
703{
704 uint32_t mb, me, sh;
705
706 sh = SH(ctx->opcode);
707 mb = MB(ctx->opcode);
708 me = ME(ctx->opcode);
709 gen_op_load_gpr_T0(rS(ctx->opcode));
4b3686fa
FB		 710#if 1 // TRY
711 if (sh == 0) {
712 gen_op_andi_(MASK(mb, me));
713 goto store;
714 }
715#endif
79aceca5
FB		 716 if (mb == 0) {
717 if (me == 31) {
718 gen_op_rotlwi(sh);
719 goto store;
4b3686fa 720#if 0
79aceca5
FB		 721 } else if (me == (31 - sh)) {
722 gen_op_slwi(sh);
723 goto store;
4b3686fa 724#endif
79aceca5
FB		 725 }
726 } else if (me == 31) {
4b3686fa 727#if 0
79aceca5
FB		 728 if (sh == (32 - mb)) {
729 gen_op_srwi(mb);
730 goto store;
79aceca5 731 }
4b3686fa 732#endif
79aceca5
FB		 733 }
734 gen_op_rlwinm(sh, MASK(mb, me));
735store:
736 if (Rc(ctx->opcode) != 0)
737 gen_op_set_Rc0();
738 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 739}
740/* rlwnm & rlwnm. */
741GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
742{
743 uint32_t mb, me;
744
745 mb = MB(ctx->opcode);
746 me = ME(ctx->opcode);
747 gen_op_load_gpr_T0(rS(ctx->opcode));
748 gen_op_load_gpr_T1(rB(ctx->opcode));
749 if (mb == 0 && me == 31) {
750 gen_op_rotl();
751 } else
752 {
753 gen_op_rlwnm(MASK(mb, me));
754 }
755 if (Rc(ctx->opcode) != 0)
756 gen_op_set_Rc0();
757 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 758}
759
760/*** Integer shift ***/
761/* slw & slw. */
762__GEN_LOGICAL2(slw, 0x18, 0x00);
763/* sraw & sraw. */
764__GEN_LOGICAL2(sraw, 0x18, 0x18);
765/* srawi & srawi. */
766GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
767{
768 gen_op_load_gpr_T0(rS(ctx->opcode));
4ecc3190 769 if (SH(ctx->opcode) != 0)
79aceca5
FB		 770 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
771 if (Rc(ctx->opcode) != 0)
772 gen_op_set_Rc0();
773 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 774}
775/* srw & srw. */
776__GEN_LOGICAL2(srw, 0x18, 0x10);
777
778/*** Floating-Point arithmetic ***/
4ecc3190 779#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
9a64fbe4
FB		 780GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
781{ \
3cc62370
FB		 782 if (!ctx->fpu_enabled) { \
783 RET_EXCP(ctx, EXCP_NO_FP, 0); \
784 return; \
785 } \
9a64fbe4
FB		 786 gen_op_reset_scrfx(); \
787 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
788 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
789 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
4ecc3190
FB		 790 gen_op_f##op(); \
791 if (isfloat) { \
792 gen_op_frsp(); \
793 } \
9a64fbe4
FB		 794 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
795 if (Rc(ctx->opcode)) \
796 gen_op_set_Rc1(); \
797}
798
799#define GEN_FLOAT_ACB(name, op2) \
4ecc3190
FB		 800_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
801_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
9a64fbe4 802
4ecc3190 803#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 804GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
805{ \
3cc62370
FB		 806 if (!ctx->fpu_enabled) { \
807 RET_EXCP(ctx, EXCP_NO_FP, 0); \
808 return; \
809 } \
9a64fbe4
FB		 810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
812 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
4ecc3190
FB		 813 gen_op_f##op(); \
814 if (isfloat) { \
815 gen_op_frsp(); \
816 } \
9a64fbe4
FB		 817 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
818 if (Rc(ctx->opcode)) \
819 gen_op_set_Rc1(); \
820}
821#define GEN_FLOAT_AB(name, op2, inval) \
4ecc3190
FB		 822_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
823_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4 824
4ecc3190 825#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
9a64fbe4
FB		 826GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
827{ \
3cc62370
FB		 828 if (!ctx->fpu_enabled) { \
829 RET_EXCP(ctx, EXCP_NO_FP, 0); \
830 return; \
831 } \
9a64fbe4
FB		 832 gen_op_reset_scrfx(); \
833 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
834 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
4ecc3190
FB		 835 gen_op_f##op(); \
836 if (isfloat) { \
837 gen_op_frsp(); \
838 } \
9a64fbe4
FB		 839 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
840 if (Rc(ctx->opcode)) \
841 gen_op_set_Rc1(); \
842}
843#define GEN_FLOAT_AC(name, op2, inval) \
4ecc3190
FB		 844_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
845_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
9a64fbe4
FB		 846
847#define GEN_FLOAT_B(name, op2, op3) \
848GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
849{ \
3cc62370
FB		 850 if (!ctx->fpu_enabled) { \
851 RET_EXCP(ctx, EXCP_NO_FP, 0); \
852 return; \
853 } \
9a64fbe4
FB		 854 gen_op_reset_scrfx(); \
855 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
856 gen_op_f##name(); \
857 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
858 if (Rc(ctx->opcode)) \
859 gen_op_set_Rc1(); \
79aceca5
FB		 860}
861
4ecc3190
FB		 862#define GEN_FLOAT_BS(name, op1, op2) \
863GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
9a64fbe4 864{ \
3cc62370
FB		 865 if (!ctx->fpu_enabled) { \
866 RET_EXCP(ctx, EXCP_NO_FP, 0); \
867 return; \
868 } \
9a64fbe4
FB		 869 gen_op_reset_scrfx(); \
870 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
871 gen_op_f##name(); \
872 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
873 if (Rc(ctx->opcode)) \
874 gen_op_set_Rc1(); \
79aceca5
FB		 875}
876
9a64fbe4
FB		 877/* fadd - fadds */
878GEN_FLOAT_AB(add, 0x15, 0x000007C0);
4ecc3190 879/* fdiv - fdivs */
9a64fbe4 880GEN_FLOAT_AB(div, 0x12, 0x000007C0);
4ecc3190 881/* fmul - fmuls */
9a64fbe4 882GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 883
884/* fres */
4ecc3190 885GEN_FLOAT_BS(res, 0x3B, 0x18);
79aceca5
FB		 886
887/* frsqrte */
4ecc3190 888GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
79aceca5
FB		 889
890/* fsel */
4ecc3190
FB		 891_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
892/* fsub - fsubs */
9a64fbe4 893GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 894/* Optional: */
895/* fsqrt */
c7d344af
FB		 896GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
897{
898 if (!ctx->fpu_enabled) {
899 RET_EXCP(ctx, EXCP_NO_FP, 0);
900 return;
901 }
902 gen_op_reset_scrfx();
903 gen_op_load_fpr_FT0(rB(ctx->opcode));
904 gen_op_fsqrt();
905 gen_op_store_FT0_fpr(rD(ctx->opcode));
906 if (Rc(ctx->opcode))
907 gen_op_set_Rc1();
908}
79aceca5 909
9a64fbe4 910GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 911{
3cc62370
FB		 912 if (!ctx->fpu_enabled) {
913 RET_EXCP(ctx, EXCP_NO_FP, 0);
914 return;
915 }
9a64fbe4
FB		 916 gen_op_reset_scrfx();
917 gen_op_load_fpr_FT0(rB(ctx->opcode));
4ecc3190
FB		 918 gen_op_fsqrt();
919 gen_op_frsp();
9a64fbe4
FB		 920 gen_op_store_FT0_fpr(rD(ctx->opcode));
921 if (Rc(ctx->opcode))
922 gen_op_set_Rc1();
79aceca5
FB		 923}
924
925/*** Floating-Point multiply-and-add ***/
4ecc3190 926/* fmadd - fmadds */
9a64fbe4 927GEN_FLOAT_ACB(madd, 0x1D);
4ecc3190 928/* fmsub - fmsubs */
9a64fbe4 929GEN_FLOAT_ACB(msub, 0x1C);
4ecc3190 930/* fnmadd - fnmadds */
9a64fbe4 931GEN_FLOAT_ACB(nmadd, 0x1F);
4ecc3190 932/* fnmsub - fnmsubs */
9a64fbe4 933GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 934
935/*** Floating-Point round & convert ***/
936/* fctiw */
9a64fbe4 937GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 938/* fctiwz */
9a64fbe4 939GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 940/* frsp */
9a64fbe4 941GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 942
943/*** Floating-Point compare ***/
944/* fcmpo */
945GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
946{
3cc62370
FB		 947 if (!ctx->fpu_enabled) {
948 RET_EXCP(ctx, EXCP_NO_FP, 0);
949 return;
950 }
9a64fbe4
FB		 951 gen_op_reset_scrfx();
952 gen_op_load_fpr_FT0(rA(ctx->opcode));
953 gen_op_load_fpr_FT1(rB(ctx->opcode));
954 gen_op_fcmpo();
955 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 956}
957
958/* fcmpu */
959GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
960{
3cc62370
FB		 961 if (!ctx->fpu_enabled) {
962 RET_EXCP(ctx, EXCP_NO_FP, 0);
963 return;
964 }
9a64fbe4
FB		 965 gen_op_reset_scrfx();
966 gen_op_load_fpr_FT0(rA(ctx->opcode));
967 gen_op_load_fpr_FT1(rB(ctx->opcode));
968 gen_op_fcmpu();
969 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 970}
971
9a64fbe4
FB		 972/*** Floating-point move ***/
973/* fabs */
974GEN_FLOAT_B(abs, 0x08, 0x08);
975
976/* fmr - fmr. */
977GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
978{
3cc62370
FB		 979 if (!ctx->fpu_enabled) {
980 RET_EXCP(ctx, EXCP_NO_FP, 0);
981 return;
982 }
9a64fbe4
FB		 983 gen_op_reset_scrfx();
984 gen_op_load_fpr_FT0(rB(ctx->opcode));
985 gen_op_store_FT0_fpr(rD(ctx->opcode));
986 if (Rc(ctx->opcode))
987 gen_op_set_Rc1();
988}
989
990/* fnabs */
991GEN_FLOAT_B(nabs, 0x08, 0x04);
992/* fneg */
993GEN_FLOAT_B(neg, 0x08, 0x01);
994
79aceca5
FB		 995/*** Floating-Point status & ctrl register ***/
996/* mcrfs */
997GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
998{
3cc62370
FB		 999 if (!ctx->fpu_enabled) {
1000 RET_EXCP(ctx, EXCP_NO_FP, 0);
1001 return;
1002 }
fb0eaffc
FB		 1003 gen_op_load_fpscr_T0(crfS(ctx->opcode));
1004 gen_op_store_T0_crf(crfD(ctx->opcode));
1005 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 1006}
1007
1008/* mffs */
1009GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1010{
3cc62370
FB		 1011 if (!ctx->fpu_enabled) {
1012 RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 return;
1014 }
28b6751f 1015 gen_op_load_fpscr();
fb0eaffc
FB		 1016 gen_op_store_FT0_fpr(rD(ctx->opcode));
1017 if (Rc(ctx->opcode))
1018 gen_op_set_Rc1();
79aceca5
FB		 1019}
1020
1021/* mtfsb0 */
1022GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1023{
fb0eaffc
FB		 1024 uint8_t crb;
1025
3cc62370
FB		 1026 if (!ctx->fpu_enabled) {
1027 RET_EXCP(ctx, EXCP_NO_FP, 0);
1028 return;
1029 }
fb0eaffc
FB		 1030 crb = crbD(ctx->opcode) >> 2;
1031 gen_op_load_fpscr_T0(crb);
1032 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1033 gen_op_store_T0_fpscr(crb);
1034 if (Rc(ctx->opcode))
1035 gen_op_set_Rc1();
79aceca5
FB		 1036}
1037
1038/* mtfsb1 */
1039GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1040{
fb0eaffc
FB		 1041 uint8_t crb;
1042
3cc62370
FB		 1043 if (!ctx->fpu_enabled) {
1044 RET_EXCP(ctx, EXCP_NO_FP, 0);
1045 return;
1046 }
fb0eaffc
FB		 1047 crb = crbD(ctx->opcode) >> 2;
1048 gen_op_load_fpscr_T0(crb);
1049 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1050 gen_op_store_T0_fpscr(crb);
1051 if (Rc(ctx->opcode))
1052 gen_op_set_Rc1();
79aceca5
FB		 1053}
1054
1055/* mtfsf */
1056GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1057{
3cc62370
FB		 1058 if (!ctx->fpu_enabled) {
1059 RET_EXCP(ctx, EXCP_NO_FP, 0);
1060 return;
1061 }
fb0eaffc 1062 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 1063 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 1064 if (Rc(ctx->opcode))
1065 gen_op_set_Rc1();
79aceca5
FB		 1066}
1067
1068/* mtfsfi */
1069GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1070{
3cc62370
FB		 1071 if (!ctx->fpu_enabled) {
1072 RET_EXCP(ctx, EXCP_NO_FP, 0);
1073 return;
1074 }
fb0eaffc
FB		 1075 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1076 if (Rc(ctx->opcode))
1077 gen_op_set_Rc1();
79aceca5
FB		 1078}
1079
1080/*** Integer load ***/
111bfab3 1081#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
9a64fbe4 1082#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1083#define OP_LD_TABLE(width) \
1084static GenOpFunc *gen_op_l##width[] = { \
1085 &gen_op_l##width##_raw, \
1086 &gen_op_l##width##_le_raw, \
1087};
1088#define OP_ST_TABLE(width) \
1089static GenOpFunc *gen_op_st##width[] = { \
1090 &gen_op_st##width##_raw, \
1091 &gen_op_st##width##_le_raw, \
1092};
1093/* Byte access routine are endian safe */
1094#define gen_op_stb_le_raw gen_op_stb_raw
1095#define gen_op_lbz_le_raw gen_op_lbz_raw
9a64fbe4 1096#else
9a64fbe4
FB		 1097#define OP_LD_TABLE(width) \
1098static GenOpFunc *gen_op_l##width[] = { \
1099 &gen_op_l##width##_user, \
111bfab3 1100 &gen_op_l##width##_le_user, \
9a64fbe4 1101 &gen_op_l##width##_kernel, \
111bfab3
FB		 1102 &gen_op_l##width##_le_kernel, \
1103};
9a64fbe4
FB		 1104#define OP_ST_TABLE(width) \
1105static GenOpFunc *gen_op_st##width[] = { \
1106 &gen_op_st##width##_user, \
111bfab3 1107 &gen_op_st##width##_le_user, \
9a64fbe4 1108 &gen_op_st##width##_kernel, \
111bfab3
FB		 1109 &gen_op_st##width##_le_kernel, \
1110};
1111/* Byte access routine are endian safe */
1112#define gen_op_stb_le_user gen_op_stb_user
1113#define gen_op_lbz_le_user gen_op_lbz_user
1114#define gen_op_stb_le_kernel gen_op_stb_kernel
1115#define gen_op_lbz_le_kernel gen_op_lbz_kernel
9a64fbe4
FB		 1116#endif
1117
1118#define GEN_LD(width, opc) \
79aceca5
FB		 1119GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1120{ \
1121 uint32_t simm = SIMM(ctx->opcode); \
1122 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1123 gen_op_set_T0(simm); \
79aceca5
FB		 1124 } else { \
1125 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1126 if (simm != 0) \
1127 gen_op_addi(simm); \
79aceca5 1128 } \
9a64fbe4 1129 op_ldst(l##width); \
79aceca5 1130 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1131}
1132
9a64fbe4 1133#define GEN_LDU(width, opc) \
79aceca5
FB		 1134GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1135{ \
9a64fbe4 1136 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1137 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1138 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1139 RET_INVAL(ctx); \
1140 return; \
9a64fbe4 1141 } \
79aceca5 1142 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1143 if (simm != 0) \
1144 gen_op_addi(simm); \
1145 op_ldst(l##width); \
79aceca5
FB		 1146 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1148}
1149
9a64fbe4 1150#define GEN_LDUX(width, opc) \
79aceca5
FB		 1151GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1152{ \
1153 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1154 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1155 RET_INVAL(ctx); \
1156 return; \
9a64fbe4 1157 } \
79aceca5
FB		 1158 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1159 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1160 gen_op_add(); \
1161 op_ldst(l##width); \
79aceca5
FB		 1162 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1163 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1164}
1165
9a64fbe4 1166#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1167GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1168{ \
1169 if (rA(ctx->opcode) == 0) { \
1170 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1171 } else { \
1172 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1173 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1174 gen_op_add(); \
79aceca5 1175 } \
9a64fbe4 1176 op_ldst(l##width); \
79aceca5 1177 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1178}
1179
9a64fbe4
FB		 1180#define GEN_LDS(width, op) \
1181OP_LD_TABLE(width); \
1182GEN_LD(width, op | 0x20); \
1183GEN_LDU(width, op | 0x21); \
1184GEN_LDUX(width, op | 0x01); \
1185GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1186
1187/* lbz lbzu lbzux lbzx */
9a64fbe4 1188GEN_LDS(bz, 0x02);
79aceca5 1189/* lha lhau lhaux lhax */
9a64fbe4 1190GEN_LDS(ha, 0x0A);
79aceca5 1191/* lhz lhzu lhzux lhzx */
9a64fbe4 1192GEN_LDS(hz, 0x08);
79aceca5 1193/* lwz lwzu lwzux lwzx */
9a64fbe4 1194GEN_LDS(wz, 0x00);
79aceca5
FB		 1195
1196/*** Integer store ***/
9a64fbe4 1197#define GEN_ST(width, opc) \
79aceca5
FB		 1198GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1199{ \
1200 uint32_t simm = SIMM(ctx->opcode); \
1201 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1202 gen_op_set_T0(simm); \
79aceca5
FB		 1203 } else { \
1204 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1205 if (simm != 0) \
1206 gen_op_addi(simm); \
79aceca5 1207 } \
9a64fbe4
FB		 1208 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1209 op_ldst(st##width); \
79aceca5
FB		 1210}
1211
9a64fbe4 1212#define GEN_STU(width, opc) \
79aceca5
FB		 1213GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1214{ \
9a64fbe4
FB		 1215 uint32_t simm = SIMM(ctx->opcode); \
1216 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1217 RET_INVAL(ctx); \
1218 return; \
9a64fbe4 1219 } \
79aceca5 1220 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1221 if (simm != 0) \
1222 gen_op_addi(simm); \
79aceca5 1223 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1224 op_ldst(st##width); \
79aceca5 1225 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1226}
1227
9a64fbe4 1228#define GEN_STUX(width, opc) \
79aceca5
FB		 1229GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1230{ \
9a64fbe4 1231 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1232 RET_INVAL(ctx); \
1233 return; \
9a64fbe4 1234 } \
79aceca5
FB		 1235 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1236 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1237 gen_op_add(); \
1238 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1239 op_ldst(st##width); \
79aceca5 1240 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1241}
1242
9a64fbe4 1243#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1244GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1245{ \
1246 if (rA(ctx->opcode) == 0) { \
1247 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1248 } else { \
1249 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1250 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1251 gen_op_add(); \
79aceca5 1252 } \
9a64fbe4
FB		 1253 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1254 op_ldst(st##width); \
79aceca5
FB		 1255}
1256
9a64fbe4
FB		 1257#define GEN_STS(width, op) \
1258OP_ST_TABLE(width); \
1259GEN_ST(width, op | 0x20); \
1260GEN_STU(width, op | 0x21); \
1261GEN_STUX(width, op | 0x01); \
1262GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1263
1264/* stb stbu stbux stbx */
9a64fbe4 1265GEN_STS(b, 0x06);
79aceca5 1266/* sth sthu sthux sthx */
9a64fbe4 1267GEN_STS(h, 0x0C);
79aceca5 1268/* stw stwu stwux stwx */
9a64fbe4 1269GEN_STS(w, 0x04);
79aceca5
FB		 1270
1271/*** Integer load and store with byte reverse ***/
1272/* lhbrx */
9a64fbe4
FB		 1273OP_LD_TABLE(hbr);
1274GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1275/* lwbrx */
9a64fbe4
FB		 1276OP_LD_TABLE(wbr);
1277GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1278/* sthbrx */
9a64fbe4
FB		 1279OP_ST_TABLE(hbr);
1280GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1281/* stwbrx */
9a64fbe4
FB		 1282OP_ST_TABLE(wbr);
1283GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1284
1285/*** Integer load and store multiple ***/
111bfab3 1286#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
9a64fbe4 1287#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1288static GenOpFunc1 *gen_op_lmw[] = {
1289 &gen_op_lmw_raw,
1290 &gen_op_lmw_le_raw,
1291};
1292static GenOpFunc1 *gen_op_stmw[] = {
1293 &gen_op_stmw_raw,
1294 &gen_op_stmw_le_raw,
1295};
9a64fbe4 1296#else
9a64fbe4
FB		 1297static GenOpFunc1 *gen_op_lmw[] = {
1298 &gen_op_lmw_user,
111bfab3 1299 &gen_op_lmw_le_user,
9a64fbe4 1300 &gen_op_lmw_kernel,
111bfab3 1301 &gen_op_lmw_le_kernel,
9a64fbe4
FB		 1302};
1303static GenOpFunc1 *gen_op_stmw[] = {
1304 &gen_op_stmw_user,
111bfab3 1305 &gen_op_stmw_le_user,
9a64fbe4 1306 &gen_op_stmw_kernel,
111bfab3 1307 &gen_op_stmw_le_kernel,
9a64fbe4
FB		 1308};
1309#endif
1310
79aceca5
FB		 1311/* lmw */
1312GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1313{
9a64fbe4
FB		 1314 int simm = SIMM(ctx->opcode);
1315
79aceca5 1316 if (rA(ctx->opcode) == 0) {
9a64fbe4 1317 gen_op_set_T0(simm);
79aceca5
FB		 1318 } else {
1319 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1320 if (simm != 0)
1321 gen_op_addi(simm);
79aceca5 1322 }
9a64fbe4 1323 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1324}
1325
1326/* stmw */
1327GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1328{
9a64fbe4
FB		 1329 int simm = SIMM(ctx->opcode);
1330
79aceca5 1331 if (rA(ctx->opcode) == 0) {
9a64fbe4 1332 gen_op_set_T0(simm);
79aceca5
FB		 1333 } else {
1334 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1335 if (simm != 0)
1336 gen_op_addi(simm);
79aceca5 1337 }
9a64fbe4 1338 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1339}
1340
1341/*** Integer load and store strings ***/
9a64fbe4
FB		 1342#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1343#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
111bfab3
FB		 1344#if defined(CONFIG_USER_ONLY)
1345static GenOpFunc1 *gen_op_lswi[] = {
1346 &gen_op_lswi_raw,
1347 &gen_op_lswi_le_raw,
1348};
1349static GenOpFunc3 *gen_op_lswx[] = {
1350 &gen_op_lswx_raw,
1351 &gen_op_lswx_le_raw,
1352};
1353static GenOpFunc1 *gen_op_stsw[] = {
1354 &gen_op_stsw_raw,
1355 &gen_op_stsw_le_raw,
1356};
1357#else
9a64fbe4
FB		 1358static GenOpFunc1 *gen_op_lswi[] = {
1359 &gen_op_lswi_user,
111bfab3 1360 &gen_op_lswi_le_user,
9a64fbe4 1361 &gen_op_lswi_kernel,
111bfab3 1362 &gen_op_lswi_le_kernel,
9a64fbe4
FB		 1363};
1364static GenOpFunc3 *gen_op_lswx[] = {
1365 &gen_op_lswx_user,
111bfab3 1366 &gen_op_lswx_le_user,
9a64fbe4 1367 &gen_op_lswx_kernel,
111bfab3 1368 &gen_op_lswx_le_kernel,
9a64fbe4
FB		 1369};
1370static GenOpFunc1 *gen_op_stsw[] = {
1371 &gen_op_stsw_user,
111bfab3 1372 &gen_op_stsw_le_user,
9a64fbe4 1373 &gen_op_stsw_kernel,
111bfab3 1374 &gen_op_stsw_le_kernel,
9a64fbe4
FB		 1375};
1376#endif
1377
79aceca5 1378/* lswi */
3fc6c082 1379/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 1380 * rA is in the range of registers to be loaded.
1381 * In an other hand, IBM says this is valid, but rA won't be loaded.
1382 * For now, I'll follow the spec...
1383 */
79aceca5
FB		 1384GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1385{
1386 int nb = NB(ctx->opcode);
1387 int start = rD(ctx->opcode);
9a64fbe4 1388 int ra = rA(ctx->opcode);
79aceca5
FB		 1389 int nr;
1390
1391 if (nb == 0)
1392 nb = 32;
1393 nr = nb / 4;
297d8e62
FB		 1394 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1395 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1396 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1397 return;
297d8e62 1398 }
9a64fbe4 1399 if (ra == 0) {
79aceca5
FB		 1400 gen_op_set_T0(0);
1401 } else {
9a64fbe4 1402 gen_op_load_gpr_T0(ra);
79aceca5 1403 }
9a64fbe4 1404 gen_op_set_T1(nb);
8dd4983c
FB		 1405 /* NIP cannot be restored if the memory exception comes from an helper */
1406 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1407 op_ldsts(lswi, start);
79aceca5
FB		 1408}
1409
1410/* lswx */
1411GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1412{
9a64fbe4
FB		 1413 int ra = rA(ctx->opcode);
1414 int rb = rB(ctx->opcode);
1415
1416 if (ra == 0) {
1417 gen_op_load_gpr_T0(rb);
1418 ra = rb;
79aceca5 1419 } else {
9a64fbe4
FB		 1420 gen_op_load_gpr_T0(ra);
1421 gen_op_load_gpr_T1(rb);
1422 gen_op_add();
79aceca5 1423 }
9a64fbe4 1424 gen_op_load_xer_bc();
8dd4983c
FB		 1425 /* NIP cannot be restored if the memory exception comes from an helper */
1426 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1427 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1428}
1429
1430/* stswi */
1431GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1432{
4b3686fa
FB		 1433 int nb = NB(ctx->opcode);
1434
79aceca5
FB		 1435 if (rA(ctx->opcode) == 0) {
1436 gen_op_set_T0(0);
1437 } else {
1438 gen_op_load_gpr_T0(rA(ctx->opcode));
1439 }
4b3686fa
FB		 1440 if (nb == 0)
1441 nb = 32;
1442 gen_op_set_T1(nb);
8dd4983c
FB		 1443 /* NIP cannot be restored if the memory exception comes from an helper */
1444 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1445 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1446}
1447
1448/* stswx */
1449GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1450{
9a64fbe4
FB		 1451 int ra = rA(ctx->opcode);
1452
1453 if (ra == 0) {
1454 gen_op_load_gpr_T0(rB(ctx->opcode));
1455 ra = rB(ctx->opcode);
79aceca5 1456 } else {
9a64fbe4
FB		 1457 gen_op_load_gpr_T0(ra);
1458 gen_op_load_gpr_T1(rB(ctx->opcode));
1459 gen_op_add();
79aceca5 1460 }
9a64fbe4 1461 gen_op_load_xer_bc();
8dd4983c
FB		 1462 /* NIP cannot be restored if the memory exception comes from an helper */
1463 gen_op_update_nip((ctx)->nip - 4);
9a64fbe4 1464 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1465}
1466
1467/*** Memory synchronisation ***/
1468/* eieio */
1469GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1470{
79aceca5
FB		 1471}
1472
1473/* isync */
1474GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1475{
79aceca5
FB		 1476}
1477
111bfab3
FB		 1478#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1479#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
9a64fbe4 1480#if defined(CONFIG_USER_ONLY)
111bfab3
FB		 1481static GenOpFunc *gen_op_lwarx[] = {
1482 &gen_op_lwarx_raw,
1483 &gen_op_lwarx_le_raw,
1484};
1485static GenOpFunc *gen_op_stwcx[] = {
1486 &gen_op_stwcx_raw,
1487 &gen_op_stwcx_le_raw,
1488};
9a64fbe4 1489#else
985a19d6
FB		 1490static GenOpFunc *gen_op_lwarx[] = {
1491 &gen_op_lwarx_user,
111bfab3 1492 &gen_op_lwarx_le_user,
985a19d6 1493 &gen_op_lwarx_kernel,
111bfab3 1494 &gen_op_lwarx_le_kernel,
985a19d6 1495};
9a64fbe4
FB		 1496static GenOpFunc *gen_op_stwcx[] = {
1497 &gen_op_stwcx_user,
111bfab3 1498 &gen_op_stwcx_le_user,
9a64fbe4 1499 &gen_op_stwcx_kernel,
111bfab3 1500 &gen_op_stwcx_le_kernel,
9a64fbe4
FB		 1501};
1502#endif
1503
111bfab3 1504/* lwarx */
9a64fbe4 1505GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1506{
79aceca5
FB		 1507 if (rA(ctx->opcode) == 0) {
1508 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1509 } else {
1510 gen_op_load_gpr_T0(rA(ctx->opcode));
1511 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1512 gen_op_add();
79aceca5 1513 }
985a19d6 1514 op_lwarx();
79aceca5 1515 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1516}
1517
1518/* stwcx. */
9a64fbe4 1519GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1520{
79aceca5
FB		 1521 if (rA(ctx->opcode) == 0) {
1522 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1523 } else {
1524 gen_op_load_gpr_T0(rA(ctx->opcode));
1525 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1526 gen_op_add();
79aceca5 1527 }
9a64fbe4
FB		 1528 gen_op_load_gpr_T1(rS(ctx->opcode));
1529 op_stwcx();
79aceca5
FB		 1530}
1531
1532/* sync */
1533GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1534{
79aceca5
FB		 1535}
1536
1537/*** Floating-point load ***/
9a64fbe4 1538#define GEN_LDF(width, opc) \
c7d344af 1539GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1540{ \
1541 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1542 if (!ctx->fpu_enabled) { \
1543 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1544 return; \
1545 } \
79aceca5 1546 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1547 gen_op_set_T0(simm); \
79aceca5
FB		 1548 } else { \
1549 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1550 if (simm != 0) \
1551 gen_op_addi(simm); \
79aceca5 1552 } \
9a64fbe4
FB		 1553 op_ldst(l##width); \
1554 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1555}
1556
9a64fbe4 1557#define GEN_LDUF(width, opc) \
c7d344af 1558GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1559{ \
9a64fbe4 1560 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1561 if (!ctx->fpu_enabled) { \
1562 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1563 return; \
1564 } \
79aceca5 1565 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1566 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1567 RET_INVAL(ctx); \
1568 return; \
9a64fbe4 1569 } \
79aceca5 1570 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1571 if (simm != 0) \
1572 gen_op_addi(simm); \
1573 op_ldst(l##width); \
1574 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1575 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1576}
1577
9a64fbe4 1578#define GEN_LDUXF(width, opc) \
c7d344af 1579GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1580{ \
4ecc3190
FB		 1581 if (!ctx->fpu_enabled) { \
1582 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1583 return; \
1584 } \
79aceca5 1585 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1586 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1587 RET_INVAL(ctx); \
1588 return; \
9a64fbe4 1589 } \
79aceca5
FB		 1590 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1591 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1592 gen_op_add(); \
1593 op_ldst(l##width); \
1594 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1595 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1596}
1597
9a64fbe4 1598#define GEN_LDXF(width, opc2, opc3) \
c7d344af 1599GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1600{ \
4ecc3190
FB		 1601 if (!ctx->fpu_enabled) { \
1602 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1603 return; \
1604 } \
79aceca5
FB		 1605 if (rA(ctx->opcode) == 0) { \
1606 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1607 } else { \
1608 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1609 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1610 gen_op_add(); \
79aceca5 1611 } \
9a64fbe4
FB		 1612 op_ldst(l##width); \
1613 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1614}
1615
9a64fbe4
FB		 1616#define GEN_LDFS(width, op) \
1617OP_LD_TABLE(width); \
1618GEN_LDF(width, op | 0x20); \
1619GEN_LDUF(width, op | 0x21); \
1620GEN_LDUXF(width, op | 0x01); \
1621GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1622
1623/* lfd lfdu lfdux lfdx */
9a64fbe4 1624GEN_LDFS(fd, 0x12);
79aceca5 1625/* lfs lfsu lfsux lfsx */
9a64fbe4 1626GEN_LDFS(fs, 0x10);
79aceca5
FB		 1627
1628/*** Floating-point store ***/
1629#define GEN_STF(width, opc) \
c7d344af 1630GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5
FB		 1631{ \
1632 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1633 if (!ctx->fpu_enabled) { \
1634 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1635 return; \
1636 } \
79aceca5 1637 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1638 gen_op_set_T0(simm); \
79aceca5
FB		 1639 } else { \
1640 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1641 if (simm != 0) \
1642 gen_op_addi(simm); \
79aceca5 1643 } \
9a64fbe4
FB		 1644 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1645 op_ldst(st##width); \
79aceca5
FB		 1646}
1647
9a64fbe4 1648#define GEN_STUF(width, opc) \
c7d344af 1649GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
79aceca5 1650{ \
9a64fbe4 1651 uint32_t simm = SIMM(ctx->opcode); \
4ecc3190
FB		 1652 if (!ctx->fpu_enabled) { \
1653 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1654 return; \
1655 } \
9a64fbe4 1656 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1657 RET_INVAL(ctx); \
1658 return; \
9a64fbe4 1659 } \
79aceca5 1660 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1661 if (simm != 0) \
1662 gen_op_addi(simm); \
1663 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1664 op_ldst(st##width); \
79aceca5 1665 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1666}
1667
9a64fbe4 1668#define GEN_STUXF(width, opc) \
c7d344af 1669GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
79aceca5 1670{ \
4ecc3190
FB		 1671 if (!ctx->fpu_enabled) { \
1672 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1673 return; \
1674 } \
9a64fbe4 1675 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1676 RET_INVAL(ctx); \
1677 return; \
9a64fbe4 1678 } \
79aceca5
FB		 1679 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1680 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1681 gen_op_add(); \
1682 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1683 op_ldst(st##width); \
79aceca5 1684 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1685}
1686
9a64fbe4 1687#define GEN_STXF(width, opc2, opc3) \
c7d344af 1688GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
79aceca5 1689{ \
4ecc3190
FB		 1690 if (!ctx->fpu_enabled) { \
1691 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1692 return; \
1693 } \
79aceca5
FB		 1694 if (rA(ctx->opcode) == 0) { \
1695 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1696 } else { \
1697 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1698 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1699 gen_op_add(); \
79aceca5 1700 } \
9a64fbe4
FB		 1701 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1702 op_ldst(st##width); \
79aceca5
FB		 1703}
1704
9a64fbe4
FB		 1705#define GEN_STFS(width, op) \
1706OP_ST_TABLE(width); \
1707GEN_STF(width, op | 0x20); \
1708GEN_STUF(width, op | 0x21); \
1709GEN_STUXF(width, op | 0x01); \
1710GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1711
1712/* stfd stfdu stfdux stfdx */
9a64fbe4 1713GEN_STFS(fd, 0x16);
79aceca5 1714/* stfs stfsu stfsux stfsx */
9a64fbe4 1715GEN_STFS(fs, 0x14);
79aceca5
FB		 1716
1717/* Optional: */
1718/* stfiwx */
1719GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1720{
3cc62370
FB		 1721 if (!ctx->fpu_enabled) {
1722 RET_EXCP(ctx, EXCP_NO_FP, 0);
1723 return;
1724 }
9fddaa0c 1725 RET_INVAL(ctx);
79aceca5
FB		 1726}
1727
1728/*** Branch ***/
79aceca5 1729
c1942362
FB		 1730static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1731{
1732 TranslationBlock *tb;
1733 tb = ctx->tb;
1734 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1735 if (n == 0)
1736 gen_op_goto_tb0(TBPARAM(tb));
1737 else
1738 gen_op_goto_tb1(TBPARAM(tb));
1739 gen_op_set_T1(dest);
1740 gen_op_b_T1();
1741 gen_op_set_T0((long)tb + n);
ea4e754f
FB		 1742 if (ctx->singlestep_enabled)
1743 gen_op_debug();
c1942362
FB		 1744 gen_op_exit_tb();
1745 } else {
1746 gen_op_set_T1(dest);
1747 gen_op_b_T1();
ea4e754f
FB		 1748 if (ctx->singlestep_enabled)
1749 gen_op_debug();
c1942362
FB		 1750 gen_op_set_T0(0);
1751 gen_op_exit_tb();
1752 }
c53be334
FB		 1753}
1754
79aceca5
FB		 1755/* b ba bl bla */
1756GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1757{
38a64f9d
FB		 1758 uint32_t li, target;
1759
1760 /* sign extend LI */
1761 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
79aceca5
FB		 1762
1763 if (AA(ctx->opcode) == 0)
046d6672 1764 target = ctx->nip + li - 4;
79aceca5 1765 else
9a64fbe4 1766 target = li;
9a64fbe4 1767 if (LK(ctx->opcode)) {
046d6672 1768 gen_op_setlr(ctx->nip);
9a64fbe4 1769 }
c1942362 1770 gen_goto_tb(ctx, 0, target);
9a64fbe4 1771 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1772}
1773
e98a6e40
FB		 1774#define BCOND_IM 0
1775#define BCOND_LR 1
1776#define BCOND_CTR 2
1777
1778static inline void gen_bcond(DisasContext *ctx, int type)
1779{
1780 uint32_t target = 0;
1781 uint32_t bo = BO(ctx->opcode);
1782 uint32_t bi = BI(ctx->opcode);
1783 uint32_t mask;
1784 uint32_t li;
1785
e98a6e40
FB		 1786 if ((bo & 0x4) == 0)
1787 gen_op_dec_ctr();
1788 switch(type) {
1789 case BCOND_IM:
18fba28c 1790 li = (int32_t)((int16_t)(BD(ctx->opcode)));
e98a6e40 1791 if (AA(ctx->opcode) == 0) {
046d6672 1792 target = ctx->nip + li - 4;
e98a6e40
FB		 1793 } else {
1794 target = li;
1795 }
1796 break;
1797 case BCOND_CTR:
1798 gen_op_movl_T1_ctr();
1799 break;
1800 default:
1801 case BCOND_LR:
1802 gen_op_movl_T1_lr();
1803 break;
1804 }
1805 if (LK(ctx->opcode)) {
046d6672 1806 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1807 }
1808 if (bo & 0x10) {
1809 /* No CR condition */
1810 switch (bo & 0x6) {
1811 case 0:
1812 gen_op_test_ctr();
1813 break;
1814 case 2:
1815 gen_op_test_ctrz();
1816 break;
1817 default:
1818 case 4:
1819 case 6:
1820 if (type == BCOND_IM) {
c1942362 1821 gen_goto_tb(ctx, 0, target);
e98a6e40
FB		 1822 } else {
1823 gen_op_b_T1();
e98a6e40
FB		 1824 }
1825 goto no_test;
1826 }
1827 } else {
1828 mask = 1 << (3 - (bi & 0x03));
1829 gen_op_load_crf_T0(bi >> 2);
1830 if (bo & 0x8) {
1831 switch (bo & 0x6) {
1832 case 0:
1833 gen_op_test_ctr_true(mask);
1834 break;
1835 case 2:
1836 gen_op_test_ctrz_true(mask);
1837 break;
1838 default:
1839 case 4:
1840 case 6:
1841 gen_op_test_true(mask);
1842 break;
1843 }
1844 } else {
1845 switch (bo & 0x6) {
1846 case 0:
1847 gen_op_test_ctr_false(mask);
1848 break;
1849 case 2:
1850 gen_op_test_ctrz_false(mask);
1851 break;
1852 default:
1853 case 4:
1854 case 6:
1855 gen_op_test_false(mask);
1856 break;
1857 }
1858 }
1859 }
1860 if (type == BCOND_IM) {
c53be334
FB		 1861 int l1 = gen_new_label();
1862 gen_op_jz_T0(l1);
c1942362 1863 gen_goto_tb(ctx, 0, target);
c53be334 1864 gen_set_label(l1);
c1942362 1865 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 1866 } else {
046d6672 1867 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1868 }
1869 no_test:
1870 ctx->exception = EXCP_BRANCH;
1871}
1872
1873GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1874{
1875 gen_bcond(ctx, BCOND_IM);
1876}
1877
1878GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1879{
1880 gen_bcond(ctx, BCOND_CTR);
1881}
1882
1883GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1884{
1885 gen_bcond(ctx, BCOND_LR);
1886}
79aceca5
FB		 1887
1888/*** Condition register logical ***/
1889#define GEN_CRLOGIC(op, opc) \
1890GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1891{ \
1892 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1893 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1894 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1895 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1896 gen_op_##op(); \
1897 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1898 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1899 3 - (crbD(ctx->opcode) & 0x03)); \
1900 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1901}
1902
1903/* crand */
1904GEN_CRLOGIC(and, 0x08)
1905/* crandc */
1906GEN_CRLOGIC(andc, 0x04)
1907/* creqv */
1908GEN_CRLOGIC(eqv, 0x09)
1909/* crnand */
1910GEN_CRLOGIC(nand, 0x07)
1911/* crnor */
1912GEN_CRLOGIC(nor, 0x01)
1913/* cror */
1914GEN_CRLOGIC(or, 0x0E)
1915/* crorc */
1916GEN_CRLOGIC(orc, 0x0D)
1917/* crxor */
1918GEN_CRLOGIC(xor, 0x06)
1919/* mcrf */
1920GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1921{
1922 gen_op_load_crf_T0(crfS(ctx->opcode));
1923 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1924}
1925
1926/*** System linkage ***/
1927/* rfi (supervisor only) */
1928GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1929{
9a64fbe4 1930#if defined(CONFIG_USER_ONLY)
9fddaa0c 1931 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1932#else
1933 /* Restore CPU state */
1934 if (!ctx->supervisor) {
9fddaa0c
FB		 1935 RET_PRIVOPC(ctx);
1936 return;
9a64fbe4
FB		 1937 }
1938 gen_op_rfi();
2be0071f 1939 RET_CHG_FLOW(ctx);
9a64fbe4 1940#endif
79aceca5
FB		 1941}
1942
1943/* sc */
1944GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1945{
9a64fbe4 1946#if defined(CONFIG_USER_ONLY)
9fddaa0c 1947 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1948#else
9fddaa0c 1949 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1950#endif
79aceca5
FB		 1951}
1952
1953/*** Trap ***/
1954/* tw */
1955GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1956{
9a64fbe4
FB		 1957 gen_op_load_gpr_T0(rA(ctx->opcode));
1958 gen_op_load_gpr_T1(rB(ctx->opcode));
1959 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1960}
1961
1962/* twi */
1963GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1964{
9a64fbe4
FB		 1965 gen_op_load_gpr_T0(rA(ctx->opcode));
1966#if 0
1967 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1968 SIMM(ctx->opcode), TO(ctx->opcode));
1969#endif
1970 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1971}
1972
1973/*** Processor control ***/
1974static inline int check_spr_access (int spr, int rw, int supervisor)
1975{
1976 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1977
9a64fbe4
FB		 1978#if 0
1979 if (spr != LR && spr != CTR) {
1980 if (loglevel > 0) {
1981 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1982 SPR_ENCODE(spr), supervisor, rw, rights,
1983 (rights >> ((2 * supervisor) + rw)) & 1);
1984 } else {
1985 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1986 SPR_ENCODE(spr), supervisor, rw, rights,
1987 (rights >> ((2 * supervisor) + rw)) & 1);
1988 }
1989 }
1990#endif
1991 if (rights == 0)
1992 return -1;
79aceca5
FB		 1993 rights = rights >> (2 * supervisor);
1994 rights = rights >> rw;
1995
1996 return rights & 1;
1997}
1998
1999/* mcrxr */
2000GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
2001{
2002 gen_op_load_xer_cr();
2003 gen_op_store_T0_crf(crfD(ctx->opcode));
2004 gen_op_clear_xer_cr();
79aceca5
FB		 2005}
2006
2007/* mfcr */
2008GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
2009{
2010 gen_op_load_cr();
2011 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2012}
2013
2014/* mfmsr */
2015GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
2016{
9a64fbe4 2017#if defined(CONFIG_USER_ONLY)
9fddaa0c 2018 RET_PRIVREG(ctx);
9a64fbe4
FB		 2019#else
2020 if (!ctx->supervisor) {
9fddaa0c
FB		 2021 RET_PRIVREG(ctx);
2022 return;
9a64fbe4 2023 }
79aceca5
FB		 2024 gen_op_load_msr();
2025 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 2026#endif
79aceca5
FB		 2027}
2028
3fc6c082
FB		 2029#if 0
2030#define SPR_NOACCESS ((void *)(-1))
2031#else
2032static void spr_noaccess (void *opaque, int sprn)
2033{
2034 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
2035 printf("ERROR: try to access SPR %d !\n", sprn);
2036}
2037#define SPR_NOACCESS (&spr_noaccess)
2038#endif
2039
79aceca5 2040/* mfspr */
3fc6c082 2041static inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 2042{
3fc6c082 2043 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 2044 uint32_t sprn = SPR(ctx->opcode);
2045
3fc6c082
FB		 2046#if !defined(CONFIG_USER_ONLY)
2047 if (ctx->supervisor)
2048 read_cb = ctx->spr_cb[sprn].oea_read;
2049 else
9a64fbe4 2050#endif
3fc6c082
FB		 2051 read_cb = ctx->spr_cb[sprn].uea_read;
2052 if (read_cb != NULL) {
2053 if (read_cb != SPR_NOACCESS) {
2054 (*read_cb)(ctx, sprn);
2055 gen_op_store_T0_gpr(rD(ctx->opcode));
2056 } else {
2057 /* Privilege exception */
f24e5695
FB		 2058 if (loglevel) {
2059 fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
2060 sprn, sprn);
2061 }
3fc6c082 2062 printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
9fddaa0c 2063 RET_PRIVREG(ctx);
79aceca5 2064 }
3fc6c082
FB		 2065 } else {
2066 /* Not defined */
f24e5695
FB		 2067 if (loglevel) {
2068 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
2069 sprn, sprn);
2070 }
3fc6c082
FB		 2071 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
2072 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
79aceca5 2073 }
79aceca5
FB		 2074}
2075
3fc6c082 2076GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 2077{
3fc6c082 2078 gen_op_mfspr(ctx);
79aceca5 2079 }
3fc6c082
FB		 2080
2081/* mftb */
2082GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
2083{
2084 gen_op_mfspr(ctx);
79aceca5
FB		 2085}
2086
2087/* mtcrf */
8dd4983c
FB		 2088/* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2089GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5
FB		 2090{
2091 gen_op_load_gpr_T0(rS(ctx->opcode));
2092 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 2093}
2094
2095/* mtmsr */
2096GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2097{
9a64fbe4 2098#if defined(CONFIG_USER_ONLY)
9fddaa0c 2099 RET_PRIVREG(ctx);
9a64fbe4
FB		 2100#else
2101 if (!ctx->supervisor) {
9fddaa0c
FB		 2102 RET_PRIVREG(ctx);
2103 return;
9a64fbe4 2104 }
e80e1cc4 2105 gen_op_update_nip((ctx)->nip);
79aceca5
FB		 2106 gen_op_load_gpr_T0(rS(ctx->opcode));
2107 gen_op_store_msr();
2108 /* Must stop the translation as machine state (may have) changed */
e80e1cc4 2109 RET_CHG_FLOW(ctx);
9a64fbe4 2110#endif
79aceca5
FB		 2111}
2112
2113/* mtspr */
2114GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2115{
3fc6c082 2116 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 2117 uint32_t sprn = SPR(ctx->opcode);
2118
3fc6c082
FB		 2119#if !defined(CONFIG_USER_ONLY)
2120 if (ctx->supervisor)
2121 write_cb = ctx->spr_cb[sprn].oea_write;
2122 else
9a64fbe4 2123#endif
3fc6c082
FB		 2124 write_cb = ctx->spr_cb[sprn].uea_write;
2125 if (write_cb != NULL) {
2126 if (write_cb != SPR_NOACCESS) {
2127 gen_op_load_gpr_T0(rS(ctx->opcode));
2128 (*write_cb)(ctx, sprn);
2129 } else {
2130 /* Privilege exception */
f24e5695
FB		 2131 if (loglevel) {
2132 fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
2133 sprn, sprn);
2134 }
3fc6c082 2135 printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
9fddaa0c 2136 RET_PRIVREG(ctx);
9a64fbe4 2137 }
3fc6c082
FB		 2138 } else {
2139 /* Not defined */
f24e5695
FB		 2140 if (loglevel) {
2141 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
2142 sprn, sprn);
2143 }
3fc6c082
FB		 2144 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
2145 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
79aceca5 2146 }
79aceca5
FB		 2147}
2148
2149/*** Cache management ***/
2150/* For now, all those will be implemented as nop:
2151 * this is valid, regarding the PowerPC specs...
9a64fbe4 2152 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2153 */
2154/* dcbf */
9a64fbe4 2155GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2156{
a541f297
FB		 2157 if (rA(ctx->opcode) == 0) {
2158 gen_op_load_gpr_T0(rB(ctx->opcode));
2159 } else {
2160 gen_op_load_gpr_T0(rA(ctx->opcode));
2161 gen_op_load_gpr_T1(rB(ctx->opcode));
2162 gen_op_add();
2163 }
2164 op_ldst(lbz);
79aceca5
FB		 2165}
2166
2167/* dcbi (Supervisor only) */
9a64fbe4 2168GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2169{
a541f297 2170#if defined(CONFIG_USER_ONLY)
9fddaa0c 2171 RET_PRIVOPC(ctx);
a541f297
FB		 2172#else
2173 if (!ctx->supervisor) {
9fddaa0c
FB		 2174 RET_PRIVOPC(ctx);
2175 return;
9a64fbe4 2176 }
a541f297
FB		 2177 if (rA(ctx->opcode) == 0) {
2178 gen_op_load_gpr_T0(rB(ctx->opcode));
2179 } else {
2180 gen_op_load_gpr_T0(rA(ctx->opcode));
2181 gen_op_load_gpr_T1(rB(ctx->opcode));
2182 gen_op_add();
2183 }
2184 op_ldst(lbz);
2185 op_ldst(stb);
2186#endif
79aceca5
FB		 2187}
2188
2189/* dcdst */
9a64fbe4 2190GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2191{
a541f297
FB		 2192 if (rA(ctx->opcode) == 0) {
2193 gen_op_load_gpr_T0(rB(ctx->opcode));
2194 } else {
2195 gen_op_load_gpr_T0(rA(ctx->opcode));
2196 gen_op_load_gpr_T1(rB(ctx->opcode));
2197 gen_op_add();
2198 }
2199 op_ldst(lbz);
79aceca5
FB		 2200}
2201
2202/* dcbt */
9a64fbe4 2203GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2204{
79aceca5
FB		 2205}
2206
2207/* dcbtst */
9a64fbe4 2208GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2209{
79aceca5
FB		 2210}
2211
2212/* dcbz */
9a64fbe4
FB		 2213#if defined(CONFIG_USER_ONLY)
2214#define op_dcbz() gen_op_dcbz_raw()
2215#else
2216#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2217static GenOpFunc *gen_op_dcbz[] = {
2218 &gen_op_dcbz_user,
2d5262f9
FB		 2219 &gen_op_dcbz_user,
2220 &gen_op_dcbz_kernel,
9a64fbe4
FB		 2221 &gen_op_dcbz_kernel,
2222};
2223#endif
2224
2225GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2226{
fb0eaffc
FB		 2227 if (rA(ctx->opcode) == 0) {
2228 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2229 } else {
2230 gen_op_load_gpr_T0(rA(ctx->opcode));
2231 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2232 gen_op_add();
fb0eaffc 2233 }
9a64fbe4 2234 op_dcbz();
4b3686fa 2235 gen_op_check_reservation();
79aceca5
FB		 2236}
2237
2238/* icbi */
9a64fbe4 2239GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2240{
fb0eaffc
FB		 2241 if (rA(ctx->opcode) == 0) {
2242 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2243 } else {
2244 gen_op_load_gpr_T0(rA(ctx->opcode));
2245 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2246 gen_op_add();
fb0eaffc 2247 }
9a64fbe4 2248 gen_op_icbi();
79aceca5
FB		 2249}
2250
2251/* Optional: */
2252/* dcba */
c7d344af 2253GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2254{
79aceca5
FB		 2255}
2256
2257/*** Segment register manipulation ***/
2258/* Supervisor only: */
2259/* mfsr */
2260GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2261{
9a64fbe4 2262#if defined(CONFIG_USER_ONLY)
9fddaa0c 2263 RET_PRIVREG(ctx);
9a64fbe4
FB		 2264#else
2265 if (!ctx->supervisor) {
9fddaa0c
FB		 2266 RET_PRIVREG(ctx);
2267 return;
9a64fbe4
FB		 2268 }
2269 gen_op_load_sr(SR(ctx->opcode));
2270 gen_op_store_T0_gpr(rD(ctx->opcode));
2271#endif
79aceca5
FB		 2272}
2273
2274/* mfsrin */
9a64fbe4 2275GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2276{
9a64fbe4 2277#if defined(CONFIG_USER_ONLY)
9fddaa0c 2278 RET_PRIVREG(ctx);
9a64fbe4
FB		 2279#else
2280 if (!ctx->supervisor) {
9fddaa0c
FB		 2281 RET_PRIVREG(ctx);
2282 return;
9a64fbe4
FB		 2283 }
2284 gen_op_load_gpr_T1(rB(ctx->opcode));
2285 gen_op_load_srin();
2286 gen_op_store_T0_gpr(rD(ctx->opcode));
2287#endif
79aceca5
FB		 2288}
2289
2290/* mtsr */
e63c59cb 2291GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2292{
9a64fbe4 2293#if defined(CONFIG_USER_ONLY)
9fddaa0c 2294 RET_PRIVREG(ctx);
9a64fbe4
FB		 2295#else
2296 if (!ctx->supervisor) {
9fddaa0c
FB		 2297 RET_PRIVREG(ctx);
2298 return;
9a64fbe4
FB		 2299 }
2300 gen_op_load_gpr_T0(rS(ctx->opcode));
2301 gen_op_store_sr(SR(ctx->opcode));
f24e5695 2302 RET_STOP(ctx);
9a64fbe4 2303#endif
79aceca5
FB		 2304}
2305
2306/* mtsrin */
9a64fbe4 2307GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2308{
9a64fbe4 2309#if defined(CONFIG_USER_ONLY)
9fddaa0c 2310 RET_PRIVREG(ctx);
9a64fbe4
FB		 2311#else
2312 if (!ctx->supervisor) {
9fddaa0c
FB		 2313 RET_PRIVREG(ctx);
2314 return;
9a64fbe4
FB		 2315 }
2316 gen_op_load_gpr_T0(rS(ctx->opcode));
2317 gen_op_load_gpr_T1(rB(ctx->opcode));
2318 gen_op_store_srin();
f24e5695 2319 RET_STOP(ctx);
9a64fbe4 2320#endif
79aceca5
FB		 2321}
2322
2323/*** Lookaside buffer management ***/
2324/* Optional & supervisor only: */
2325/* tlbia */
3fc6c082 2326GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 2327{
9a64fbe4 2328#if defined(CONFIG_USER_ONLY)
9fddaa0c 2329 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2330#else
2331 if (!ctx->supervisor) {
9fddaa0c
FB		 2332 if (loglevel)
2333 fprintf(logfile, "%s: ! supervisor\n", __func__);
2334 RET_PRIVOPC(ctx);
2335 return;
9a64fbe4
FB		 2336 }
2337 gen_op_tlbia();
f24e5695 2338 RET_STOP(ctx);
9a64fbe4 2339#endif
79aceca5
FB		 2340}
2341
2342/* tlbie */
9a64fbe4 2343GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2344{
9a64fbe4 2345#if defined(CONFIG_USER_ONLY)
9fddaa0c 2346 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2347#else
2348 if (!ctx->supervisor) {
9fddaa0c
FB		 2349 RET_PRIVOPC(ctx);
2350 return;
9a64fbe4
FB		 2351 }
2352 gen_op_load_gpr_T0(rB(ctx->opcode));
2353 gen_op_tlbie();
f24e5695 2354 RET_STOP(ctx);
9a64fbe4 2355#endif
79aceca5
FB		 2356}
2357
2358/* tlbsync */
e63c59cb 2359GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2360{
9a64fbe4 2361#if defined(CONFIG_USER_ONLY)
9fddaa0c 2362 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2363#else
2364 if (!ctx->supervisor) {
9fddaa0c
FB		 2365 RET_PRIVOPC(ctx);
2366 return;
9a64fbe4
FB		 2367 }
2368 /* This has no effect: it should ensure that all previous
2369 * tlbie have completed
2370 */
f24e5695 2371 RET_STOP(ctx);
9a64fbe4 2372#endif
79aceca5
FB		 2373}
2374
2375/*** External control ***/
2376/* Optional: */
9a64fbe4
FB		 2377#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2378#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
111bfab3
FB		 2379#if defined(CONFIG_USER_ONLY)
2380static GenOpFunc *gen_op_eciwx[] = {
2381 &gen_op_eciwx_raw,
2382 &gen_op_eciwx_le_raw,
2383};
2384static GenOpFunc *gen_op_ecowx[] = {
2385 &gen_op_ecowx_raw,
2386 &gen_op_ecowx_le_raw,
2387};
2388#else
9a64fbe4
FB		 2389static GenOpFunc *gen_op_eciwx[] = {
2390 &gen_op_eciwx_user,
111bfab3 2391 &gen_op_eciwx_le_user,
9a64fbe4 2392 &gen_op_eciwx_kernel,
111bfab3 2393 &gen_op_eciwx_le_kernel,
9a64fbe4
FB		 2394};
2395static GenOpFunc *gen_op_ecowx[] = {
2396 &gen_op_ecowx_user,
111bfab3 2397 &gen_op_ecowx_le_user,
9a64fbe4 2398 &gen_op_ecowx_kernel,
111bfab3 2399 &gen_op_ecowx_le_kernel,
9a64fbe4
FB		 2400};
2401#endif
2402
111bfab3 2403/* eciwx */
79aceca5
FB		 2404GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2405{
9a64fbe4
FB		 2406 /* Should check EAR[E] & alignment ! */
2407 if (rA(ctx->opcode) == 0) {
2408 gen_op_load_gpr_T0(rB(ctx->opcode));
2409 } else {
2410 gen_op_load_gpr_T0(rA(ctx->opcode));
2411 gen_op_load_gpr_T1(rB(ctx->opcode));
2412 gen_op_add();
2413 }
2414 op_eciwx();
2415 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2416}
2417
2418/* ecowx */
2419GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2420{
9a64fbe4
FB		 2421 /* Should check EAR[E] & alignment ! */
2422 if (rA(ctx->opcode) == 0) {
2423 gen_op_load_gpr_T0(rB(ctx->opcode));
2424 } else {
2425 gen_op_load_gpr_T0(rA(ctx->opcode));
2426 gen_op_load_gpr_T1(rB(ctx->opcode));
2427 gen_op_add();
2428 }
2429 gen_op_load_gpr_T2(rS(ctx->opcode));
2430 op_ecowx();
79aceca5
FB		 2431}
2432
2433/* End opcode list */
2434GEN_OPCODE_MARK(end);
2435
3fc6c082 2436#include "translate_init.c"
79aceca5 2437
9a64fbe4 2438/*****************************************************************************/
3fc6c082 2439/* Misc PowerPC helpers */
7fe48483
FB		 2440void cpu_dump_state(CPUState *env, FILE *f,
2441 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2442 int flags)
79aceca5 2443{
3fc6c082
FB		 2444#if defined(TARGET_PPC64) || 1
2445#define FILL ""
26a76461 2446#define REGX "%016" PRIx64
3fc6c082
FB		 2447#define RGPL 4
2448#define RFPL 4
2449#else
2450#define FILL " "
26a76461 2451#define REGX "%08" PRIx64
3fc6c082
FB		 2452#define RGPL 8
2453#define RFPL 4
2454#endif
2455
79aceca5
FB		 2456 int i;
2457
3fc6c082
FB		 2458 cpu_fprintf(f, "NIP " REGX " LR " REGX " CTR " REGX "\n",
2459 env->nip, env->lr, env->ctr);
2460 cpu_fprintf(f, "MSR " REGX FILL " XER %08x TB %08x %08x DECR %08x\n",
2461 do_load_msr(env), do_load_xer(env), cpu_ppc_load_tbu(env),
2462 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
79aceca5 2463 for (i = 0; i < 32; i++) {
3fc6c082
FB		 2464 if ((i & (RGPL - 1)) == 0)
2465 cpu_fprintf(f, "GPR%02d", i);
2466 cpu_fprintf(f, " " REGX, env->gpr[i]);
2467 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 2468 cpu_fprintf(f, "\n");
79aceca5 2469 }
3fc6c082 2470 cpu_fprintf(f, "CR ");
79aceca5 2471 for (i = 0; i < 8; i++)
7fe48483
FB		 2472 cpu_fprintf(f, "%01x", env->crf[i]);
2473 cpu_fprintf(f, " [");
79aceca5
FB		 2474 for (i = 0; i < 8; i++) {
2475 char a = '-';
79aceca5
FB		 2476 if (env->crf[i] & 0x08)
2477 a = 'L';
2478 else if (env->crf[i] & 0x04)
2479 a = 'G';
2480 else if (env->crf[i] & 0x02)
2481 a = 'E';
7fe48483 2482 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2483 }
3fc6c082
FB		 2484 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
2485 for (i = 0; i < 32; i++) {
2486 if ((i & (RFPL - 1)) == 0)
2487 cpu_fprintf(f, "FPR%02d", i);
26a76461 2488 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 2489 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 2490 cpu_fprintf(f, "\n");
79aceca5 2491 }
3fc6c082
FB		 2492 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
2493 "SDR1 " REGX "\n",
2494 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
79aceca5 2495
3fc6c082
FB		 2496#undef REGX
2497#undef RGPL
2498#undef RFPL
2499#undef FILL
79aceca5
FB		 2500}
2501
9a64fbe4 2502/*****************************************************************************/
79aceca5
FB		 2503int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2504 int search_pc)
2505{
9fddaa0c 2506 DisasContext ctx, *ctxp = &ctx;
79aceca5 2507 opc_handler_t **table, *handler;
0fa85d43 2508 target_ulong pc_start;
79aceca5
FB		 2509 uint16_t *gen_opc_end;
2510 int j, lj = -1;
79aceca5
FB		 2511
2512 pc_start = tb->pc;
2513 gen_opc_ptr = gen_opc_buf;
2514 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2515 gen_opparam_ptr = gen_opparam_buf;
c53be334 2516 nb_gen_labels = 0;
046d6672 2517 ctx.nip = pc_start;
79aceca5 2518 ctx.tb = tb;
9a64fbe4 2519 ctx.exception = EXCP_NONE;
3fc6c082 2520 ctx.spr_cb = env->spr_cb;
9a64fbe4 2521#if defined(CONFIG_USER_ONLY)
111bfab3 2522 ctx.mem_idx = msr_le;
9a64fbe4
FB		 2523#else
2524 ctx.supervisor = 1 - msr_pr;
111bfab3 2525 ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le;
9a64fbe4 2526#endif
3cc62370 2527 ctx.fpu_enabled = msr_fp;
ea4e754f 2528 ctx.singlestep_enabled = env->singlestep_enabled;
3fc6c082 2529#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 2530 /* Single step trace mode */
2531 msr_se = 1;
2532#endif
2533 /* Set env in case of segfault during code fetch */
2534 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
ea4e754f
FB		 2535 if (env->nb_breakpoints > 0) {
2536 for(j = 0; j < env->nb_breakpoints; j++) {
2537 if (env->breakpoints[j] == ctx.nip) {
2538 gen_op_update_nip(ctx.nip);
2539 gen_op_debug();
2540 break;
2541 }
2542 }
2543 }
79aceca5 2544 if (search_pc) {
79aceca5
FB		 2545 j = gen_opc_ptr - gen_opc_buf;
2546 if (lj < j) {
2547 lj++;
2548 while (lj < j)
2549 gen_opc_instr_start[lj++] = 0;
046d6672 2550 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 2551 gen_opc_instr_start[lj] = 1;
2552 }
2553 }
9fddaa0c
FB		 2554#if defined PPC_DEBUG_DISAS
2555 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 2556 fprintf(logfile, "----------------\n");
046d6672 2557 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 2558 ctx.nip, 1 - msr_pr, msr_ir);
2559 }
2560#endif
0fa85d43 2561 ctx.opcode = ldl_code(ctx.nip);
111bfab3
FB		 2562 if (msr_le) {
2563 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
2564 ((ctx.opcode & 0x00FF0000) >> 8) |
2565 ((ctx.opcode & 0x0000FF00) << 8) |
2566 ((ctx.opcode & 0x000000FF) << 24);
2567 }
9fddaa0c
FB		 2568#if defined PPC_DEBUG_DISAS
2569 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 2570 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 2571 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
111bfab3 2572 opc3(ctx.opcode), msr_le ? "little" : "big");
79aceca5
FB		 2573 }
2574#endif
046d6672 2575 ctx.nip += 4;
3fc6c082 2576 table = env->opcodes;
79aceca5
FB		 2577 handler = table[opc1(ctx.opcode)];
2578 if (is_indirect_opcode(handler)) {
2579 table = ind_table(handler);
2580 handler = table[opc2(ctx.opcode)];
2581 if (is_indirect_opcode(handler)) {
2582 table = ind_table(handler);
2583 handler = table[opc3(ctx.opcode)];
2584 }
2585 }
2586 /* Is opcode *REALLY* valid ? */
79aceca5 2587 if (handler->handler == &gen_invalid) {
4b3686fa 2588 if (loglevel > 0) {
79aceca5 2589 fprintf(logfile, "invalid/unsupported opcode: "
4b3686fa 2590 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
9a64fbe4 2591 opc1(ctx.opcode), opc2(ctx.opcode),
4b3686fa
FB		 2592 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2593 } else {
2594 printf("invalid/unsupported opcode: "
2595 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2596 opc1(ctx.opcode), opc2(ctx.opcode),
2597 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2598 }
79aceca5 2599 } else {
4b3686fa
FB		 2600 if ((ctx.opcode & handler->inval) != 0) {
2601 if (loglevel > 0) {
79aceca5 2602 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 2603 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 2604 ctx.opcode & handler->inval, opc1(ctx.opcode),
2605 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 2606 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 2607 } else {
2608 printf("invalid bits: %08x for opcode: "
046d6672 2609 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 2610 ctx.opcode & handler->inval, opc1(ctx.opcode),
2611 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 2612 ctx.opcode, ctx.nip - 4);
9a64fbe4 2613 }
4b3686fa
FB		 2614 RET_INVAL(ctxp);
2615 break;
79aceca5 2616 }
79aceca5 2617 }
4b3686fa 2618 (*(handler->handler))(&ctx);
9a64fbe4
FB		 2619 /* Check trace mode exceptions */
2620 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
2621 /* Check in single step trace mode
2622 * we need to stop except if:
2623 * - rfi, trap or syscall
2624 * - first instruction of an exception handler
2625 */
046d6672
FB		 2626 (msr_se && (ctx.nip < 0x100 ||
2627 ctx.nip > 0xF00 ||
2628 (ctx.nip & 0xFC) != 0x04) &&
2be0071f
FB		 2629 ctx.exception != EXCP_SYSCALL &&
2630 ctx.exception != EXCP_SYSCALL_USER &&
9a64fbe4 2631 ctx.exception != EXCP_TRAP)) {
9fddaa0c 2632 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 2633 }
ea4e754f
FB		 2634
2635 /* if we reach a page boundary or are single stepping, stop
2636 * generation
2637 */
2638 if (((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2639 (env->singlestep_enabled)) {
8dd4983c 2640 break;
9a64fbe4 2641 }
3fc6c082
FB		 2642#if defined (DO_SINGLE_STEP)
2643 break;
2644#endif
2645 }
9fddaa0c 2646 if (ctx.exception == EXCP_NONE) {
c1942362 2647 gen_goto_tb(&ctx, 0, ctx.nip);
9fddaa0c
FB		 2648 } else if (ctx.exception != EXCP_BRANCH) {
2649 gen_op_set_T0(0);
9a64fbe4
FB		 2650 }
2651#if 1
79aceca5
FB		 2652 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
2653 * do bad business and then qemu crashes !
2654 */
2655 gen_op_set_T0(0);
9a64fbe4 2656#endif
79aceca5
FB		 2657 /* Generate the return instruction */
2658 gen_op_exit_tb();
2659 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 2660 if (search_pc) {
2661 j = gen_opc_ptr - gen_opc_buf;
2662 lj++;
2663 while (lj <= j)
2664 gen_opc_instr_start[lj++] = 0;
79aceca5 2665 tb->size = 0;
985a19d6 2666#if 0
9a64fbe4
FB		 2667 if (loglevel > 0) {
2668 page_dump(logfile);
2669 }
985a19d6 2670#endif
9a64fbe4 2671 } else {
046d6672 2672 tb->size = ctx.nip - pc_start;
9a64fbe4 2673 }
79aceca5 2674#ifdef DEBUG_DISAS
9fddaa0c 2675 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 2676 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 2677 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 2678 }
2679 if (loglevel & CPU_LOG_TB_IN_ASM) {
0fa85d43 2680 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
0e1fd369 2681 target_disas(logfile, pc_start, ctx.nip - pc_start, msr_le);
79aceca5 2682 fprintf(logfile, "\n");
9fddaa0c
FB		 2683 }
2684 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 2685 fprintf(logfile, "OP:\n");
2686 dump_ops(gen_opc_buf, gen_opparam_buf);
2687 fprintf(logfile, "\n");
2688 }
2689#endif
79aceca5
FB		 2690 return 0;
2691}
2692
9a64fbe4 2693int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 2694{
2695 return gen_intermediate_code_internal(env, tb, 0);
2696}
2697
9a64fbe4 2698int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 2699{
2700 return gen_intermediate_code_internal(env, tb, 1);
2701}
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