[qemu.git] / hw / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "sysbus.h"
#include "sysemu.h"
#include "qemu-timer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

struct etrax_timer {
    SysBusDevice busdev;
    MemoryRegion mmio;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
};

static uint64_t
timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
    struct etrax_timer *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_get_clock_ns(vm_clock) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(struct etrax_timer *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(struct etrax_timer *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request();

    t->wd_hits++;
}

static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_write(void *opaque, target_phys_addr_t addr,
            uint64_t val64, unsigned int size)
{
    struct etrax_timer *t = opaque;
    uint32_t value = val64;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void etraxfs_timer_reset(void *opaque)
{
    struct etrax_timer *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static int etraxfs_timer_init(SysBusDevice *dev)
{
    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init(t->bh_t0);
    t->ptimer_t1 = ptimer_init(t->bh_t1);
    t->ptimer_wd = ptimer_init(t->bh_wd);

    sysbus_init_irq(dev, &t->irq);
    sysbus_init_irq(dev, &t->nmi);

    memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
    sysbus_init_mmio(dev, &t->mmio);
    qemu_register_reset(etraxfs_timer_reset, t);
    return 0;
}

static void etraxfs_timer_register(void)
{
    sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
                        etraxfs_timer_init);
}

device_init(etraxfs_timer_register)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
3b1fd90e	24	#include "sysbus.h"
5439779e	25	#include "sysemu.h"
87ecb68b	26	#include "qemu-timer.h"
83fa1010	27
bbaf29c7 EI	28	#define D(x)
bbaf29c7 EI	29
ca87d03b EI	30	#define RW_TMR0_DIV 0x00
	31	#define R_TMR0_DATA 0x04
	32	#define RW_TMR0_CTRL 0x08
	33	#define RW_TMR1_DIV 0x10
	34	#define R_TMR1_DATA 0x14
	35	#define RW_TMR1_CTRL 0x18
	36	#define R_TIME 0x38
	37	#define RW_WD_CTRL 0x40
5439779e	38	#define R_WD_STAT 0x44
ca87d03b EI	39	#define RW_INTR_MASK 0x48
	40	#define RW_ACK_INTR 0x4c
	41	#define R_INTR 0x50
	42	#define R_MASKED_INTR 0x54
83fa1010	43
3b1fd90e EI	44	struct etrax_timer {
3b1fd90e EI	45	SysBusDevice busdev;
b8e5da2c	46	MemoryRegion mmio;
3b1fd90e EI	47	qemu_irq irq;
3b1fd90e EI	48	qemu_irq nmi;
84ceea57 EI	49
	50	QEMUBH *bh_t0;
	51	QEMUBH *bh_t1;
	52	QEMUBH *bh_wd;
	53	ptimer_state *ptimer_t0;
	54	ptimer_state *ptimer_t1;
	55	ptimer_state *ptimer_wd;
84ceea57 EI	56
	57	int wd_hits;
	58
	59	/* Control registers. */
	60	uint32_t rw_tmr0_div;
	61	uint32_t r_tmr0_data;
	62	uint32_t rw_tmr0_ctrl;
	63
	64	uint32_t rw_tmr1_div;
	65	uint32_t r_tmr1_data;
	66	uint32_t rw_tmr1_ctrl;
	67
	68	uint32_t rw_wd_ctrl;
	69
	70	uint32_t rw_intr_mask;
	71	uint32_t rw_ack_intr;
	72	uint32_t r_intr;
	73	uint32_t r_masked_intr;
83fa1010 TS	74	};
83fa1010 TS	75
b8e5da2c EI	76	static uint64_t
b8e5da2c EI	77	timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
83fa1010	78	{
3b1fd90e	79	struct etrax_timer *t = opaque;
84ceea57 EI	80	uint32_t r = 0;
	81
	82	switch (addr) {
	83	case R_TMR0_DATA:
	84	r = ptimer_get_count(t->ptimer_t0);
	85	break;
	86	case R_TMR1_DATA:
	87	r = ptimer_get_count(t->ptimer_t1);
	88	break;
	89	case R_TIME:
74475455	90	r = qemu_get_clock_ns(vm_clock) / 10;
84ceea57 EI	91	break;
	92	case RW_INTR_MASK:
	93	r = t->rw_intr_mask;
	94	break;
	95	case R_MASKED_INTR:
	96	r = t->r_intr & t->rw_intr_mask;
	97	break;
	98	default:
	99	D(printf ("%s %x\n", __func__, addr));
	100	break;
	101	}
	102	return r;
83fa1010 TS	103	}
83fa1010 TS	104
3b1fd90e	105	static void update_ctrl(struct etrax_timer *t, int tnum)
83fa1010	106	{
84ceea57 EI	107	unsigned int op;
	108	unsigned int freq;
	109	unsigned int freq_hz;
	110	unsigned int div;
	111	uint32_t ctrl;
	112
	113	ptimer_state *timer;
	114
	115	if (tnum == 0) {
	116	ctrl = t->rw_tmr0_ctrl;
	117	div = t->rw_tmr0_div;
	118	timer = t->ptimer_t0;
	119	} else {
	120	ctrl = t->rw_tmr1_ctrl;
	121	div = t->rw_tmr1_div;
	122	timer = t->ptimer_t1;
	123	}
	124
	125
	126	op = ctrl & 3;
	127	freq = ctrl >> 2;
	128	freq_hz = 32000000;
	129
	130	switch (freq)
	131	{
	132	case 0:
	133	case 1:
	134	D(printf ("extern or disabled timer clock?\n"));
	135	break;
	136	case 4: freq_hz = 29493000; break;
	137	case 5: freq_hz = 32000000; break;
	138	case 6: freq_hz = 32768000; break;
	139	case 7: freq_hz = 100000000; break;
	140	default:
	141	abort();
	142	break;
	143	}
	144
	145	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	146	ptimer_set_freq(timer, freq_hz);
	147	ptimer_set_limit(timer, div, 0);
	148
	149	switch (op)
	150	{
	151	case 0:
	152	/* Load. */
	153	ptimer_set_limit(timer, div, 1);
	154	break;
	155	case 1:
	156	/* Hold. */
	157	ptimer_stop(timer);
	158	break;
	159	case 2:
	160	/* Run. */
	161	ptimer_run(timer, 0);
	162	break;
	163	default:
	164	abort();
	165	break;
	166	}
83fa1010 TS	167	}
83fa1010 TS	168
3b1fd90e	169	static void timer_update_irq(struct etrax_timer *t)
83fa1010	170	{
84ceea57 EI	171	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	172	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	173
84ceea57	174	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	175	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	176	}
83fa1010 TS	177
5439779e	178	static void timer0_hit(void *opaque)
60237223	179	{
3b1fd90e	180	struct etrax_timer *t = opaque;
84ceea57 EI	181	t->r_intr \|= 1;
84ceea57 EI	182	timer_update_irq(t);
60237223 EI	183	}
60237223 EI	184
5439779e EI	185	static void timer1_hit(void *opaque)
5439779e EI	186	{
3b1fd90e	187	struct etrax_timer *t = opaque;
84ceea57 EI	188	t->r_intr \|= 2;
84ceea57 EI	189	timer_update_irq(t);
5439779e EI	190	}
	191
	192	static void watchdog_hit(void *opaque)
	193	{
3b1fd90e	194	struct etrax_timer *t = opaque;
84ceea57 EI	195	if (t->wd_hits == 0) {
	196	/* real hw gives a single tick before reseting but we are
	197	a bit friendlier to compensate for our slower execution. */
	198	ptimer_set_count(t->ptimer_wd, 10);
	199	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	200	qemu_irq_raise(t->nmi);
84ceea57 EI	201	}
	202	else
	203	qemu_system_reset_request();
	204
	205	t->wd_hits++;
5439779e EI	206	}
5439779e EI	207
3b1fd90e	208	static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
5439779e	209	{
84ceea57 EI	210	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	211	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	212	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	213	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	214	unsigned int new_cmd = (value >> 8) & 1;
5439779e	215
84ceea57 EI	216	/* If the watchdog is enabled, they written key must match the
	217	complement of the previous. */
	218	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	219
84ceea57 EI	220	if (wd_en && wd_key != new_key)
84ceea57 EI	221	return;
5439779e	222
84ceea57 EI	223	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	224	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	225
84ceea57	226	if (t->wd_hits)
3b1fd90e	227	qemu_irq_lower(t->nmi);
5ef98b47	228
84ceea57	229	t->wd_hits = 0;
5ef98b47	230
84ceea57 EI	231	ptimer_set_freq(t->ptimer_wd, 760);
	232	if (wd_cnt == 0)
	233	wd_cnt = 256;
	234	ptimer_set_count(t->ptimer_wd, wd_cnt);
	235	if (new_cmd)
	236	ptimer_run(t->ptimer_wd, 1);
	237	else
	238	ptimer_stop(t->ptimer_wd);
5439779e	239
84ceea57	240	t->rw_wd_ctrl = value;
5439779e EI	241	}
5439779e EI	242
83fa1010	243	static void
b8e5da2c EI	244	timer_write(void *opaque, target_phys_addr_t addr,
b8e5da2c EI	245	uint64_t val64, unsigned int size)
83fa1010	246	{
3b1fd90e	247	struct etrax_timer *t = opaque;
b8e5da2c	248	uint32_t value = val64;
84ceea57 EI	249
	250	switch (addr)
	251	{
	252	case RW_TMR0_DIV:
	253	t->rw_tmr0_div = value;
	254	break;
	255	case RW_TMR0_CTRL:
	256	D(printf ("RW_TMR0_CTRL=%x\n", value));
	257	t->rw_tmr0_ctrl = value;
	258	update_ctrl(t, 0);
	259	break;
	260	case RW_TMR1_DIV:
	261	t->rw_tmr1_div = value;
	262	break;
	263	case RW_TMR1_CTRL:
	264	D(printf ("RW_TMR1_CTRL=%x\n", value));
	265	t->rw_tmr1_ctrl = value;
	266	update_ctrl(t, 1);
	267	break;
	268	case RW_INTR_MASK:
	269	D(printf ("RW_INTR_MASK=%x\n", value));
	270	t->rw_intr_mask = value;
	271	timer_update_irq(t);
	272	break;
	273	case RW_WD_CTRL:
	274	timer_watchdog_update(t, value);
	275	break;
	276	case RW_ACK_INTR:
	277	t->rw_ack_intr = value;
	278	timer_update_irq(t);
	279	t->rw_ack_intr = 0;
	280	break;
	281	default:
	282	printf ("%s " TARGET_FMT_plx " %x\n",
	283	__func__, addr, value);
	284	break;
	285	}
83fa1010 TS	286	}
83fa1010 TS	287
b8e5da2c EI	288	static const MemoryRegionOps timer_ops = {
	289	.read = timer_read,
	290	.write = timer_write,
	291	.endianness = DEVICE_LITTLE_ENDIAN,
	292	.valid = {
	293	.min_access_size = 4,
	294	.max_access_size = 4
	295	}
83fa1010 TS	296	};
83fa1010 TS	297
5439779e EI	298	static void etraxfs_timer_reset(void *opaque)
5439779e EI	299	{
3b1fd90e	300	struct etrax_timer *t = opaque;
84ceea57 EI	301
	302	ptimer_stop(t->ptimer_t0);
	303	ptimer_stop(t->ptimer_t1);
	304	ptimer_stop(t->ptimer_wd);
	305	t->rw_wd_ctrl = 0;
	306	t->r_intr = 0;
	307	t->rw_intr_mask = 0;
3b1fd90e	308	qemu_irq_lower(t->irq);
5439779e EI	309	}
5439779e EI	310
81a322d4	311	static int etraxfs_timer_init(SysBusDevice *dev)
83fa1010	312	{
3b1fd90e	313	struct etrax_timer t = FROM_SYSBUS(typeof (t), dev);
83fa1010	314
84ceea57 EI	315	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	316	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	317	t->bh_wd = qemu_bh_new(watchdog_hit, t);
	318	t->ptimer_t0 = ptimer_init(t->bh_t0);
	319	t->ptimer_t1 = ptimer_init(t->bh_t1);
	320	t->ptimer_wd = ptimer_init(t->bh_wd);
3b1fd90e EI	321
	322	sysbus_init_irq(dev, &t->irq);
	323	sysbus_init_irq(dev, &t->nmi);
83fa1010	324
b8e5da2c	325	memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
750ecd44	326	sysbus_init_mmio(dev, &t->mmio);
a08d4367	327	qemu_register_reset(etraxfs_timer_reset, t);
81a322d4	328	return 0;
83fa1010	329	}
3b1fd90e EI	330
	331	static void etraxfs_timer_register(void)
	332	{
	333	sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
	334	etraxfs_timer_init);
	335	}
	336
	337	device_init(etraxfs_timer_register)