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linux-user: Use the 5KEf processor for 64-bit emulation
[qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
2b41f10e 31#include "cpu.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
fc9c5412
JS		 40const char *filename;
41const char *argv0;
42int gdbstub_port;
43envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698 45unsigned long mmap_min_addr;
14f24e14 46#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 47unsigned long guest_base;
48int have_guest_base;
288e65b9
AG		 49#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
50/*
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
53 *
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
56 */
314992b1
AG		 57# ifdef TARGET_MIPS
58/* MIPS only supports 31 bits of virtual address space for user space */
59unsigned long reserved_va = 0x77000000;
60# else
288e65b9 61unsigned long reserved_va = 0xf7000000;
314992b1 62# endif
288e65b9 63#else
68a1c816 64unsigned long reserved_va;
379f6698 65#endif
288e65b9 66#endif
1b530a6d 67
fc9c5412
JS		 68static void usage(void);
69
7ee2822c 70static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 71const char *qemu_uname_release;
586314f2 72
9de5e440
FB		 73/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
703e0e89 76unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 77
78void gemu_log(const char *fmt, ...)
79{
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85}
86
8fcd3692 87#if defined(TARGET_I386)
05390248 88int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 89{
90 return -1;
91}
8fcd3692 92#endif
92ccca6a 93
d5975363
PB		 94/***********************************************************/
95/* Helper routines for implementing atomic operations. */
96
97/* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
c2764719 101static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 102static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
103static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
104static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
105static int pending_cpus;
106
107/* Make sure everything is in a consistent state for calling fork(). */
108void fork_start(void)
109{
5e5f07e0 110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 111 pthread_mutex_lock(&exclusive_lock);
d032d1b4 112 mmap_fork_start();
d5975363
PB		 113}
114
115void fork_end(int child)
116{
d032d1b4 117 mmap_fork_end(child);
d5975363 118 if (child) {
bdc44640 119 CPUState *cpu, *next_cpu;
d5975363
PB		 120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
bdc44640
AF		 122 CPU_FOREACH_SAFE(cpu, next_cpu) {
123 if (cpu != thread_cpu) {
124 QTAILQ_REMOVE(&cpus, thread_cpu, node);
125 }
126 }
d5975363
PB		 127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 129 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 133 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 137 }
d5975363
PB		 138}
139
140/* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142static inline void exclusive_idle(void)
143{
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147}
148
149/* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151static inline void start_exclusive(void)
152{
0315c31c
AF		 153 CPUState *other_cpu;
154
d5975363
PB		 155 pthread_mutex_lock(&exclusive_lock);
156 exclusive_idle();
157
158 pending_cpus = 1;
159 /* Make all other cpus stop executing. */
bdc44640 160 CPU_FOREACH(other_cpu) {
0315c31c 161 if (other_cpu->running) {
d5975363 162 pending_cpus++;
60a3e17a 163 cpu_exit(other_cpu);
d5975363
PB		 164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169}
170
171/* Finish an exclusive operation. */
172static inline void end_exclusive(void)
173{
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177}
178
179/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 180static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 181{
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
0315c31c 184 cpu->running = true;
d5975363
PB		 185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 189static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
0315c31c 192 cpu->running = false;
d5975363
PB		 193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201}
c2764719
PB		 202
203void cpu_list_lock(void)
204{
205 pthread_mutex_lock(&cpu_list_mutex);
206}
207
208void cpu_list_unlock(void)
209{
210 pthread_mutex_unlock(&cpu_list_mutex);
211}
d5975363
PB		 212
213
a541f297
FB		 214#ifdef TARGET_I386
215/***********************************************************/
216/* CPUX86 core interface */
217
05390248 218void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 219{
220}
221
28ab0e2e
FB		 222uint64_t cpu_get_tsc(CPUX86State *env)
223{
224 return cpu_get_real_ticks();
225}
226
5fafdf24 227static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 228 int flags)
6dbad63e 229{
f4beb510 230 unsigned int e1, e2;
53a5960a 231 uint32_t *p;
6dbad63e
FB		 232 e1 = (addr << 16) | (limit & 0xffff);
233 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 234 e2 |= flags;
53a5960a 235 p = ptr;
d538e8f5 236 p[0] = tswap32(e1);
237 p[1] = tswap32(e2);
f4beb510
FB		 238}
239
e441570f 240static uint64_t *idt_table;
eb38c52c 241#ifdef TARGET_X86_64
d2fd1af7
FB		 242static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
243 uint64_t addr, unsigned int sel)
f4beb510 244{
4dbc422b 245 uint32_t *p, e1, e2;
f4beb510
FB		 246 e1 = (addr & 0xffff) | (sel << 16);
247 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 248 p = ptr;
4dbc422b
FB		 249 p[0] = tswap32(e1);
250 p[1] = tswap32(e2);
251 p[2] = tswap32(addr >> 32);
252 p[3] = 0;
6dbad63e 253}
d2fd1af7
FB		 254/* only dpl matters as we do only user space emulation */
255static void set_idt(int n, unsigned int dpl)
256{
257 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
258}
259#else
d2fd1af7
FB		 260static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
261 uint32_t addr, unsigned int sel)
262{
4dbc422b 263 uint32_t *p, e1, e2;
d2fd1af7
FB		 264 e1 = (addr & 0xffff) | (sel << 16);
265 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
266 p = ptr;
4dbc422b
FB		 267 p[0] = tswap32(e1);
268 p[1] = tswap32(e2);
d2fd1af7
FB		 269}
270
f4beb510
FB		 271/* only dpl matters as we do only user space emulation */
272static void set_idt(int n, unsigned int dpl)
273{
274 set_gate(idt_table + n, 0, dpl, 0, 0);
275}
d2fd1af7 276#endif
31e31b8a 277
89e957e7 278void cpu_loop(CPUX86State *env)
1b6b029e 279{
db6b81d4 280 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 281 int trapnr;
992f48a0 282 abi_ulong pc;
c227f099 283 target_siginfo_t info;
851e67a1 284
1b6b029e 285 for(;;) {
bc8a22cc 286 trapnr = cpu_x86_exec(env);
bc8a22cc 287 switch(trapnr) {
f4beb510 288 case 0x80:
d2fd1af7 289 /* linux syscall from int $0x80 */
5fafdf24
TS		 290 env->regs[R_EAX] = do_syscall(env,
291 env->regs[R_EAX],
f4beb510
FB		 292 env->regs[R_EBX],
293 env->regs[R_ECX],
294 env->regs[R_EDX],
295 env->regs[R_ESI],
296 env->regs[R_EDI],
5945cfcb
PM		 297 env->regs[R_EBP],
298 0, 0);
f4beb510 299 break;
d2fd1af7
FB		 300#ifndef TARGET_ABI32
301 case EXCP_SYSCALL:
5ba18547 302 /* linux syscall from syscall instruction */
d2fd1af7
FB		 303 env->regs[R_EAX] = do_syscall(env,
304 env->regs[R_EAX],
305 env->regs[R_EDI],
306 env->regs[R_ESI],
307 env->regs[R_EDX],
308 env->regs[10],
309 env->regs[8],
5945cfcb
PM		 310 env->regs[9],
311 0, 0);
d2fd1af7
FB		 312 break;
313#endif
f4beb510
FB		 314 case EXCP0B_NOSEG:
315 case EXCP0C_STACK:
316 info.si_signo = SIGBUS;
317 info.si_errno = 0;
318 info.si_code = TARGET_SI_KERNEL;
319 info._sifields._sigfault._addr = 0;
624f7979 320 queue_signal(env, info.si_signo, &info);
f4beb510 321 break;
1b6b029e 322 case EXCP0D_GPF:
d2fd1af7 323 /* XXX: potential problem if ABI32 */
84409ddb 324#ifndef TARGET_X86_64
851e67a1 325 if (env->eflags & VM_MASK) {
89e957e7 326 handle_vm86_fault(env);
84409ddb
JM		 327 } else
328#endif
329 {
f4beb510
FB		 330 info.si_signo = SIGSEGV;
331 info.si_errno = 0;
332 info.si_code = TARGET_SI_KERNEL;
333 info._sifields._sigfault._addr = 0;
624f7979 334 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 335 }
336 break;
b689bc57
FB		 337 case EXCP0E_PAGE:
338 info.si_signo = SIGSEGV;
339 info.si_errno = 0;
340 if (!(env->error_code & 1))
341 info.si_code = TARGET_SEGV_MAPERR;
342 else
343 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 344 info._sifields._sigfault._addr = env->cr[2];
624f7979 345 queue_signal(env, info.si_signo, &info);
b689bc57 346 break;
9de5e440 347 case EXCP00_DIVZ:
84409ddb 348#ifndef TARGET_X86_64
bc8a22cc 349 if (env->eflags & VM_MASK) {
447db213 350 handle_vm86_trap(env, trapnr);
84409ddb
JM		 351 } else
352#endif
353 {
bc8a22cc
FB		 354 /* division by zero */
355 info.si_signo = SIGFPE;
356 info.si_errno = 0;
357 info.si_code = TARGET_FPE_INTDIV;
358 info._sifields._sigfault._addr = env->eip;
624f7979 359 queue_signal(env, info.si_signo, &info);
bc8a22cc 360 }
9de5e440 361 break;
01df040b 362 case EXCP01_DB:
447db213 363 case EXCP03_INT3:
84409ddb 364#ifndef TARGET_X86_64
447db213
FB		 365 if (env->eflags & VM_MASK) {
366 handle_vm86_trap(env, trapnr);
84409ddb
JM		 367 } else
368#endif
369 {
447db213
FB		 370 info.si_signo = SIGTRAP;
371 info.si_errno = 0;
01df040b 372 if (trapnr == EXCP01_DB) {
447db213
FB		 373 info.si_code = TARGET_TRAP_BRKPT;
374 info._sifields._sigfault._addr = env->eip;
375 } else {
376 info.si_code = TARGET_SI_KERNEL;
377 info._sifields._sigfault._addr = 0;
378 }
624f7979 379 queue_signal(env, info.si_signo, &info);
447db213
FB		 380 }
381 break;
9de5e440
FB		 382 case EXCP04_INTO:
383 case EXCP05_BOUND:
84409ddb 384#ifndef TARGET_X86_64
bc8a22cc 385 if (env->eflags & VM_MASK) {
447db213 386 handle_vm86_trap(env, trapnr);
84409ddb
JM		 387 } else
388#endif
389 {
bc8a22cc
FB		 390 info.si_signo = SIGSEGV;
391 info.si_errno = 0;
b689bc57 392 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 393 info._sifields._sigfault._addr = 0;
624f7979 394 queue_signal(env, info.si_signo, &info);
bc8a22cc 395 }
9de5e440
FB		 396 break;
397 case EXCP06_ILLOP:
398 info.si_signo = SIGILL;
399 info.si_errno = 0;
400 info.si_code = TARGET_ILL_ILLOPN;
401 info._sifields._sigfault._addr = env->eip;
624f7979 402 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 403 break;
404 case EXCP_INTERRUPT:
405 /* just indicate that signals should be handled asap */
406 break;
1fddef4b
FB		 407 case EXCP_DEBUG:
408 {
409 int sig;
410
db6b81d4 411 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 412 if (sig)
413 {
414 info.si_signo = sig;
415 info.si_errno = 0;
416 info.si_code = TARGET_TRAP_BRKPT;
624f7979 417 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 418 }
419 }
420 break;
1b6b029e 421 default:
970a87a6 422 pc = env->segs[R_CS].base + env->eip;
5fafdf24 423 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 424 (long)pc, trapnr);
1b6b029e
FB		 425 abort();
426 }
66fb9763 427 process_pending_signals(env);
1b6b029e
FB		 428 }
429}
b346ff46
FB		 430#endif
431
432#ifdef TARGET_ARM
433
d8fd2954
PB		 434#define get_user_code_u32(x, gaddr, doswap) \
435 ({ abi_long __r = get_user_u32((x), (gaddr)); \
436 if (!__r && (doswap)) { \
437 (x) = bswap32(x); \
438 } \
439 __r; \
440 })
441
442#define get_user_code_u16(x, gaddr, doswap) \
443 ({ abi_long __r = get_user_u16((x), (gaddr)); \
444 if (!__r && (doswap)) { \
445 (x) = bswap16(x); \
446 } \
447 __r; \
448 })
449
1861c454
PM		 450#ifdef TARGET_ABI32
451/* Commpage handling -- there is no commpage for AArch64 */
452
97cc7560
DDAG		 453/*
454 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
455 * Input:
456 * r0 = pointer to oldval
457 * r1 = pointer to newval
458 * r2 = pointer to target value
459 *
460 * Output:
461 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
462 * C set if *ptr was changed, clear if no exchange happened
463 *
464 * Note segv's in kernel helpers are a bit tricky, we can set the
465 * data address sensibly but the PC address is just the entry point.
466 */
467static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
468{
469 uint64_t oldval, newval, val;
470 uint32_t addr, cpsr;
471 target_siginfo_t info;
472
473 /* Based on the 32 bit code in do_kernel_trap */
474
475 /* XXX: This only works between threads, not between processes.
476 It's probably possible to implement this with native host
477 operations. However things like ldrex/strex are much harder so
478 there's not much point trying. */
479 start_exclusive();
480 cpsr = cpsr_read(env);
481 addr = env->regs[2];
482
483 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 484 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 485 goto segv;
486 };
487
488 if (get_user_u64(newval, env->regs[1])) {
abf1172f 489 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 490 goto segv;
491 };
492
493 if (get_user_u64(val, addr)) {
abf1172f 494 env->exception.vaddress = addr;
97cc7560
DDAG		 495 goto segv;
496 }
497
498 if (val == oldval) {
499 val = newval;
500
501 if (put_user_u64(val, addr)) {
abf1172f 502 env->exception.vaddress = addr;
97cc7560
DDAG		 503 goto segv;
504 };
505
506 env->regs[0] = 0;
507 cpsr |= CPSR_C;
508 } else {
509 env->regs[0] = -1;
510 cpsr &= ~CPSR_C;
511 }
512 cpsr_write(env, cpsr, CPSR_C);
513 end_exclusive();
514 return;
515
516segv:
517 end_exclusive();
518 /* We get the PC of the entry address - which is as good as anything,
519 on a real kernel what you get depends on which mode it uses. */
520 info.si_signo = SIGSEGV;
521 info.si_errno = 0;
522 /* XXX: check env->error_code */
523 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 524 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560
DDAG		 525 queue_signal(env, info.si_signo, &info);
526
527 end_exclusive();
528}
529
fbb4a2e3
PB		 530/* Handle a jump to the kernel code page. */
531static int
532do_kernel_trap(CPUARMState *env)
533{
534 uint32_t addr;
535 uint32_t cpsr;
536 uint32_t val;
537
538 switch (env->regs[15]) {
539 case 0xffff0fa0: /* __kernel_memory_barrier */
540 /* ??? No-op. Will need to do better for SMP. */
541 break;
542 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 543 /* XXX: This only works between threads, not between processes.
544 It's probably possible to implement this with native host
545 operations. However things like ldrex/strex are much harder so
546 there's not much point trying. */
547 start_exclusive();
fbb4a2e3
PB		 548 cpsr = cpsr_read(env);
549 addr = env->regs[2];
550 /* FIXME: This should SEGV if the access fails. */
551 if (get_user_u32(val, addr))
552 val = ~env->regs[0];
553 if (val == env->regs[0]) {
554 val = env->regs[1];
555 /* FIXME: Check for segfaults. */
556 put_user_u32(val, addr);
557 env->regs[0] = 0;
558 cpsr |= CPSR_C;
559 } else {
560 env->regs[0] = -1;
561 cpsr &= ~CPSR_C;
562 }
563 cpsr_write(env, cpsr, CPSR_C);
d5975363 564 end_exclusive();
fbb4a2e3
PB		 565 break;
566 case 0xffff0fe0: /* __kernel_get_tls */
54bf36ed 567 env->regs[0] = env->cp15.tpidrro_el[0];
fbb4a2e3 568 break;
97cc7560
DDAG		 569 case 0xffff0f60: /* __kernel_cmpxchg64 */
570 arm_kernel_cmpxchg64_helper(env);
571 break;
572
fbb4a2e3
PB		 573 default:
574 return 1;
575 }
576 /* Jump back to the caller. */
577 addr = env->regs[14];
578 if (addr & 1) {
579 env->thumb = 1;
580 addr &= ~1;
581 }
582 env->regs[15] = addr;
583
584 return 0;
585}
586
fa2ef212 587/* Store exclusive handling for AArch32 */
426f5abc
PB		 588static int do_strex(CPUARMState *env)
589{
03d05e2d 590 uint64_t val;
426f5abc
PB		 591 int size;
592 int rc = 1;
593 int segv = 0;
594 uint32_t addr;
595 start_exclusive();
03d05e2d 596 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 597 goto fail;
598 }
03d05e2d
PM		 599 /* We know we're always AArch32 so the address is in uint32_t range
600 * unless it was the -1 exclusive-monitor-lost value (which won't
601 * match exclusive_test above).
602 */
603 assert(extract64(env->exclusive_addr, 32, 32) == 0);
604 addr = env->exclusive_addr;
426f5abc
PB		 605 size = env->exclusive_info & 0xf;
606 switch (size) {
607 case 0:
608 segv = get_user_u8(val, addr);
609 break;
610 case 1:
611 segv = get_user_u16(val, addr);
612 break;
613 case 2:
614 case 3:
615 segv = get_user_u32(val, addr);
616 break;
f7001a3b
AJ		 617 default:
618 abort();
426f5abc
PB		 619 }
620 if (segv) {
abf1172f 621 env->exception.vaddress = addr;
426f5abc
PB		 622 goto done;
623 }
426f5abc 624 if (size == 3) {
03d05e2d
PM		 625 uint32_t valhi;
626 segv = get_user_u32(valhi, addr + 4);
426f5abc 627 if (segv) {
abf1172f 628 env->exception.vaddress = addr + 4;
426f5abc
PB		 629 goto done;
630 }
03d05e2d 631 val = deposit64(val, 32, 32, valhi);
426f5abc 632 }
03d05e2d
PM		 633 if (val != env->exclusive_val) {
634 goto fail;
635 }
636
426f5abc
PB		 637 val = env->regs[(env->exclusive_info >> 8) & 0xf];
638 switch (size) {
639 case 0:
640 segv = put_user_u8(val, addr);
641 break;
642 case 1:
643 segv = put_user_u16(val, addr);
644 break;
645 case 2:
646 case 3:
647 segv = put_user_u32(val, addr);
648 break;
649 }
650 if (segv) {
abf1172f 651 env->exception.vaddress = addr;
426f5abc
PB		 652 goto done;
653 }
654 if (size == 3) {
655 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 656 segv = put_user_u32(val, addr + 4);
426f5abc 657 if (segv) {
abf1172f 658 env->exception.vaddress = addr + 4;
426f5abc
PB		 659 goto done;
660 }
661 }
662 rc = 0;
663fail:
725b8a69 664 env->regs[15] += 4;
426f5abc
PB		 665 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
666done:
667 end_exclusive();
668 return segv;
669}
670
b346ff46
FB		 671void cpu_loop(CPUARMState *env)
672{
0315c31c 673 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 674 int trapnr;
675 unsigned int n, insn;
c227f099 676 target_siginfo_t info;
b5ff1b31 677 uint32_t addr;
3b46e624 678
b346ff46 679 for(;;) {
0315c31c 680 cpu_exec_start(cs);
b346ff46 681 trapnr = cpu_arm_exec(env);
0315c31c 682 cpu_exec_end(cs);
b346ff46
FB		 683 switch(trapnr) {
684 case EXCP_UDEF:
c6981055 685 {
0429a971 686 TaskState *ts = cs->opaque;
c6981055 687 uint32_t opcode;
6d9a42be 688 int rc;
c6981055
FB		 689
690 /* we handle the FPU emulation here, as Linux */
691 /* we get the opcode */
2f619698 692 /* FIXME - what to do if get_user() fails? */
d8fd2954 693 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 694
6d9a42be
AJ		 695 rc = EmulateAll(opcode, &ts->fpa, env);
696 if (rc == 0) { /* illegal instruction */
c6981055
FB		 697 info.si_signo = SIGILL;
698 info.si_errno = 0;
699 info.si_code = TARGET_ILL_ILLOPN;
700 info._sifields._sigfault._addr = env->regs[15];
624f7979 701 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 702 } else if (rc < 0) { /* FP exception */
703 int arm_fpe=0;
704
705 /* translate softfloat flags to FPSR flags */
706 if (-rc & float_flag_invalid)
707 arm_fpe |= BIT_IOC;
708 if (-rc & float_flag_divbyzero)
709 arm_fpe |= BIT_DZC;
710 if (-rc & float_flag_overflow)
711 arm_fpe |= BIT_OFC;
712 if (-rc & float_flag_underflow)
713 arm_fpe |= BIT_UFC;
714 if (-rc & float_flag_inexact)
715 arm_fpe |= BIT_IXC;
716
717 FPSR fpsr = ts->fpa.fpsr;
718 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
719
720 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
721 info.si_signo = SIGFPE;
722 info.si_errno = 0;
723
724 /* ordered by priority, least first */
725 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
726 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
727 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
728 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
729 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
730
731 info._sifields._sigfault._addr = env->regs[15];
624f7979 732 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 733 } else {
734 env->regs[15] += 4;
735 }
736
737 /* accumulate unenabled exceptions */
738 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
739 fpsr |= BIT_IXC;
740 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
741 fpsr |= BIT_UFC;
742 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
743 fpsr |= BIT_OFC;
744 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
745 fpsr |= BIT_DZC;
746 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
747 fpsr |= BIT_IOC;
748 ts->fpa.fpsr=fpsr;
749 } else { /* everything OK */
c6981055
FB		 750 /* increment PC */
751 env->regs[15] += 4;
752 }
753 }
b346ff46
FB		 754 break;
755 case EXCP_SWI:
06c949e6 756 case EXCP_BKPT:
b346ff46 757 {
ce4defa0 758 env->eabi = 1;
b346ff46 759 /* system call */
06c949e6
PB		 760 if (trapnr == EXCP_BKPT) {
761 if (env->thumb) {
2f619698 762 /* FIXME - what to do if get_user() fails? */
d8fd2954 763 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 764 n = insn & 0xff;
765 env->regs[15] += 2;
766 } else {
2f619698 767 /* FIXME - what to do if get_user() fails? */
d8fd2954 768 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 769 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
770 env->regs[15] += 4;
771 }
192c7bd9 772 } else {
06c949e6 773 if (env->thumb) {
2f619698 774 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 775 get_user_code_u16(insn, env->regs[15] - 2,
776 env->bswap_code);
06c949e6
PB		 777 n = insn & 0xff;
778 } else {
2f619698 779 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 780 get_user_code_u32(insn, env->regs[15] - 4,
781 env->bswap_code);
06c949e6
PB		 782 n = insn & 0xffffff;
783 }
192c7bd9
FB		 784 }
785
6f1f31c0 786 if (n == ARM_NR_cacheflush) {
dcfd14b3 787 /* nop */
a4f81979
FB		 788 } else if (n == ARM_NR_semihosting
789 || n == ARM_NR_thumb_semihosting) {
790 env->regs[0] = do_arm_semihosting (env);
3a1363ac 791 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 792 /* linux syscall */
ce4defa0 793 if (env->thumb || n == 0) {
192c7bd9
FB		 794 n = env->regs[7];
795 } else {
796 n -= ARM_SYSCALL_BASE;
ce4defa0 797 env->eabi = 0;
192c7bd9 798 }
fbb4a2e3
PB		 799 if ( n > ARM_NR_BASE) {
800 switch (n) {
801 case ARM_NR_cacheflush:
dcfd14b3 802 /* nop */
fbb4a2e3
PB		 803 break;
804 case ARM_NR_set_tls:
805 cpu_set_tls(env, env->regs[0]);
806 env->regs[0] = 0;
807 break;
d5355087
HL		 808 case ARM_NR_breakpoint:
809 env->regs[15] -= env->thumb ? 2 : 4;
810 goto excp_debug;
fbb4a2e3
PB		 811 default:
812 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
813 n);
814 env->regs[0] = -TARGET_ENOSYS;
815 break;
816 }
817 } else {
818 env->regs[0] = do_syscall(env,
819 n,
820 env->regs[0],
821 env->regs[1],
822 env->regs[2],
823 env->regs[3],
824 env->regs[4],
5945cfcb
PM		 825 env->regs[5],
826 0, 0);
fbb4a2e3 827 }
b346ff46
FB		 828 } else {
829 goto error;
830 }
831 }
832 break;
43fff238
FB		 833 case EXCP_INTERRUPT:
834 /* just indicate that signals should be handled asap */
835 break;
abf1172f
PM		 836 case EXCP_STREX:
837 if (!do_strex(env)) {
838 break;
839 }
840 /* fall through for segv */
68016c62
FB		 841 case EXCP_PREFETCH_ABORT:
842 case EXCP_DATA_ABORT:
abf1172f 843 addr = env->exception.vaddress;
68016c62
FB		 844 {
845 info.si_signo = SIGSEGV;
846 info.si_errno = 0;
847 /* XXX: check env->error_code */
848 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 849 info._sifields._sigfault._addr = addr;
624f7979 850 queue_signal(env, info.si_signo, &info);
68016c62
FB		 851 }
852 break;
1fddef4b 853 case EXCP_DEBUG:
d5355087 854 excp_debug:
1fddef4b
FB		 855 {
856 int sig;
857
db6b81d4 858 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 859 if (sig)
860 {
861 info.si_signo = sig;
862 info.si_errno = 0;
863 info.si_code = TARGET_TRAP_BRKPT;
624f7979 864 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 865 }
866 }
867 break;
fbb4a2e3
PB		 868 case EXCP_KERNEL_TRAP:
869 if (do_kernel_trap(env))
870 goto error;
871 break;
b346ff46
FB		 872 default:
873 error:
5fafdf24 874 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 875 trapnr);
878096ee 876 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 877 abort();
878 }
879 process_pending_signals(env);
880 }
881}
882
1861c454
PM		 883#else
884
fa2ef212
MM		 885/*
886 * Handle AArch64 store-release exclusive
887 *
888 * rs = gets the status result of store exclusive
889 * rt = is the register that is stored
890 * rt2 = is the second register store (in STP)
891 *
892 */
893static int do_strex_a64(CPUARMState *env)
894{
895 uint64_t val;
896 int size;
897 bool is_pair;
898 int rc = 1;
899 int segv = 0;
900 uint64_t addr;
901 int rs, rt, rt2;
902
903 start_exclusive();
904 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
905 size = extract32(env->exclusive_info, 0, 2);
906 is_pair = extract32(env->exclusive_info, 2, 1);
907 rs = extract32(env->exclusive_info, 4, 5);
908 rt = extract32(env->exclusive_info, 9, 5);
909 rt2 = extract32(env->exclusive_info, 14, 5);
910
911 addr = env->exclusive_addr;
912
913 if (addr != env->exclusive_test) {
914 goto finish;
915 }
916
917 switch (size) {
918 case 0:
919 segv = get_user_u8(val, addr);
920 break;
921 case 1:
922 segv = get_user_u16(val, addr);
923 break;
924 case 2:
925 segv = get_user_u32(val, addr);
926 break;
927 case 3:
928 segv = get_user_u64(val, addr);
929 break;
930 default:
931 abort();
932 }
933 if (segv) {
abf1172f 934 env->exception.vaddress = addr;
fa2ef212
MM		 935 goto error;
936 }
937 if (val != env->exclusive_val) {
938 goto finish;
939 }
940 if (is_pair) {
941 if (size == 2) {
942 segv = get_user_u32(val, addr + 4);
943 } else {
944 segv = get_user_u64(val, addr + 8);
945 }
946 if (segv) {
abf1172f 947 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 948 goto error;
949 }
950 if (val != env->exclusive_high) {
951 goto finish;
952 }
953 }
2ea5a2ca
JG		 954 /* handle the zero register */
955 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 956 switch (size) {
957 case 0:
958 segv = put_user_u8(val, addr);
959 break;
960 case 1:
961 segv = put_user_u16(val, addr);
962 break;
963 case 2:
964 segv = put_user_u32(val, addr);
965 break;
966 case 3:
967 segv = put_user_u64(val, addr);
968 break;
969 }
970 if (segv) {
971 goto error;
972 }
973 if (is_pair) {
2ea5a2ca
JG		 974 /* handle the zero register */
975 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 976 if (size == 2) {
977 segv = put_user_u32(val, addr + 4);
978 } else {
979 segv = put_user_u64(val, addr + 8);
980 }
981 if (segv) {
abf1172f 982 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 983 goto error;
984 }
985 }
986 rc = 0;
987finish:
988 env->pc += 4;
989 /* rs == 31 encodes a write to the ZR, thus throwing away
990 * the status return. This is rather silly but valid.
991 */
992 if (rs < 31) {
993 env->xregs[rs] = rc;
994 }
995error:
996 /* instruction faulted, PC does not advance */
997 /* either way a strex releases any exclusive lock we have */
998 env->exclusive_addr = -1;
999 end_exclusive();
1000 return segv;
1001}
1002
1861c454
PM		 1003/* AArch64 main loop */
1004void cpu_loop(CPUARMState *env)
1005{
1006 CPUState *cs = CPU(arm_env_get_cpu(env));
1007 int trapnr, sig;
1008 target_siginfo_t info;
1861c454
PM		 1009
1010 for (;;) {
1011 cpu_exec_start(cs);
1012 trapnr = cpu_arm_exec(env);
1013 cpu_exec_end(cs);
1014
1015 switch (trapnr) {
1016 case EXCP_SWI:
1017 env->xregs[0] = do_syscall(env,
1018 env->xregs[8],
1019 env->xregs[0],
1020 env->xregs[1],
1021 env->xregs[2],
1022 env->xregs[3],
1023 env->xregs[4],
1024 env->xregs[5],
1025 0, 0);
1026 break;
1027 case EXCP_INTERRUPT:
1028 /* just indicate that signals should be handled asap */
1029 break;
1030 case EXCP_UDEF:
1031 info.si_signo = SIGILL;
1032 info.si_errno = 0;
1033 info.si_code = TARGET_ILL_ILLOPN;
1034 info._sifields._sigfault._addr = env->pc;
1035 queue_signal(env, info.si_signo, &info);
1036 break;
abf1172f
PM		 1037 case EXCP_STREX:
1038 if (!do_strex_a64(env)) {
1039 break;
1040 }
1041 /* fall through for segv */
1861c454 1042 case EXCP_PREFETCH_ABORT:
1861c454 1043 case EXCP_DATA_ABORT:
1861c454
PM		 1044 info.si_signo = SIGSEGV;
1045 info.si_errno = 0;
1046 /* XXX: check env->error_code */
1047 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1048 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1049 queue_signal(env, info.si_signo, &info);
1050 break;
1051 case EXCP_DEBUG:
1052 case EXCP_BKPT:
1053 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1054 if (sig) {
1055 info.si_signo = sig;
1056 info.si_errno = 0;
1057 info.si_code = TARGET_TRAP_BRKPT;
1058 queue_signal(env, info.si_signo, &info);
1059 }
1060 break;
1861c454
PM		 1061 default:
1062 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1063 trapnr);
1064 cpu_dump_state(cs, stderr, fprintf, 0);
1065 abort();
1066 }
1067 process_pending_signals(env);
fa2ef212
MM		 1068 /* Exception return on AArch64 always clears the exclusive monitor,
1069 * so any return to running guest code implies this.
1070 * A strex (successful or otherwise) also clears the monitor, so
1071 * we don't need to specialcase EXCP_STREX.
1072 */
1073 env->exclusive_addr = -1;
1861c454
PM		 1074 }
1075}
1076#endif /* ndef TARGET_ABI32 */
1077
b346ff46 1078#endif
1b6b029e 1079
d2fbca94
GX		 1080#ifdef TARGET_UNICORE32
1081
05390248 1082void cpu_loop(CPUUniCore32State *env)
d2fbca94 1083{
0315c31c 1084 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1085 int trapnr;
1086 unsigned int n, insn;
1087 target_siginfo_t info;
1088
1089 for (;;) {
0315c31c 1090 cpu_exec_start(cs);
d2fbca94 1091 trapnr = uc32_cpu_exec(env);
0315c31c 1092 cpu_exec_end(cs);
d2fbca94
GX		 1093 switch (trapnr) {
1094 case UC32_EXCP_PRIV:
1095 {
1096 /* system call */
1097 get_user_u32(insn, env->regs[31] - 4);
1098 n = insn & 0xffffff;
1099
1100 if (n >= UC32_SYSCALL_BASE) {
1101 /* linux syscall */
1102 n -= UC32_SYSCALL_BASE;
1103 if (n == UC32_SYSCALL_NR_set_tls) {
1104 cpu_set_tls(env, env->regs[0]);
1105 env->regs[0] = 0;
1106 } else {
1107 env->regs[0] = do_syscall(env,
1108 n,
1109 env->regs[0],
1110 env->regs[1],
1111 env->regs[2],
1112 env->regs[3],
1113 env->regs[4],
5945cfcb
PM		 1114 env->regs[5],
1115 0, 0);
d2fbca94
GX		 1116 }
1117 } else {
1118 goto error;
1119 }
1120 }
1121 break;
d48813dd
GX		 1122 case UC32_EXCP_DTRAP:
1123 case UC32_EXCP_ITRAP:
d2fbca94
GX		 1124 info.si_signo = SIGSEGV;
1125 info.si_errno = 0;
1126 /* XXX: check env->error_code */
1127 info.si_code = TARGET_SEGV_MAPERR;
1128 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1129 queue_signal(env, info.si_signo, &info);
1130 break;
1131 case EXCP_INTERRUPT:
1132 /* just indicate that signals should be handled asap */
1133 break;
1134 case EXCP_DEBUG:
1135 {
1136 int sig;
1137
db6b81d4 1138 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1139 if (sig) {
1140 info.si_signo = sig;
1141 info.si_errno = 0;
1142 info.si_code = TARGET_TRAP_BRKPT;
1143 queue_signal(env, info.si_signo, &info);
1144 }
1145 }
1146 break;
1147 default:
1148 goto error;
1149 }
1150 process_pending_signals(env);
1151 }
1152
1153error:
1154 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1155 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1156 abort();
1157}
1158#endif
1159
93ac68bc 1160#ifdef TARGET_SPARC
ed23fbd9 1161#define SPARC64_STACK_BIAS 2047
93ac68bc 1162
060366c5
FB		 1163//#define DEBUG_WIN
1164
2623cbaf
FB		 1165/* WARNING: dealing with register windows _is_ complicated. More info
1166 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1167static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1168{
1a14026e 1169 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1170 /* wrap handling : if cwp is on the last window, then we use the
1171 registers 'after' the end */
1a14026e
BS		 1172 if (index < 8 && env->cwp == env->nwindows - 1)
1173 index += 16 * env->nwindows;
060366c5
FB		 1174 return index;
1175}
1176
2623cbaf
FB		 1177/* save the register window 'cwp1' */
1178static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1179{
2623cbaf 1180 unsigned int i;
992f48a0 1181 abi_ulong sp_ptr;
3b46e624 1182
53a5960a 1183 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1184#ifdef TARGET_SPARC64
1185 if (sp_ptr & 3)
1186 sp_ptr += SPARC64_STACK_BIAS;
1187#endif
060366c5 1188#if defined(DEBUG_WIN)
2daf0284
BS		 1189 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1190 sp_ptr, cwp1);
060366c5 1191#endif
2623cbaf 1192 for(i = 0; i < 16; i++) {
2f619698
FB		 1193 /* FIXME - what to do if put_user() fails? */
1194 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1195 sp_ptr += sizeof(abi_ulong);
2623cbaf 1196 }
060366c5
FB		 1197}
1198
1199static void save_window(CPUSPARCState *env)
1200{
5ef54116 1201#ifndef TARGET_SPARC64
2623cbaf 1202 unsigned int new_wim;
1a14026e
BS		 1203 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1204 ((1LL << env->nwindows) - 1);
1205 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1206 env->wim = new_wim;
5ef54116 1207#else
1a14026e 1208 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1209 env->cansave++;
1210 env->canrestore--;
1211#endif
060366c5
FB		 1212}
1213
1214static void restore_window(CPUSPARCState *env)
1215{
eda52953
BS		 1216#ifndef TARGET_SPARC64
1217 unsigned int new_wim;
1218#endif
1219 unsigned int i, cwp1;
992f48a0 1220 abi_ulong sp_ptr;
3b46e624 1221
eda52953 1222#ifndef TARGET_SPARC64
1a14026e
BS		 1223 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1224 ((1LL << env->nwindows) - 1);
eda52953 1225#endif
3b46e624 1226
060366c5 1227 /* restore the invalid window */
1a14026e 1228 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1229 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1230#ifdef TARGET_SPARC64
1231 if (sp_ptr & 3)
1232 sp_ptr += SPARC64_STACK_BIAS;
1233#endif
060366c5 1234#if defined(DEBUG_WIN)
2daf0284
BS		 1235 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1236 sp_ptr, cwp1);
060366c5 1237#endif
2623cbaf 1238 for(i = 0; i < 16; i++) {
2f619698
FB		 1239 /* FIXME - what to do if get_user() fails? */
1240 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1241 sp_ptr += sizeof(abi_ulong);
2623cbaf 1242 }
5ef54116
FB		 1243#ifdef TARGET_SPARC64
1244 env->canrestore++;
1a14026e
BS		 1245 if (env->cleanwin < env->nwindows - 1)
1246 env->cleanwin++;
5ef54116 1247 env->cansave--;
eda52953
BS		 1248#else
1249 env->wim = new_wim;
5ef54116 1250#endif
060366c5
FB		 1251}
1252
1253static void flush_windows(CPUSPARCState *env)
1254{
1255 int offset, cwp1;
2623cbaf
FB		 1256
1257 offset = 1;
060366c5
FB		 1258 for(;;) {
1259 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1260 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1261#ifndef TARGET_SPARC64
060366c5
FB		 1262 if (env->wim & (1 << cwp1))
1263 break;
eda52953
BS		 1264#else
1265 if (env->canrestore == 0)
1266 break;
1267 env->cansave++;
1268 env->canrestore--;
1269#endif
2623cbaf 1270 save_window_offset(env, cwp1);
060366c5
FB		 1271 offset++;
1272 }
1a14026e 1273 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1274#ifndef TARGET_SPARC64
1275 /* set wim so that restore will reload the registers */
2623cbaf 1276 env->wim = 1 << cwp1;
eda52953 1277#endif
2623cbaf
FB		 1278#if defined(DEBUG_WIN)
1279 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1280#endif
2623cbaf 1281}
060366c5 1282
93ac68bc
FB		 1283void cpu_loop (CPUSPARCState *env)
1284{
878096ee 1285 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1286 int trapnr;
1287 abi_long ret;
c227f099 1288 target_siginfo_t info;
3b46e624 1289
060366c5
FB		 1290 while (1) {
1291 trapnr = cpu_sparc_exec (env);
3b46e624 1292
20132b96
RH		 1293 /* Compute PSR before exposing state. */
1294 if (env->cc_op != CC_OP_FLAGS) {
1295 cpu_get_psr(env);
1296 }
1297
060366c5 1298 switch (trapnr) {
5ef54116 1299#ifndef TARGET_SPARC64
5fafdf24 1300 case 0x88:
060366c5 1301 case 0x90:
5ef54116 1302#else
cb33da57 1303 case 0x110:
5ef54116
FB		 1304 case 0x16d:
1305#endif
060366c5 1306 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1307 env->regwptr[0], env->regwptr[1],
1308 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1309 env->regwptr[4], env->regwptr[5],
1310 0, 0);
2cc20260 1311 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1312#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1313 env->xcc |= PSR_CARRY;
1314#else
060366c5 1315 env->psr |= PSR_CARRY;
27908725 1316#endif
060366c5
FB		 1317 ret = -ret;
1318 } else {
992f48a0 1319#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1320 env->xcc &= ~PSR_CARRY;
1321#else
060366c5 1322 env->psr &= ~PSR_CARRY;
27908725 1323#endif
060366c5
FB		 1324 }
1325 env->regwptr[0] = ret;
1326 /* next instruction */
1327 env->pc = env->npc;
1328 env->npc = env->npc + 4;
1329 break;
1330 case 0x83: /* flush windows */
992f48a0
BS		 1331#ifdef TARGET_ABI32
1332 case 0x103:
1333#endif
2623cbaf 1334 flush_windows(env);
060366c5
FB		 1335 /* next instruction */
1336 env->pc = env->npc;
1337 env->npc = env->npc + 4;
1338 break;
3475187d 1339#ifndef TARGET_SPARC64
060366c5
FB		 1340 case TT_WIN_OVF: /* window overflow */
1341 save_window(env);
1342 break;
1343 case TT_WIN_UNF: /* window underflow */
1344 restore_window(env);
1345 break;
61ff6f58
FB		 1346 case TT_TFAULT:
1347 case TT_DFAULT:
1348 {
59f7182f 1349 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1350 info.si_errno = 0;
1351 /* XXX: check env->error_code */
1352 info.si_code = TARGET_SEGV_MAPERR;
1353 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1354 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1355 }
1356 break;
3475187d 1357#else
5ef54116
FB		 1358 case TT_SPILL: /* window overflow */
1359 save_window(env);
1360 break;
1361 case TT_FILL: /* window underflow */
1362 restore_window(env);
1363 break;
7f84a729
BS		 1364 case TT_TFAULT:
1365 case TT_DFAULT:
1366 {
59f7182f 1367 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1368 info.si_errno = 0;
1369 /* XXX: check env->error_code */
1370 info.si_code = TARGET_SEGV_MAPERR;
1371 if (trapnr == TT_DFAULT)
1372 info._sifields._sigfault._addr = env->dmmuregs[4];
1373 else
8194f35a 1374 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1375 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1376 }
1377 break;
27524dc3 1378#ifndef TARGET_ABI32
5bfb56b2
BS		 1379 case 0x16e:
1380 flush_windows(env);
1381 sparc64_get_context(env);
1382 break;
1383 case 0x16f:
1384 flush_windows(env);
1385 sparc64_set_context(env);
1386 break;
27524dc3 1387#endif
3475187d 1388#endif
48dc41eb
FB		 1389 case EXCP_INTERRUPT:
1390 /* just indicate that signals should be handled asap */
1391 break;
75f22e4e
RH		 1392 case TT_ILL_INSN:
1393 {
1394 info.si_signo = TARGET_SIGILL;
1395 info.si_errno = 0;
1396 info.si_code = TARGET_ILL_ILLOPC;
1397 info._sifields._sigfault._addr = env->pc;
1398 queue_signal(env, info.si_signo, &info);
1399 }
1400 break;
1fddef4b
FB		 1401 case EXCP_DEBUG:
1402 {
1403 int sig;
1404
db6b81d4 1405 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1406 if (sig)
1407 {
1408 info.si_signo = sig;
1409 info.si_errno = 0;
1410 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1411 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1412 }
1413 }
1414 break;
060366c5
FB		 1415 default:
1416 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1417 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1418 exit (1);
1419 }
1420 process_pending_signals (env);
1421 }
93ac68bc
FB		 1422}
1423
1424#endif
1425
67867308 1426#ifdef TARGET_PPC
05390248 1427static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1428{
1429 /* TO FIX */
1430 return 0;
1431}
3b46e624 1432
05390248 1433uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1434{
e3ea6529 1435 return cpu_ppc_get_tb(env);
9fddaa0c 1436}
3b46e624 1437
05390248 1438uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1439{
1440 return cpu_ppc_get_tb(env) >> 32;
1441}
3b46e624 1442
05390248 1443uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1444{
b711de95 1445 return cpu_ppc_get_tb(env);
9fddaa0c 1446}
5fafdf24 1447
05390248 1448uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1449{
a062e36c 1450 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1451}
76a66253 1452
05390248 1453uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1454__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1455
05390248 1456uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1457{
76a66253 1458 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1459}
76a66253 1460
a750fc0b 1461/* XXX: to be fixed */
73b01960 1462int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1463{
1464 return -1;
1465}
1466
73b01960 1467int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1468{
1469 return -1;
1470}
1471
001faf32
BS		 1472#define EXCP_DUMP(env, fmt, ...) \
1473do { \
a0762859 1474 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1475 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1476 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1477 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1478 if (qemu_log_enabled()) { \
a0762859 1479 log_cpu_state(cs, 0); \
eeacee4d 1480 } \
e1833e1f
JM		 1481} while (0)
1482
56f066bb
NF		 1483static int do_store_exclusive(CPUPPCState *env)
1484{
1485 target_ulong addr;
1486 target_ulong page_addr;
e22c357b 1487 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1488 int flags;
1489 int segv = 0;
1490
1491 addr = env->reserve_ea;
1492 page_addr = addr & TARGET_PAGE_MASK;
1493 start_exclusive();
1494 mmap_lock();
1495 flags = page_get_flags(page_addr);
1496 if ((flags & PAGE_READ) == 0) {
1497 segv = 1;
1498 } else {
1499 int reg = env->reserve_info & 0x1f;
4b1daa72 1500 int size = env->reserve_info >> 5;
56f066bb
NF		 1501 int stored = 0;
1502
1503 if (addr == env->reserve_addr) {
1504 switch (size) {
1505 case 1: segv = get_user_u8(val, addr); break;
1506 case 2: segv = get_user_u16(val, addr); break;
1507 case 4: segv = get_user_u32(val, addr); break;
1508#if defined(TARGET_PPC64)
1509 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1510 case 16: {
1511 segv = get_user_u64(val, addr);
1512 if (!segv) {
1513 segv = get_user_u64(val2, addr + 8);
1514 }
1515 break;
1516 }
56f066bb
NF		 1517#endif
1518 default: abort();
1519 }
1520 if (!segv && val == env->reserve_val) {
1521 val = env->gpr[reg];
1522 switch (size) {
1523 case 1: segv = put_user_u8(val, addr); break;
1524 case 2: segv = put_user_u16(val, addr); break;
1525 case 4: segv = put_user_u32(val, addr); break;
1526#if defined(TARGET_PPC64)
1527 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1528 case 16: {
1529 if (val2 == env->reserve_val2) {
e22c357b
DK		 1530 if (msr_le) {
1531 val2 = val;
1532 val = env->gpr[reg+1];
1533 } else {
1534 val2 = env->gpr[reg+1];
1535 }
27b95bfe
TM		 1536 segv = put_user_u64(val, addr);
1537 if (!segv) {
1538 segv = put_user_u64(val2, addr + 8);
1539 }
1540 }
1541 break;
1542 }
56f066bb
NF		 1543#endif
1544 default: abort();
1545 }
1546 if (!segv) {
1547 stored = 1;
1548 }
1549 }
1550 }
1551 env->crf[0] = (stored << 1) | xer_so;
1552 env->reserve_addr = (target_ulong)-1;
1553 }
1554 if (!segv) {
1555 env->nip += 4;
1556 }
1557 mmap_unlock();
1558 end_exclusive();
1559 return segv;
1560}
1561
67867308
FB		 1562void cpu_loop(CPUPPCState *env)
1563{
0315c31c 1564 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1565 target_siginfo_t info;
61190b14 1566 int trapnr;
9e0e2f96 1567 target_ulong ret;
3b46e624 1568
67867308 1569 for(;;) {
0315c31c 1570 cpu_exec_start(cs);
67867308 1571 trapnr = cpu_ppc_exec(env);
0315c31c 1572 cpu_exec_end(cs);
67867308 1573 switch(trapnr) {
e1833e1f
JM		 1574 case POWERPC_EXCP_NONE:
1575 /* Just go on */
67867308 1576 break;
e1833e1f 1577 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1578 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1579 "Aborting\n");
61190b14 1580 break;
e1833e1f 1581 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1582 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1583 "Aborting\n");
1584 break;
1585 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1586 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1587 env->spr[SPR_DAR]);
1588 /* XXX: check this. Seems bugged */
2be0071f
FB		 1589 switch (env->error_code & 0xFF000000) {
1590 case 0x40000000:
61190b14
FB		 1591 info.si_signo = TARGET_SIGSEGV;
1592 info.si_errno = 0;
1593 info.si_code = TARGET_SEGV_MAPERR;
1594 break;
2be0071f 1595 case 0x04000000:
61190b14
FB		 1596 info.si_signo = TARGET_SIGILL;
1597 info.si_errno = 0;
1598 info.si_code = TARGET_ILL_ILLADR;
1599 break;
2be0071f 1600 case 0x08000000:
61190b14
FB		 1601 info.si_signo = TARGET_SIGSEGV;
1602 info.si_errno = 0;
1603 info.si_code = TARGET_SEGV_ACCERR;
1604 break;
61190b14
FB		 1605 default:
1606 /* Let's send a regular segfault... */
e1833e1f
JM		 1607 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1608 env->error_code);
61190b14
FB		 1609 info.si_signo = TARGET_SIGSEGV;
1610 info.si_errno = 0;
1611 info.si_code = TARGET_SEGV_MAPERR;
1612 break;
1613 }
67867308 1614 info._sifields._sigfault._addr = env->nip;
624f7979 1615 queue_signal(env, info.si_signo, &info);
67867308 1616 break;
e1833e1f 1617 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1618 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1619 "\n", env->spr[SPR_SRR0]);
e1833e1f 1620 /* XXX: check this */
2be0071f
FB		 1621 switch (env->error_code & 0xFF000000) {
1622 case 0x40000000:
61190b14 1623 info.si_signo = TARGET_SIGSEGV;
67867308 1624 info.si_errno = 0;
61190b14
FB		 1625 info.si_code = TARGET_SEGV_MAPERR;
1626 break;
2be0071f
FB		 1627 case 0x10000000:
1628 case 0x08000000:
61190b14
FB		 1629 info.si_signo = TARGET_SIGSEGV;
1630 info.si_errno = 0;
1631 info.si_code = TARGET_SEGV_ACCERR;
1632 break;
1633 default:
1634 /* Let's send a regular segfault... */
e1833e1f
JM		 1635 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1636 env->error_code);
61190b14
FB		 1637 info.si_signo = TARGET_SIGSEGV;
1638 info.si_errno = 0;
1639 info.si_code = TARGET_SEGV_MAPERR;
1640 break;
1641 }
1642 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1643 queue_signal(env, info.si_signo, &info);
67867308 1644 break;
e1833e1f 1645 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1646 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1647 "Aborting\n");
1648 break;
1649 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1650 EXCP_DUMP(env, "Unaligned memory access\n");
1651 /* XXX: check this */
61190b14 1652 info.si_signo = TARGET_SIGBUS;
67867308 1653 info.si_errno = 0;
61190b14
FB		 1654 info.si_code = TARGET_BUS_ADRALN;
1655 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1656 queue_signal(env, info.si_signo, &info);
67867308 1657 break;
e1833e1f
JM		 1658 case POWERPC_EXCP_PROGRAM: /* Program exception */
1659 /* XXX: check this */
61190b14 1660 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1661 case POWERPC_EXCP_FP:
1662 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1663 info.si_signo = TARGET_SIGFPE;
1664 info.si_errno = 0;
1665 switch (env->error_code & 0xF) {
e1833e1f 1666 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1667 info.si_code = TARGET_FPE_FLTOVF;
1668 break;
e1833e1f 1669 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1670 info.si_code = TARGET_FPE_FLTUND;
1671 break;
e1833e1f
JM		 1672 case POWERPC_EXCP_FP_ZX:
1673 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1674 info.si_code = TARGET_FPE_FLTDIV;
1675 break;
e1833e1f 1676 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1677 info.si_code = TARGET_FPE_FLTRES;
1678 break;
e1833e1f 1679 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1680 info.si_code = TARGET_FPE_FLTINV;
1681 break;
7c58044c 1682 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1683 case POWERPC_EXCP_FP_VXISI:
1684 case POWERPC_EXCP_FP_VXIDI:
1685 case POWERPC_EXCP_FP_VXIMZ:
1686 case POWERPC_EXCP_FP_VXVC:
1687 case POWERPC_EXCP_FP_VXSQRT:
1688 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1689 info.si_code = TARGET_FPE_FLTSUB;
1690 break;
1691 default:
e1833e1f
JM		 1692 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1693 env->error_code);
1694 break;
61190b14 1695 }
e1833e1f
JM		 1696 break;
1697 case POWERPC_EXCP_INVAL:
1698 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1699 info.si_signo = TARGET_SIGILL;
1700 info.si_errno = 0;
1701 switch (env->error_code & 0xF) {
e1833e1f 1702 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1703 info.si_code = TARGET_ILL_ILLOPC;
1704 break;
e1833e1f 1705 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1706 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1707 break;
e1833e1f 1708 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1709 info.si_code = TARGET_ILL_PRVREG;
1710 break;
e1833e1f 1711 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1712 info.si_code = TARGET_ILL_COPROC;
1713 break;
1714 default:
e1833e1f
JM		 1715 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1716 env->error_code & 0xF);
61190b14
FB		 1717 info.si_code = TARGET_ILL_ILLADR;
1718 break;
1719 }
1720 break;
e1833e1f
JM		 1721 case POWERPC_EXCP_PRIV:
1722 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1723 info.si_signo = TARGET_SIGILL;
1724 info.si_errno = 0;
1725 switch (env->error_code & 0xF) {
e1833e1f 1726 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1727 info.si_code = TARGET_ILL_PRVOPC;
1728 break;
e1833e1f 1729 case POWERPC_EXCP_PRIV_REG:
61190b14 1730 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1731 break;
61190b14 1732 default:
e1833e1f
JM		 1733 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1734 env->error_code & 0xF);
61190b14
FB		 1735 info.si_code = TARGET_ILL_PRVOPC;
1736 break;
1737 }
1738 break;
e1833e1f 1739 case POWERPC_EXCP_TRAP:
a47dddd7 1740 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1741 break;
61190b14
FB		 1742 default:
1743 /* Should not happen ! */
a47dddd7 1744 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1745 env->error_code);
1746 break;
61190b14
FB		 1747 }
1748 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1749 queue_signal(env, info.si_signo, &info);
67867308 1750 break;
e1833e1f
JM		 1751 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1752 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1753 info.si_signo = TARGET_SIGILL;
67867308 1754 info.si_errno = 0;
61190b14
FB		 1755 info.si_code = TARGET_ILL_COPROC;
1756 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1757 queue_signal(env, info.si_signo, &info);
67867308 1758 break;
e1833e1f 1759 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1760 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1761 "Aborting\n");
61190b14 1762 break;
e1833e1f
JM		 1763 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1764 EXCP_DUMP(env, "No APU instruction allowed\n");
1765 info.si_signo = TARGET_SIGILL;
1766 info.si_errno = 0;
1767 info.si_code = TARGET_ILL_COPROC;
1768 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1769 queue_signal(env, info.si_signo, &info);
61190b14 1770 break;
e1833e1f 1771 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1772 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1773 "Aborting\n");
61190b14 1774 break;
e1833e1f 1775 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1776 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1777 "Aborting\n");
1778 break;
1779 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1780 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1781 "Aborting\n");
1782 break;
1783 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1784 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1785 "Aborting\n");
1786 break;
1787 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1788 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1789 "Aborting\n");
1790 break;
e1833e1f
JM		 1791 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1792 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1793 info.si_signo = TARGET_SIGILL;
1794 info.si_errno = 0;
1795 info.si_code = TARGET_ILL_COPROC;
1796 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1797 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1798 break;
1799 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1800 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1801 break;
1802 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1803 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1804 break;
1805 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1806 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1807 break;
1808 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1809 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1810 "Aborting\n");
1811 break;
1812 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1813 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1814 "Aborting\n");
1815 break;
1816 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1817 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1818 "Aborting\n");
1819 break;
e1833e1f 1820 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1821 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1822 "Aborting\n");
1823 break;
1824 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1825 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1826 "while in user mode. Aborting\n");
1827 break;
e85e7c6e 1828 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1829 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1830 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1831 "while in user mode. Aborting\n");
1832 break;
e1833e1f
JM		 1833 case POWERPC_EXCP_TRACE: /* Trace exception */
1834 /* Nothing to do:
1835 * we use this exception to emulate step-by-step execution mode.
1836 */
1837 break;
e85e7c6e 1838 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1839 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1840 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1841 "while in user mode. Aborting\n");
1842 break;
1843 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1844 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1845 "while in user mode. Aborting\n");
1846 break;
1847 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1848 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1849 "while in user mode. Aborting\n");
1850 break;
1851 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1852 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1853 "while in user mode. Aborting\n");
1854 break;
e1833e1f
JM		 1855 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1856 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1857 info.si_signo = TARGET_SIGILL;
1858 info.si_errno = 0;
1859 info.si_code = TARGET_ILL_COPROC;
1860 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1861 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1862 break;
1863 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1864 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1865 "while in user mode. Aborting\n");
1866 break;
1867 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1868 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1869 "Aborting\n");
1870 break;
1871 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1872 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1873 "Aborting\n");
1874 break;
1875 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1876 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1877 break;
1878 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1879 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1880 "while in user-mode. Aborting");
1881 break;
1882 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1883 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1884 "Aborting");
1885 break;
1886 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1887 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1888 "Aborting");
1889 break;
1890 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1891 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1892 break;
1893 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1894 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1895 "not handled\n");
1896 break;
1897 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1898 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1899 "Aborting\n");
1900 break;
1901 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1902 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1903 "Aborting\n");
1904 break;
1905 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1906 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1907 break;
1908 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1909 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1910 break;
1911 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1912 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1913 break;
1914 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1915 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1916 "Aborting\n");
1917 break;
1918 case POWERPC_EXCP_STOP: /* stop translation */
1919 /* We did invalidate the instruction cache. Go on */
1920 break;
1921 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1922 /* We just stopped because of a branch. Go on */
1923 break;
1924 case POWERPC_EXCP_SYSCALL_USER:
1925 /* system call in user-mode emulation */
1926 /* WARNING:
1927 * PPC ABI uses overflow flag in cr0 to signal an error
1928 * in syscalls.
1929 */
e1833e1f
JM		 1930 env->crf[0] &= ~0x1;
1931 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1932 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1933 env->gpr[8], 0, 0);
9e0e2f96 1934 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1935 /* Returning from a successful sigreturn syscall.
1936 Avoid corrupting register state. */
1937 break;
1938 }
9e0e2f96 1939 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1940 env->crf[0] |= 0x1;
1941 ret = -ret;
61190b14 1942 }
e1833e1f 1943 env->gpr[3] = ret;
e1833e1f 1944 break;
56f066bb
NF		 1945 case POWERPC_EXCP_STCX:
1946 if (do_store_exclusive(env)) {
1947 info.si_signo = TARGET_SIGSEGV;
1948 info.si_errno = 0;
1949 info.si_code = TARGET_SEGV_MAPERR;
1950 info._sifields._sigfault._addr = env->nip;
1951 queue_signal(env, info.si_signo, &info);
1952 }
1953 break;
71f75756
AJ		 1954 case EXCP_DEBUG:
1955 {
1956 int sig;
1957
db6b81d4 1958 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1959 if (sig) {
1960 info.si_signo = sig;
1961 info.si_errno = 0;
1962 info.si_code = TARGET_TRAP_BRKPT;
1963 queue_signal(env, info.si_signo, &info);
1964 }
1965 }
1966 break;
56ba31ff
JM		 1967 case EXCP_INTERRUPT:
1968 /* just indicate that signals should be handled asap */
1969 break;
e1833e1f 1970 default:
a47dddd7 1971 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1972 break;
67867308
FB		 1973 }
1974 process_pending_signals(env);
1975 }
1976}
1977#endif
1978
048f6b4d
FB		 1979#ifdef TARGET_MIPS
1980
ff4f7382
RH		 1981# ifdef TARGET_ABI_MIPSO32
1982# define MIPS_SYS(name, args) args,
048f6b4d 1983static const uint8_t mips_syscall_args[] = {
29fb0f25 1984 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1985 MIPS_SYS(sys_exit , 1)
1986 MIPS_SYS(sys_fork , 0)
1987 MIPS_SYS(sys_read , 3)
1988 MIPS_SYS(sys_write , 3)
1989 MIPS_SYS(sys_open , 3) /* 4005 */
1990 MIPS_SYS(sys_close , 1)
1991 MIPS_SYS(sys_waitpid , 3)
1992 MIPS_SYS(sys_creat , 2)
1993 MIPS_SYS(sys_link , 2)
1994 MIPS_SYS(sys_unlink , 1) /* 4010 */
1995 MIPS_SYS(sys_execve , 0)
1996 MIPS_SYS(sys_chdir , 1)
1997 MIPS_SYS(sys_time , 1)
1998 MIPS_SYS(sys_mknod , 3)
1999 MIPS_SYS(sys_chmod , 2) /* 4015 */
2000 MIPS_SYS(sys_lchown , 3)
2001 MIPS_SYS(sys_ni_syscall , 0)
2002 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2003 MIPS_SYS(sys_lseek , 3)
2004 MIPS_SYS(sys_getpid , 0) /* 4020 */
2005 MIPS_SYS(sys_mount , 5)
868e34d7 2006 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2007 MIPS_SYS(sys_setuid , 1)
2008 MIPS_SYS(sys_getuid , 0)
2009 MIPS_SYS(sys_stime , 1) /* 4025 */
2010 MIPS_SYS(sys_ptrace , 4)
2011 MIPS_SYS(sys_alarm , 1)
2012 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2013 MIPS_SYS(sys_pause , 0)
2014 MIPS_SYS(sys_utime , 2) /* 4030 */
2015 MIPS_SYS(sys_ni_syscall , 0)
2016 MIPS_SYS(sys_ni_syscall , 0)
2017 MIPS_SYS(sys_access , 2)
2018 MIPS_SYS(sys_nice , 1)
2019 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2020 MIPS_SYS(sys_sync , 0)
2021 MIPS_SYS(sys_kill , 2)
2022 MIPS_SYS(sys_rename , 2)
2023 MIPS_SYS(sys_mkdir , 2)
2024 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2025 MIPS_SYS(sys_dup , 1)
2026 MIPS_SYS(sys_pipe , 0)
2027 MIPS_SYS(sys_times , 1)
2028 MIPS_SYS(sys_ni_syscall , 0)
2029 MIPS_SYS(sys_brk , 1) /* 4045 */
2030 MIPS_SYS(sys_setgid , 1)
2031 MIPS_SYS(sys_getgid , 0)
2032 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2033 MIPS_SYS(sys_geteuid , 0)
2034 MIPS_SYS(sys_getegid , 0) /* 4050 */
2035 MIPS_SYS(sys_acct , 0)
868e34d7 2036 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2037 MIPS_SYS(sys_ni_syscall , 0)
2038 MIPS_SYS(sys_ioctl , 3)
2039 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2040 MIPS_SYS(sys_ni_syscall , 2)
2041 MIPS_SYS(sys_setpgid , 2)
2042 MIPS_SYS(sys_ni_syscall , 0)
2043 MIPS_SYS(sys_olduname , 1)
2044 MIPS_SYS(sys_umask , 1) /* 4060 */
2045 MIPS_SYS(sys_chroot , 1)
2046 MIPS_SYS(sys_ustat , 2)
2047 MIPS_SYS(sys_dup2 , 2)
2048 MIPS_SYS(sys_getppid , 0)
2049 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2050 MIPS_SYS(sys_setsid , 0)
2051 MIPS_SYS(sys_sigaction , 3)
2052 MIPS_SYS(sys_sgetmask , 0)
2053 MIPS_SYS(sys_ssetmask , 1)
2054 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2055 MIPS_SYS(sys_setregid , 2)
2056 MIPS_SYS(sys_sigsuspend , 0)
2057 MIPS_SYS(sys_sigpending , 1)
2058 MIPS_SYS(sys_sethostname , 2)
2059 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2060 MIPS_SYS(sys_getrlimit , 2)
2061 MIPS_SYS(sys_getrusage , 2)
2062 MIPS_SYS(sys_gettimeofday, 2)
2063 MIPS_SYS(sys_settimeofday, 2)
2064 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2065 MIPS_SYS(sys_setgroups , 2)
2066 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2067 MIPS_SYS(sys_symlink , 2)
2068 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2069 MIPS_SYS(sys_readlink , 3) /* 4085 */
2070 MIPS_SYS(sys_uselib , 1)
2071 MIPS_SYS(sys_swapon , 2)
2072 MIPS_SYS(sys_reboot , 3)
2073 MIPS_SYS(old_readdir , 3)
2074 MIPS_SYS(old_mmap , 6) /* 4090 */
2075 MIPS_SYS(sys_munmap , 2)
2076 MIPS_SYS(sys_truncate , 2)
2077 MIPS_SYS(sys_ftruncate , 2)
2078 MIPS_SYS(sys_fchmod , 2)
2079 MIPS_SYS(sys_fchown , 3) /* 4095 */
2080 MIPS_SYS(sys_getpriority , 2)
2081 MIPS_SYS(sys_setpriority , 3)
2082 MIPS_SYS(sys_ni_syscall , 0)
2083 MIPS_SYS(sys_statfs , 2)
2084 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2085 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2086 MIPS_SYS(sys_socketcall , 2)
2087 MIPS_SYS(sys_syslog , 3)
2088 MIPS_SYS(sys_setitimer , 3)
2089 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2090 MIPS_SYS(sys_newstat , 2)
2091 MIPS_SYS(sys_newlstat , 2)
2092 MIPS_SYS(sys_newfstat , 2)
2093 MIPS_SYS(sys_uname , 1)
2094 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2095 MIPS_SYS(sys_vhangup , 0)
2096 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2097 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2098 MIPS_SYS(sys_wait4 , 4)
2099 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2100 MIPS_SYS(sys_sysinfo , 1)
2101 MIPS_SYS(sys_ipc , 6)
2102 MIPS_SYS(sys_fsync , 1)
2103 MIPS_SYS(sys_sigreturn , 0)
18113962 2104 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2105 MIPS_SYS(sys_setdomainname, 2)
2106 MIPS_SYS(sys_newuname , 1)
2107 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2108 MIPS_SYS(sys_adjtimex , 1)
2109 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2110 MIPS_SYS(sys_sigprocmask , 3)
2111 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2112 MIPS_SYS(sys_init_module , 5)
2113 MIPS_SYS(sys_delete_module, 1)
2114 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2115 MIPS_SYS(sys_quotactl , 0)
2116 MIPS_SYS(sys_getpgid , 1)
2117 MIPS_SYS(sys_fchdir , 1)
2118 MIPS_SYS(sys_bdflush , 2)
2119 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2120 MIPS_SYS(sys_personality , 1)
2121 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2122 MIPS_SYS(sys_setfsuid , 1)
2123 MIPS_SYS(sys_setfsgid , 1)
2124 MIPS_SYS(sys_llseek , 5) /* 4140 */
2125 MIPS_SYS(sys_getdents , 3)
2126 MIPS_SYS(sys_select , 5)
2127 MIPS_SYS(sys_flock , 2)
2128 MIPS_SYS(sys_msync , 3)
2129 MIPS_SYS(sys_readv , 3) /* 4145 */
2130 MIPS_SYS(sys_writev , 3)
2131 MIPS_SYS(sys_cacheflush , 3)
2132 MIPS_SYS(sys_cachectl , 3)
2133 MIPS_SYS(sys_sysmips , 4)
2134 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2135 MIPS_SYS(sys_getsid , 1)
2136 MIPS_SYS(sys_fdatasync , 0)
2137 MIPS_SYS(sys_sysctl , 1)
2138 MIPS_SYS(sys_mlock , 2)
2139 MIPS_SYS(sys_munlock , 2) /* 4155 */
2140 MIPS_SYS(sys_mlockall , 1)
2141 MIPS_SYS(sys_munlockall , 0)
2142 MIPS_SYS(sys_sched_setparam, 2)
2143 MIPS_SYS(sys_sched_getparam, 2)
2144 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2145 MIPS_SYS(sys_sched_getscheduler, 1)
2146 MIPS_SYS(sys_sched_yield , 0)
2147 MIPS_SYS(sys_sched_get_priority_max, 1)
2148 MIPS_SYS(sys_sched_get_priority_min, 1)
2149 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2150 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2151 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2152 MIPS_SYS(sys_accept , 3)
2153 MIPS_SYS(sys_bind , 3)
2154 MIPS_SYS(sys_connect , 3) /* 4170 */
2155 MIPS_SYS(sys_getpeername , 3)
2156 MIPS_SYS(sys_getsockname , 3)
2157 MIPS_SYS(sys_getsockopt , 5)
2158 MIPS_SYS(sys_listen , 2)
2159 MIPS_SYS(sys_recv , 4) /* 4175 */
2160 MIPS_SYS(sys_recvfrom , 6)
2161 MIPS_SYS(sys_recvmsg , 3)
2162 MIPS_SYS(sys_send , 4)
2163 MIPS_SYS(sys_sendmsg , 3)
2164 MIPS_SYS(sys_sendto , 6) /* 4180 */
2165 MIPS_SYS(sys_setsockopt , 5)
2166 MIPS_SYS(sys_shutdown , 2)
2167 MIPS_SYS(sys_socket , 3)
2168 MIPS_SYS(sys_socketpair , 4)
2169 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2170 MIPS_SYS(sys_getresuid , 3)
2171 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2172 MIPS_SYS(sys_poll , 3)
2173 MIPS_SYS(sys_nfsservctl , 3)
2174 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2175 MIPS_SYS(sys_getresgid , 3)
2176 MIPS_SYS(sys_prctl , 5)
2177 MIPS_SYS(sys_rt_sigreturn, 0)
2178 MIPS_SYS(sys_rt_sigaction, 4)
2179 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2180 MIPS_SYS(sys_rt_sigpending, 2)
2181 MIPS_SYS(sys_rt_sigtimedwait, 4)
2182 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2183 MIPS_SYS(sys_rt_sigsuspend, 0)
2184 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2185 MIPS_SYS(sys_pwrite64 , 6)
2186 MIPS_SYS(sys_chown , 3)
2187 MIPS_SYS(sys_getcwd , 2)
2188 MIPS_SYS(sys_capget , 2)
2189 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2190 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2191 MIPS_SYS(sys_sendfile , 4)
2192 MIPS_SYS(sys_ni_syscall , 0)
2193 MIPS_SYS(sys_ni_syscall , 0)
2194 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2195 MIPS_SYS(sys_truncate64 , 4)
2196 MIPS_SYS(sys_ftruncate64 , 4)
2197 MIPS_SYS(sys_stat64 , 2)
2198 MIPS_SYS(sys_lstat64 , 2)
2199 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2200 MIPS_SYS(sys_pivot_root , 2)
2201 MIPS_SYS(sys_mincore , 3)
2202 MIPS_SYS(sys_madvise , 3)
2203 MIPS_SYS(sys_getdents64 , 3)
2204 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2205 MIPS_SYS(sys_ni_syscall , 0)
2206 MIPS_SYS(sys_gettid , 0)
2207 MIPS_SYS(sys_readahead , 5)
2208 MIPS_SYS(sys_setxattr , 5)
2209 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2210 MIPS_SYS(sys_fsetxattr , 5)
2211 MIPS_SYS(sys_getxattr , 4)
2212 MIPS_SYS(sys_lgetxattr , 4)
2213 MIPS_SYS(sys_fgetxattr , 4)
2214 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2215 MIPS_SYS(sys_llistxattr , 3)
2216 MIPS_SYS(sys_flistxattr , 3)
2217 MIPS_SYS(sys_removexattr , 2)
2218 MIPS_SYS(sys_lremovexattr, 2)
2219 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2220 MIPS_SYS(sys_tkill , 2)
2221 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2222 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2223 MIPS_SYS(sys_sched_setaffinity, 3)
2224 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2225 MIPS_SYS(sys_io_setup , 2)
2226 MIPS_SYS(sys_io_destroy , 1)
2227 MIPS_SYS(sys_io_getevents, 5)
2228 MIPS_SYS(sys_io_submit , 3)
2229 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2230 MIPS_SYS(sys_exit_group , 1)
2231 MIPS_SYS(sys_lookup_dcookie, 3)
2232 MIPS_SYS(sys_epoll_create, 1)
2233 MIPS_SYS(sys_epoll_ctl , 4)
2234 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2235 MIPS_SYS(sys_remap_file_pages, 5)
2236 MIPS_SYS(sys_set_tid_address, 1)
2237 MIPS_SYS(sys_restart_syscall, 0)
2238 MIPS_SYS(sys_fadvise64_64, 7)
2239 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2240 MIPS_SYS(sys_fstatfs64 , 2)
2241 MIPS_SYS(sys_timer_create, 3)
2242 MIPS_SYS(sys_timer_settime, 4)
2243 MIPS_SYS(sys_timer_gettime, 2)
2244 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2245 MIPS_SYS(sys_timer_delete, 1)
2246 MIPS_SYS(sys_clock_settime, 2)
2247 MIPS_SYS(sys_clock_gettime, 2)
2248 MIPS_SYS(sys_clock_getres, 2)
2249 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2250 MIPS_SYS(sys_tgkill , 3)
2251 MIPS_SYS(sys_utimes , 2)
2252 MIPS_SYS(sys_mbind , 4)
2253 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2254 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2255 MIPS_SYS(sys_mq_open , 4)
2256 MIPS_SYS(sys_mq_unlink , 1)
2257 MIPS_SYS(sys_mq_timedsend, 5)
2258 MIPS_SYS(sys_mq_timedreceive, 5)
2259 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2260 MIPS_SYS(sys_mq_getsetattr, 3)
2261 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2262 MIPS_SYS(sys_waitid , 4)
2263 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2264 MIPS_SYS(sys_add_key , 5)
388bb21a 2265 MIPS_SYS(sys_request_key, 4)
048f6b4d 2266 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2267 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2268 MIPS_SYS(sys_inotify_init, 0)
2269 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2270 MIPS_SYS(sys_inotify_rm_watch, 2)
2271 MIPS_SYS(sys_migrate_pages, 4)
2272 MIPS_SYS(sys_openat, 4)
2273 MIPS_SYS(sys_mkdirat, 3)
2274 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2275 MIPS_SYS(sys_fchownat, 5)
2276 MIPS_SYS(sys_futimesat, 3)
2277 MIPS_SYS(sys_fstatat64, 4)
2278 MIPS_SYS(sys_unlinkat, 3)
2279 MIPS_SYS(sys_renameat, 4) /* 4295 */
2280 MIPS_SYS(sys_linkat, 5)
2281 MIPS_SYS(sys_symlinkat, 3)
2282 MIPS_SYS(sys_readlinkat, 4)
2283 MIPS_SYS(sys_fchmodat, 3)
2284 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2285 MIPS_SYS(sys_pselect6, 6)
2286 MIPS_SYS(sys_ppoll, 5)
2287 MIPS_SYS(sys_unshare, 1)
b0932e06 2288 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2289 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2290 MIPS_SYS(sys_tee, 4)
2291 MIPS_SYS(sys_vmsplice, 4)
2292 MIPS_SYS(sys_move_pages, 6)
2293 MIPS_SYS(sys_set_robust_list, 2)
2294 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2295 MIPS_SYS(sys_kexec_load, 4)
2296 MIPS_SYS(sys_getcpu, 3)
2297 MIPS_SYS(sys_epoll_pwait, 6)
2298 MIPS_SYS(sys_ioprio_set, 3)
2299 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2300 MIPS_SYS(sys_utimensat, 4)
2301 MIPS_SYS(sys_signalfd, 3)
2302 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2303 MIPS_SYS(sys_eventfd, 1)
2304 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2305 MIPS_SYS(sys_timerfd_create, 2)
2306 MIPS_SYS(sys_timerfd_gettime, 2)
2307 MIPS_SYS(sys_timerfd_settime, 4)
2308 MIPS_SYS(sys_signalfd4, 4)
2309 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2310 MIPS_SYS(sys_epoll_create1, 1)
2311 MIPS_SYS(sys_dup3, 3)
2312 MIPS_SYS(sys_pipe2, 2)
2313 MIPS_SYS(sys_inotify_init1, 1)
2314 MIPS_SYS(sys_preadv, 6) /* 4330 */
2315 MIPS_SYS(sys_pwritev, 6)
2316 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2317 MIPS_SYS(sys_perf_event_open, 5)
2318 MIPS_SYS(sys_accept4, 4)
2319 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2320 MIPS_SYS(sys_fanotify_init, 2)
2321 MIPS_SYS(sys_fanotify_mark, 6)
2322 MIPS_SYS(sys_prlimit64, 4)
2323 MIPS_SYS(sys_name_to_handle_at, 5)
2324 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2325 MIPS_SYS(sys_clock_adjtime, 2)
2326 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2327};
ff4f7382
RH		 2328# undef MIPS_SYS
2329# endif /* O32 */
048f6b4d 2330
590bc601
PB		 2331static int do_store_exclusive(CPUMIPSState *env)
2332{
2333 target_ulong addr;
2334 target_ulong page_addr;
2335 target_ulong val;
2336 int flags;
2337 int segv = 0;
2338 int reg;
2339 int d;
2340
5499b6ff 2341 addr = env->lladdr;
590bc601
PB		 2342 page_addr = addr & TARGET_PAGE_MASK;
2343 start_exclusive();
2344 mmap_lock();
2345 flags = page_get_flags(page_addr);
2346 if ((flags & PAGE_READ) == 0) {
2347 segv = 1;
2348 } else {
2349 reg = env->llreg & 0x1f;
2350 d = (env->llreg & 0x20) != 0;
2351 if (d) {
2352 segv = get_user_s64(val, addr);
2353 } else {
2354 segv = get_user_s32(val, addr);
2355 }
2356 if (!segv) {
2357 if (val != env->llval) {
2358 env->active_tc.gpr[reg] = 0;
2359 } else {
2360 if (d) {
2361 segv = put_user_u64(env->llnewval, addr);
2362 } else {
2363 segv = put_user_u32(env->llnewval, addr);
2364 }
2365 if (!segv) {
2366 env->active_tc.gpr[reg] = 1;
2367 }
2368 }
2369 }
2370 }
5499b6ff 2371 env->lladdr = -1;
590bc601
PB		 2372 if (!segv) {
2373 env->active_tc.PC += 4;
2374 }
2375 mmap_unlock();
2376 end_exclusive();
2377 return segv;
2378}
2379
54b2f42c
MI		 2380/* Break codes */
2381enum {
2382 BRK_OVERFLOW = 6,
2383 BRK_DIVZERO = 7
2384};
2385
2386static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2387 unsigned int code)
2388{
2389 int ret = -1;
2390
2391 switch (code) {
2392 case BRK_OVERFLOW:
2393 case BRK_DIVZERO:
2394 info->si_signo = TARGET_SIGFPE;
2395 info->si_errno = 0;
2396 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2397 queue_signal(env, info->si_signo, &*info);
2398 ret = 0;
2399 break;
2400 default:
b51910ba
PJ		 2401 info->si_signo = TARGET_SIGTRAP;
2402 info->si_errno = 0;
2403 queue_signal(env, info->si_signo, &*info);
2404 ret = 0;
54b2f42c
MI		 2405 break;
2406 }
2407
2408 return ret;
2409}
2410
048f6b4d
FB		 2411void cpu_loop(CPUMIPSState *env)
2412{
0315c31c 2413 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2414 target_siginfo_t info;
ff4f7382
RH		 2415 int trapnr;
2416 abi_long ret;
2417# ifdef TARGET_ABI_MIPSO32
048f6b4d 2418 unsigned int syscall_num;
ff4f7382 2419# endif
048f6b4d
FB		 2420
2421 for(;;) {
0315c31c 2422 cpu_exec_start(cs);
048f6b4d 2423 trapnr = cpu_mips_exec(env);
0315c31c 2424 cpu_exec_end(cs);
048f6b4d
FB		 2425 switch(trapnr) {
2426 case EXCP_SYSCALL:
b5dc7732 2427 env->active_tc.PC += 4;
ff4f7382
RH		 2428# ifdef TARGET_ABI_MIPSO32
2429 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2430 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2431 ret = -TARGET_ENOSYS;
388bb21a
TS		 2432 } else {
2433 int nb_args;
992f48a0
BS		 2434 abi_ulong sp_reg;
2435 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2436
2437 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2438 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2439 switch (nb_args) {
2440 /* these arguments are taken from the stack */
94c19610
ACH		 2441 case 8:
2442 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2443 goto done_syscall;
2444 }
2445 case 7:
2446 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2447 goto done_syscall;
2448 }
2449 case 6:
2450 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2451 goto done_syscall;
2452 }
2453 case 5:
2454 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2455 goto done_syscall;
2456 }
388bb21a
TS		 2457 default:
2458 break;
048f6b4d 2459 }
b5dc7732
TS		 2460 ret = do_syscall(env, env->active_tc.gpr[2],
2461 env->active_tc.gpr[4],
2462 env->active_tc.gpr[5],
2463 env->active_tc.gpr[6],
2464 env->active_tc.gpr[7],
5945cfcb 2465 arg5, arg6, arg7, arg8);
388bb21a 2466 }
94c19610 2467done_syscall:
ff4f7382
RH		 2468# else
2469 ret = do_syscall(env, env->active_tc.gpr[2],
2470 env->active_tc.gpr[4], env->active_tc.gpr[5],
2471 env->active_tc.gpr[6], env->active_tc.gpr[7],
2472 env->active_tc.gpr[8], env->active_tc.gpr[9],
2473 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2474# endif /* O32 */
0b1bcb00
PB		 2475 if (ret == -TARGET_QEMU_ESIGRETURN) {
2476 /* Returning from a successful sigreturn syscall.
2477 Avoid clobbering register state. */
2478 break;
2479 }
ff4f7382 2480 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2481 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2482 ret = -ret;
2483 } else {
b5dc7732 2484 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2485 }
b5dc7732 2486 env->active_tc.gpr[2] = ret;
048f6b4d 2487 break;
ca7c2b1b
TS		 2488 case EXCP_TLBL:
2489 case EXCP_TLBS:
e6e5bd2d
WT		 2490 case EXCP_AdEL:
2491 case EXCP_AdES:
e4474235
PB		 2492 info.si_signo = TARGET_SIGSEGV;
2493 info.si_errno = 0;
2494 /* XXX: check env->error_code */
2495 info.si_code = TARGET_SEGV_MAPERR;
2496 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2497 queue_signal(env, info.si_signo, &info);
2498 break;
6900e84b 2499 case EXCP_CpU:
048f6b4d 2500 case EXCP_RI:
bc1ad2de
FB		 2501 info.si_signo = TARGET_SIGILL;
2502 info.si_errno = 0;
2503 info.si_code = 0;
624f7979 2504 queue_signal(env, info.si_signo, &info);
048f6b4d 2505 break;
106ec879
FB		 2506 case EXCP_INTERRUPT:
2507 /* just indicate that signals should be handled asap */
2508 break;
d08b2a28
PB		 2509 case EXCP_DEBUG:
2510 {
2511 int sig;
2512
db6b81d4 2513 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2514 if (sig)
2515 {
2516 info.si_signo = sig;
2517 info.si_errno = 0;
2518 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2519 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2520 }
2521 }
2522 break;
590bc601
PB		 2523 case EXCP_SC:
2524 if (do_store_exclusive(env)) {
2525 info.si_signo = TARGET_SIGSEGV;
2526 info.si_errno = 0;
2527 info.si_code = TARGET_SEGV_MAPERR;
2528 info._sifields._sigfault._addr = env->active_tc.PC;
2529 queue_signal(env, info.si_signo, &info);
2530 }
2531 break;
853c3240
JL		 2532 case EXCP_DSPDIS:
2533 info.si_signo = TARGET_SIGILL;
2534 info.si_errno = 0;
2535 info.si_code = TARGET_ILL_ILLOPC;
2536 queue_signal(env, info.si_signo, &info);
2537 break;
54b2f42c
MI		 2538 /* The code below was inspired by the MIPS Linux kernel trap
2539 * handling code in arch/mips/kernel/traps.c.
2540 */
2541 case EXCP_BREAK:
2542 {
2543 abi_ulong trap_instr;
2544 unsigned int code;
2545
a0333817
KCY		 2546 if (env->hflags & MIPS_HFLAG_M16) {
2547 if (env->insn_flags & ASE_MICROMIPS) {
2548 /* microMIPS mode */
1308c464
KCY		 2549 ret = get_user_u16(trap_instr, env->active_tc.PC);
2550 if (ret != 0) {
2551 goto error;
2552 }
a0333817 2553
1308c464
KCY		 2554 if ((trap_instr >> 10) == 0x11) {
2555 /* 16-bit instruction */
2556 code = trap_instr & 0xf;
2557 } else {
2558 /* 32-bit instruction */
2559 abi_ulong instr_lo;
2560
2561 ret = get_user_u16(instr_lo,
2562 env->active_tc.PC + 2);
2563 if (ret != 0) {
2564 goto error;
2565 }
2566 trap_instr = (trap_instr << 16) | instr_lo;
2567 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2568 /* Unfortunately, microMIPS also suffers from
2569 the old assembler bug... */
2570 if (code >= (1 << 10)) {
2571 code >>= 10;
2572 }
2573 }
a0333817
KCY		 2574 } else {
2575 /* MIPS16e mode */
2576 ret = get_user_u16(trap_instr, env->active_tc.PC);
2577 if (ret != 0) {
2578 goto error;
2579 }
2580 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2581 }
2582 } else {
2583 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2584 if (ret != 0) {
2585 goto error;
2586 }
54b2f42c 2587
1308c464
KCY		 2588 /* As described in the original Linux kernel code, the
2589 * below checks on 'code' are to work around an old
2590 * assembly bug.
2591 */
2592 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2593 if (code >= (1 << 10)) {
2594 code >>= 10;
2595 }
54b2f42c
MI		 2596 }
2597
2598 if (do_break(env, &info, code) != 0) {
2599 goto error;
2600 }
2601 }
2602 break;
2603 case EXCP_TRAP:
2604 {
2605 abi_ulong trap_instr;
2606 unsigned int code = 0;
2607
a0333817
KCY		 2608 if (env->hflags & MIPS_HFLAG_M16) {
2609 /* microMIPS mode */
2610 abi_ulong instr[2];
2611
2612 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2613 get_user_u16(instr[1], env->active_tc.PC + 2);
2614
2615 trap_instr = (instr[0] << 16) | instr[1];
2616 } else {
2617 ret = get_user_ual(trap_instr, env->active_tc.PC);
2618 }
2619
54b2f42c
MI		 2620 if (ret != 0) {
2621 goto error;
2622 }
2623
2624 /* The immediate versions don't provide a code. */
2625 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2626 if (env->hflags & MIPS_HFLAG_M16) {
2627 /* microMIPS mode */
2628 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2629 } else {
2630 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2631 }
54b2f42c
MI		 2632 }
2633
2634 if (do_break(env, &info, code) != 0) {
2635 goto error;
2636 }
2637 }
2638 break;
048f6b4d 2639 default:
54b2f42c 2640error:
5fafdf24 2641 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2642 trapnr);
878096ee 2643 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2644 abort();
2645 }
2646 process_pending_signals(env);
2647 }
2648}
2649#endif
2650
d962783e
JL		 2651#ifdef TARGET_OPENRISC
2652
2653void cpu_loop(CPUOpenRISCState *env)
2654{
878096ee 2655 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2656 int trapnr, gdbsig;
2657
2658 for (;;) {
2659 trapnr = cpu_exec(env);
2660 gdbsig = 0;
2661
2662 switch (trapnr) {
2663 case EXCP_RESET:
2664 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2665 exit(1);
2666 break;
2667 case EXCP_BUSERR:
2668 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2669 gdbsig = SIGBUS;
2670 break;
2671 case EXCP_DPF:
2672 case EXCP_IPF:
878096ee 2673 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2674 gdbsig = TARGET_SIGSEGV;
2675 break;
2676 case EXCP_TICK:
2677 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2678 break;
2679 case EXCP_ALIGN:
2680 qemu_log("\nAlignment pc is %#x\n", env->pc);
2681 gdbsig = SIGBUS;
2682 break;
2683 case EXCP_ILLEGAL:
2684 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2685 gdbsig = SIGILL;
2686 break;
2687 case EXCP_INT:
2688 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2689 break;
2690 case EXCP_DTLBMISS:
2691 case EXCP_ITLBMISS:
2692 qemu_log("\nTLB miss\n");
2693 break;
2694 case EXCP_RANGE:
2695 qemu_log("\nRange\n");
2696 gdbsig = SIGSEGV;
2697 break;
2698 case EXCP_SYSCALL:
2699 env->pc += 4; /* 0xc00; */
2700 env->gpr[11] = do_syscall(env,
2701 env->gpr[11], /* return value */
2702 env->gpr[3], /* r3 - r7 are params */
2703 env->gpr[4],
2704 env->gpr[5],
2705 env->gpr[6],
2706 env->gpr[7],
2707 env->gpr[8], 0, 0);
2708 break;
2709 case EXCP_FPE:
2710 qemu_log("\nFloating point error\n");
2711 break;
2712 case EXCP_TRAP:
2713 qemu_log("\nTrap\n");
2714 gdbsig = SIGTRAP;
2715 break;
2716 case EXCP_NR:
2717 qemu_log("\nNR\n");
2718 break;
2719 default:
2720 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2721 trapnr);
878096ee 2722 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2723 gdbsig = TARGET_SIGILL;
2724 break;
2725 }
2726 if (gdbsig) {
db6b81d4 2727 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2728 if (gdbsig != TARGET_SIGTRAP) {
2729 exit(1);
2730 }
2731 }
2732
2733 process_pending_signals(env);
2734 }
2735}
2736
2737#endif /* TARGET_OPENRISC */
2738
fdf9b3e8 2739#ifdef TARGET_SH4
05390248 2740void cpu_loop(CPUSH4State *env)
fdf9b3e8 2741{
878096ee 2742 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2743 int trapnr, ret;
c227f099 2744 target_siginfo_t info;
3b46e624 2745
fdf9b3e8
FB		 2746 while (1) {
2747 trapnr = cpu_sh4_exec (env);
3b46e624 2748
fdf9b3e8
FB		 2749 switch (trapnr) {
2750 case 0x160:
0b6d3ae0 2751 env->pc += 2;
5fafdf24
TS		 2752 ret = do_syscall(env,
2753 env->gregs[3],
2754 env->gregs[4],
2755 env->gregs[5],
2756 env->gregs[6],
2757 env->gregs[7],
2758 env->gregs[0],
5945cfcb
PM		 2759 env->gregs[1],
2760 0, 0);
9c2a9ea1 2761 env->gregs[0] = ret;
fdf9b3e8 2762 break;
c3b5bc8a
TS		 2763 case EXCP_INTERRUPT:
2764 /* just indicate that signals should be handled asap */
2765 break;
355fb23d
PB		 2766 case EXCP_DEBUG:
2767 {
2768 int sig;
2769
db6b81d4 2770 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2771 if (sig)
2772 {
2773 info.si_signo = sig;
2774 info.si_errno = 0;
2775 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2776 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2777 }
2778 }
2779 break;
c3b5bc8a
TS		 2780 case 0xa0:
2781 case 0xc0:
2782 info.si_signo = SIGSEGV;
2783 info.si_errno = 0;
2784 info.si_code = TARGET_SEGV_MAPERR;
2785 info._sifields._sigfault._addr = env->tea;
624f7979 2786 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2787 break;
2788
fdf9b3e8
FB		 2789 default:
2790 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2791 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2792 exit (1);
2793 }
2794 process_pending_signals (env);
2795 }
2796}
2797#endif
2798
48733d19 2799#ifdef TARGET_CRIS
05390248 2800void cpu_loop(CPUCRISState *env)
48733d19 2801{
878096ee 2802 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2803 int trapnr, ret;
c227f099 2804 target_siginfo_t info;
48733d19
TS		 2805
2806 while (1) {
2807 trapnr = cpu_cris_exec (env);
2808 switch (trapnr) {
2809 case 0xaa:
2810 {
2811 info.si_signo = SIGSEGV;
2812 info.si_errno = 0;
2813 /* XXX: check env->error_code */
2814 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2815 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2816 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2817 }
2818 break;
b6d3abda
EI		 2819 case EXCP_INTERRUPT:
2820 /* just indicate that signals should be handled asap */
2821 break;
48733d19
TS		 2822 case EXCP_BREAK:
2823 ret = do_syscall(env,
2824 env->regs[9],
2825 env->regs[10],
2826 env->regs[11],
2827 env->regs[12],
2828 env->regs[13],
2829 env->pregs[7],
5945cfcb
PM		 2830 env->pregs[11],
2831 0, 0);
48733d19 2832 env->regs[10] = ret;
48733d19
TS		 2833 break;
2834 case EXCP_DEBUG:
2835 {
2836 int sig;
2837
db6b81d4 2838 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2839 if (sig)
2840 {
2841 info.si_signo = sig;
2842 info.si_errno = 0;
2843 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2844 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2845 }
2846 }
2847 break;
2848 default:
2849 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2850 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2851 exit (1);
2852 }
2853 process_pending_signals (env);
2854 }
2855}
2856#endif
2857
b779e29e 2858#ifdef TARGET_MICROBLAZE
05390248 2859void cpu_loop(CPUMBState *env)
b779e29e 2860{
878096ee 2861 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2862 int trapnr, ret;
c227f099 2863 target_siginfo_t info;
b779e29e
EI		 2864
2865 while (1) {
2866 trapnr = cpu_mb_exec (env);
2867 switch (trapnr) {
2868 case 0xaa:
2869 {
2870 info.si_signo = SIGSEGV;
2871 info.si_errno = 0;
2872 /* XXX: check env->error_code */
2873 info.si_code = TARGET_SEGV_MAPERR;
2874 info._sifields._sigfault._addr = 0;
2875 queue_signal(env, info.si_signo, &info);
2876 }
2877 break;
2878 case EXCP_INTERRUPT:
2879 /* just indicate that signals should be handled asap */
2880 break;
2881 case EXCP_BREAK:
2882 /* Return address is 4 bytes after the call. */
2883 env->regs[14] += 4;
d7dce494 2884 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2885 ret = do_syscall(env,
2886 env->regs[12],
2887 env->regs[5],
2888 env->regs[6],
2889 env->regs[7],
2890 env->regs[8],
2891 env->regs[9],
5945cfcb
PM		 2892 env->regs[10],
2893 0, 0);
b779e29e 2894 env->regs[3] = ret;
b779e29e 2895 break;
b76da7e3
EI		 2896 case EXCP_HW_EXCP:
2897 env->regs[17] = env->sregs[SR_PC] + 4;
2898 if (env->iflags & D_FLAG) {
2899 env->sregs[SR_ESR] |= 1 << 12;
2900 env->sregs[SR_PC] -= 4;
b4916d7b 2901 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2902 }
2903
2904 env->iflags &= ~(IMM_FLAG | D_FLAG);
2905
2906 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2907 case ESR_EC_DIVZERO:
2908 info.si_signo = SIGFPE;
2909 info.si_errno = 0;
2910 info.si_code = TARGET_FPE_FLTDIV;
2911 info._sifields._sigfault._addr = 0;
2912 queue_signal(env, info.si_signo, &info);
2913 break;
b76da7e3
EI		 2914 case ESR_EC_FPU:
2915 info.si_signo = SIGFPE;
2916 info.si_errno = 0;
2917 if (env->sregs[SR_FSR] & FSR_IO) {
2918 info.si_code = TARGET_FPE_FLTINV;
2919 }
2920 if (env->sregs[SR_FSR] & FSR_DZ) {
2921 info.si_code = TARGET_FPE_FLTDIV;
2922 }
2923 info._sifields._sigfault._addr = 0;
2924 queue_signal(env, info.si_signo, &info);
2925 break;
2926 default:
2927 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2928 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2929 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2930 exit (1);
2931 break;
2932 }
2933 break;
b779e29e
EI		 2934 case EXCP_DEBUG:
2935 {
2936 int sig;
2937
db6b81d4 2938 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2939 if (sig)
2940 {
2941 info.si_signo = sig;
2942 info.si_errno = 0;
2943 info.si_code = TARGET_TRAP_BRKPT;
2944 queue_signal(env, info.si_signo, &info);
2945 }
2946 }
2947 break;
2948 default:
2949 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2950 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2951 exit (1);
2952 }
2953 process_pending_signals (env);
2954 }
2955}
2956#endif
2957
e6e5906b
PB		 2958#ifdef TARGET_M68K
2959
2960void cpu_loop(CPUM68KState *env)
2961{
878096ee 2962 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2963 int trapnr;
2964 unsigned int n;
c227f099 2965 target_siginfo_t info;
0429a971 2966 TaskState *ts = cs->opaque;
3b46e624 2967
e6e5906b
PB		 2968 for(;;) {
2969 trapnr = cpu_m68k_exec(env);
2970 switch(trapnr) {
2971 case EXCP_ILLEGAL:
2972 {
2973 if (ts->sim_syscalls) {
2974 uint16_t nr;
2975 nr = lduw(env->pc + 2);
2976 env->pc += 4;
2977 do_m68k_simcall(env, nr);
2978 } else {
2979 goto do_sigill;
2980 }
2981 }
2982 break;
a87295e8 2983 case EXCP_HALT_INSN:
e6e5906b 2984 /* Semihosing syscall. */
a87295e8 2985 env->pc += 4;
e6e5906b
PB		 2986 do_m68k_semihosting(env, env->dregs[0]);
2987 break;
2988 case EXCP_LINEA:
2989 case EXCP_LINEF:
2990 case EXCP_UNSUPPORTED:
2991 do_sigill:
2992 info.si_signo = SIGILL;
2993 info.si_errno = 0;
2994 info.si_code = TARGET_ILL_ILLOPN;
2995 info._sifields._sigfault._addr = env->pc;
624f7979 2996 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2997 break;
2998 case EXCP_TRAP0:
2999 {
3000 ts->sim_syscalls = 0;
3001 n = env->dregs[0];
3002 env->pc += 2;
5fafdf24
TS		 3003 env->dregs[0] = do_syscall(env,
3004 n,
e6e5906b
PB		 3005 env->dregs[1],
3006 env->dregs[2],
3007 env->dregs[3],
3008 env->dregs[4],
3009 env->dregs[5],
5945cfcb
PM		 3010 env->aregs[0],
3011 0, 0);
e6e5906b
PB		 3012 }
3013 break;
3014 case EXCP_INTERRUPT:
3015 /* just indicate that signals should be handled asap */
3016 break;
3017 case EXCP_ACCESS:
3018 {
3019 info.si_signo = SIGSEGV;
3020 info.si_errno = 0;
3021 /* XXX: check env->error_code */
3022 info.si_code = TARGET_SEGV_MAPERR;
3023 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3024 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3025 }
3026 break;
3027 case EXCP_DEBUG:
3028 {
3029 int sig;
3030
db6b81d4 3031 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3032 if (sig)
3033 {
3034 info.si_signo = sig;
3035 info.si_errno = 0;
3036 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3037 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3038 }
3039 }
3040 break;
3041 default:
5fafdf24 3042 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3043 trapnr);
878096ee 3044 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3045 abort();
3046 }
3047 process_pending_signals(env);
3048 }
3049}
3050#endif /* TARGET_M68K */
3051
7a3148a9 3052#ifdef TARGET_ALPHA
6910b8f6
RH		 3053static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3054{
3055 target_ulong addr, val, tmp;
3056 target_siginfo_t info;
3057 int ret = 0;
3058
3059 addr = env->lock_addr;
3060 tmp = env->lock_st_addr;
3061 env->lock_addr = -1;
3062 env->lock_st_addr = 0;
3063
3064 start_exclusive();
3065 mmap_lock();
3066
3067 if (addr == tmp) {
3068 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3069 goto do_sigsegv;
3070 }
3071
3072 if (val == env->lock_value) {
3073 tmp = env->ir[reg];
3074 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3075 goto do_sigsegv;
3076 }
3077 ret = 1;
3078 }
3079 }
3080 env->ir[reg] = ret;
3081 env->pc += 4;
3082
3083 mmap_unlock();
3084 end_exclusive();
3085 return;
3086
3087 do_sigsegv:
3088 mmap_unlock();
3089 end_exclusive();
3090
3091 info.si_signo = TARGET_SIGSEGV;
3092 info.si_errno = 0;
3093 info.si_code = TARGET_SEGV_MAPERR;
3094 info._sifields._sigfault._addr = addr;
3095 queue_signal(env, TARGET_SIGSEGV, &info);
3096}
3097
05390248 3098void cpu_loop(CPUAlphaState *env)
7a3148a9 3099{
878096ee 3100 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3101 int trapnr;
c227f099 3102 target_siginfo_t info;
6049f4f8 3103 abi_long sysret;
3b46e624 3104
7a3148a9
JM		 3105 while (1) {
3106 trapnr = cpu_alpha_exec (env);
3b46e624 3107
ac316ca4
RH		 3108 /* All of the traps imply a transition through PALcode, which
3109 implies an REI instruction has been executed. Which means
3110 that the intr_flag should be cleared. */
3111 env->intr_flag = 0;
3112
7a3148a9
JM		 3113 switch (trapnr) {
3114 case EXCP_RESET:
3115 fprintf(stderr, "Reset requested. Exit\n");
3116 exit(1);
3117 break;
3118 case EXCP_MCHK:
3119 fprintf(stderr, "Machine check exception. Exit\n");
3120 exit(1);
3121 break;
07b6c13b
RH		 3122 case EXCP_SMP_INTERRUPT:
3123 case EXCP_CLK_INTERRUPT:
3124 case EXCP_DEV_INTERRUPT:
5fafdf24 3125 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3126 exit(1);
3127 break;
07b6c13b 3128 case EXCP_MMFAULT:
6910b8f6 3129 env->lock_addr = -1;
6049f4f8
RH		 3130 info.si_signo = TARGET_SIGSEGV;
3131 info.si_errno = 0;
129d8aa5 3132 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3133 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3134 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3135 queue_signal(env, info.si_signo, &info);
7a3148a9 3136 break;
7a3148a9 3137 case EXCP_UNALIGN:
6910b8f6 3138 env->lock_addr = -1;
6049f4f8
RH		 3139 info.si_signo = TARGET_SIGBUS;
3140 info.si_errno = 0;
3141 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3142 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3143 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3144 break;
3145 case EXCP_OPCDEC:
6049f4f8 3146 do_sigill:
6910b8f6 3147 env->lock_addr = -1;
6049f4f8
RH		 3148 info.si_signo = TARGET_SIGILL;
3149 info.si_errno = 0;
3150 info.si_code = TARGET_ILL_ILLOPC;
3151 info._sifields._sigfault._addr = env->pc;
3152 queue_signal(env, info.si_signo, &info);
7a3148a9 3153 break;
07b6c13b
RH		 3154 case EXCP_ARITH:
3155 env->lock_addr = -1;
3156 info.si_signo = TARGET_SIGFPE;
3157 info.si_errno = 0;
3158 info.si_code = TARGET_FPE_FLTINV;
3159 info._sifields._sigfault._addr = env->pc;
3160 queue_signal(env, info.si_signo, &info);
3161 break;
7a3148a9 3162 case EXCP_FEN:
6049f4f8 3163 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3164 break;
07b6c13b 3165 case EXCP_CALL_PAL:
6910b8f6 3166 env->lock_addr = -1;
07b6c13b 3167 switch (env->error_code) {
6049f4f8
RH		 3168 case 0x80:
3169 /* BPT */
3170 info.si_signo = TARGET_SIGTRAP;
3171 info.si_errno = 0;
3172 info.si_code = TARGET_TRAP_BRKPT;
3173 info._sifields._sigfault._addr = env->pc;
3174 queue_signal(env, info.si_signo, &info);
3175 break;
3176 case 0x81:
3177 /* BUGCHK */
3178 info.si_signo = TARGET_SIGTRAP;
3179 info.si_errno = 0;
3180 info.si_code = 0;
3181 info._sifields._sigfault._addr = env->pc;
3182 queue_signal(env, info.si_signo, &info);
3183 break;
3184 case 0x83:
3185 /* CALLSYS */
3186 trapnr = env->ir[IR_V0];
3187 sysret = do_syscall(env, trapnr,
3188 env->ir[IR_A0], env->ir[IR_A1],
3189 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3190 env->ir[IR_A4], env->ir[IR_A5],
3191 0, 0);
a5b3b13b
RH		 3192 if (trapnr == TARGET_NR_sigreturn
3193 || trapnr == TARGET_NR_rt_sigreturn) {
3194 break;
3195 }
3196 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3197 to how this is handled internal to Linux kernel.
3198 (Ab)use trapnr temporarily as boolean indicating error. */
3199 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3200 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3201 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3202 break;
3203 case 0x86:
3204 /* IMB */
3205 /* ??? We can probably elide the code using page_unprotect
3206 that is checking for self-modifying code. Instead we
3207 could simply call tb_flush here. Until we work out the
3208 changes required to turn off the extra write protection,
3209 this can be a no-op. */
3210 break;
3211 case 0x9E:
3212 /* RDUNIQUE */
3213 /* Handled in the translator for usermode. */
3214 abort();
3215 case 0x9F:
3216 /* WRUNIQUE */
3217 /* Handled in the translator for usermode. */
3218 abort();
3219 case 0xAA:
3220 /* GENTRAP */
3221 info.si_signo = TARGET_SIGFPE;
3222 switch (env->ir[IR_A0]) {
3223 case TARGET_GEN_INTOVF:
3224 info.si_code = TARGET_FPE_INTOVF;
3225 break;
3226 case TARGET_GEN_INTDIV:
3227 info.si_code = TARGET_FPE_INTDIV;
3228 break;
3229 case TARGET_GEN_FLTOVF:
3230 info.si_code = TARGET_FPE_FLTOVF;
3231 break;
3232 case TARGET_GEN_FLTUND:
3233 info.si_code = TARGET_FPE_FLTUND;
3234 break;
3235 case TARGET_GEN_FLTINV:
3236 info.si_code = TARGET_FPE_FLTINV;
3237 break;
3238 case TARGET_GEN_FLTINE:
3239 info.si_code = TARGET_FPE_FLTRES;
3240 break;
3241 case TARGET_GEN_ROPRAND:
3242 info.si_code = 0;
3243 break;
3244 default:
3245 info.si_signo = TARGET_SIGTRAP;
3246 info.si_code = 0;
3247 break;
3248 }
3249 info.si_errno = 0;
3250 info._sifields._sigfault._addr = env->pc;
3251 queue_signal(env, info.si_signo, &info);
3252 break;
3253 default:
3254 goto do_sigill;
3255 }
7a3148a9 3256 break;
7a3148a9 3257 case EXCP_DEBUG:
db6b81d4 3258 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3259 if (info.si_signo) {
6910b8f6 3260 env->lock_addr = -1;
6049f4f8
RH		 3261 info.si_errno = 0;
3262 info.si_code = TARGET_TRAP_BRKPT;
3263 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3264 }
3265 break;
6910b8f6
RH		 3266 case EXCP_STL_C:
3267 case EXCP_STQ_C:
3268 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3269 break;
d0f20495
RH		 3270 case EXCP_INTERRUPT:
3271 /* Just indicate that signals should be handled asap. */
3272 break;
7a3148a9
JM		 3273 default:
3274 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3275 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3276 exit (1);
3277 }
3278 process_pending_signals (env);
3279 }
3280}
3281#endif /* TARGET_ALPHA */
3282
a4c075f1
UH		 3283#ifdef TARGET_S390X
3284void cpu_loop(CPUS390XState *env)
3285{
878096ee 3286 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3287 int trapnr, n, sig;
a4c075f1 3288 target_siginfo_t info;
d5a103cd 3289 target_ulong addr;
a4c075f1
UH		 3290
3291 while (1) {
d5a103cd 3292 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3293 switch (trapnr) {
3294 case EXCP_INTERRUPT:
d5a103cd 3295 /* Just indicate that signals should be handled asap. */
a4c075f1 3296 break;
a4c075f1 3297
d5a103cd
RH		 3298 case EXCP_SVC:
3299 n = env->int_svc_code;
3300 if (!n) {
3301 /* syscalls > 255 */
3302 n = env->regs[1];
a4c075f1 3303 }
d5a103cd
RH		 3304 env->psw.addr += env->int_svc_ilen;
3305 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3306 env->regs[4], env->regs[5],
3307 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3308 break;
d5a103cd
RH		 3309
3310 case EXCP_DEBUG:
db6b81d4 3311 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3312 if (sig) {
3313 n = TARGET_TRAP_BRKPT;
3314 goto do_signal_pc;
a4c075f1
UH		 3315 }
3316 break;
d5a103cd
RH		 3317 case EXCP_PGM:
3318 n = env->int_pgm_code;
3319 switch (n) {
3320 case PGM_OPERATION:
3321 case PGM_PRIVILEGED:
3322 sig = SIGILL;
3323 n = TARGET_ILL_ILLOPC;
3324 goto do_signal_pc;
3325 case PGM_PROTECTION:
3326 case PGM_ADDRESSING:
3327 sig = SIGSEGV;
a4c075f1 3328 /* XXX: check env->error_code */
d5a103cd
RH		 3329 n = TARGET_SEGV_MAPERR;
3330 addr = env->__excp_addr;
3331 goto do_signal;
3332 case PGM_EXECUTE:
3333 case PGM_SPECIFICATION:
3334 case PGM_SPECIAL_OP:
3335 case PGM_OPERAND:
3336 do_sigill_opn:
3337 sig = SIGILL;
3338 n = TARGET_ILL_ILLOPN;
3339 goto do_signal_pc;
3340
3341 case PGM_FIXPT_OVERFLOW:
3342 sig = SIGFPE;
3343 n = TARGET_FPE_INTOVF;
3344 goto do_signal_pc;
3345 case PGM_FIXPT_DIVIDE:
3346 sig = SIGFPE;
3347 n = TARGET_FPE_INTDIV;
3348 goto do_signal_pc;
3349
3350 case PGM_DATA:
3351 n = (env->fpc >> 8) & 0xff;
3352 if (n == 0xff) {
3353 /* compare-and-trap */
3354 goto do_sigill_opn;
3355 } else {
3356 /* An IEEE exception, simulated or otherwise. */
3357 if (n & 0x80) {
3358 n = TARGET_FPE_FLTINV;
3359 } else if (n & 0x40) {
3360 n = TARGET_FPE_FLTDIV;
3361 } else if (n & 0x20) {
3362 n = TARGET_FPE_FLTOVF;
3363 } else if (n & 0x10) {
3364 n = TARGET_FPE_FLTUND;
3365 } else if (n & 0x08) {
3366 n = TARGET_FPE_FLTRES;
3367 } else {
3368 /* ??? Quantum exception; BFP, DFP error. */
3369 goto do_sigill_opn;
3370 }
3371 sig = SIGFPE;
3372 goto do_signal_pc;
3373 }
3374
3375 default:
3376 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3377 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3378 exit(1);
a4c075f1
UH		 3379 }
3380 break;
d5a103cd
RH		 3381
3382 do_signal_pc:
3383 addr = env->psw.addr;
3384 do_signal:
3385 info.si_signo = sig;
3386 info.si_errno = 0;
3387 info.si_code = n;
3388 info._sifields._sigfault._addr = addr;
3389 queue_signal(env, info.si_signo, &info);
a4c075f1 3390 break;
d5a103cd 3391
a4c075f1 3392 default:
d5a103cd 3393 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3394 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3395 exit(1);
a4c075f1
UH		 3396 }
3397 process_pending_signals (env);
3398 }
3399}
3400
3401#endif /* TARGET_S390X */
3402
a2247f8e 3403THREAD CPUState *thread_cpu;
59faf6d6 3404
edf8e2af
MW		 3405void task_settid(TaskState *ts)
3406{
3407 if (ts->ts_tid == 0) {
edf8e2af 3408 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3409 }
3410}
3411
3412void stop_all_tasks(void)
3413{
3414 /*
3415 * We trust that when using NPTL, start_exclusive()
3416 * handles thread stopping correctly.
3417 */
3418 start_exclusive();
3419}
3420
c3a92833 3421/* Assumes contents are already zeroed. */
624f7979
PB		 3422void init_task_state(TaskState *ts)
3423{
3424 int i;
3425
624f7979
PB		 3426 ts->used = 1;
3427 ts->first_free = ts->sigqueue_table;
3428 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3429 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3430 }
3431 ts->sigqueue_table[i].next = NULL;
3432}
fc9c5412 3433
30ba0ee5
AF		 3434CPUArchState *cpu_copy(CPUArchState *env)
3435{
ff4700b0 3436 CPUState *cpu = ENV_GET_CPU(env);
51fb256a 3437 CPUArchState *new_env = cpu_init(cpu_model);
75a34036 3438 CPUState *new_cpu = ENV_GET_CPU(new_env);
30ba0ee5
AF		 3439#if defined(TARGET_HAS_ICE)
3440 CPUBreakpoint *bp;
3441 CPUWatchpoint *wp;
3442#endif
3443
3444 /* Reset non arch specific state */
75a34036 3445 cpu_reset(new_cpu);
30ba0ee5
AF		 3446
3447 memcpy(new_env, env, sizeof(CPUArchState));
3448
3449 /* Clone all break/watchpoints.
3450 Note: Once we support ptrace with hw-debug register access, make sure
3451 BP_CPU break/watchpoints are handled correctly on clone. */
f0c3c505 3452 QTAILQ_INIT(&cpu->breakpoints);
ff4700b0 3453 QTAILQ_INIT(&cpu->watchpoints);
30ba0ee5 3454#if defined(TARGET_HAS_ICE)
f0c3c505 3455 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3456 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3457 }
ff4700b0 3458 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3459 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5
AF		 3460 }
3461#endif
3462
3463 return new_env;
3464}
3465
fc9c5412
JS		 3466static void handle_arg_help(const char *arg)
3467{
3468 usage();
3469}
3470
3471static void handle_arg_log(const char *arg)
3472{
3473 int mask;
fc9c5412 3474
4fde1eba 3475 mask = qemu_str_to_log_mask(arg);
fc9c5412 3476 if (!mask) {
59a6fa6e 3477 qemu_print_log_usage(stdout);
fc9c5412
JS		 3478 exit(1);
3479 }
24537a01 3480 qemu_set_log(mask);
fc9c5412
JS		 3481}
3482
50171d42
CWR		 3483static void handle_arg_log_filename(const char *arg)
3484{
9a7e5424 3485 qemu_set_log_filename(arg);
50171d42
CWR		 3486}
3487
fc9c5412
JS		 3488static void handle_arg_set_env(const char *arg)
3489{
3490 char *r, *p, *token;
3491 r = p = strdup(arg);
3492 while ((token = strsep(&p, ",")) != NULL) {
3493 if (envlist_setenv(envlist, token) != 0) {
3494 usage();
3495 }
3496 }
3497 free(r);
3498}
3499
3500static void handle_arg_unset_env(const char *arg)
3501{
3502 char *r, *p, *token;
3503 r = p = strdup(arg);
3504 while ((token = strsep(&p, ",")) != NULL) {
3505 if (envlist_unsetenv(envlist, token) != 0) {
3506 usage();
3507 }
3508 }
3509 free(r);
3510}
3511
3512static void handle_arg_argv0(const char *arg)
3513{
3514 argv0 = strdup(arg);
3515}
3516
3517static void handle_arg_stack_size(const char *arg)
3518{
3519 char *p;
3520 guest_stack_size = strtoul(arg, &p, 0);
3521 if (guest_stack_size == 0) {
3522 usage();
3523 }
3524
3525 if (*p == 'M') {
3526 guest_stack_size *= 1024 * 1024;
3527 } else if (*p == 'k' || *p == 'K') {
3528 guest_stack_size *= 1024;
3529 }
3530}
3531
3532static void handle_arg_ld_prefix(const char *arg)
3533{
3534 interp_prefix = strdup(arg);
3535}
3536
3537static void handle_arg_pagesize(const char *arg)
3538{
3539 qemu_host_page_size = atoi(arg);
3540 if (qemu_host_page_size == 0 ||
3541 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3542 fprintf(stderr, "page size must be a power of two\n");
3543 exit(1);
3544 }
3545}
3546
c5e4a5a9
MR		 3547static void handle_arg_randseed(const char *arg)
3548{
3549 unsigned long long seed;
3550
3551 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3552 fprintf(stderr, "Invalid seed number: %s\n", arg);
3553 exit(1);
3554 }
3555 srand(seed);
3556}
3557
fc9c5412
JS		 3558static void handle_arg_gdb(const char *arg)
3559{
3560 gdbstub_port = atoi(arg);
3561}
3562
3563static void handle_arg_uname(const char *arg)
3564{
3565 qemu_uname_release = strdup(arg);
3566}
3567
3568static void handle_arg_cpu(const char *arg)
3569{
3570 cpu_model = strdup(arg);
c8057f95 3571 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3572 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3573#if defined(cpu_list)
3574 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3575#endif
3576 exit(1);
3577 }
3578}
3579
3580#if defined(CONFIG_USE_GUEST_BASE)
3581static void handle_arg_guest_base(const char *arg)
3582{
3583 guest_base = strtol(arg, NULL, 0);
3584 have_guest_base = 1;
3585}
3586
3587static void handle_arg_reserved_va(const char *arg)
3588{
3589 char *p;
3590 int shift = 0;
3591 reserved_va = strtoul(arg, &p, 0);
3592 switch (*p) {
3593 case 'k':
3594 case 'K':
3595 shift = 10;
3596 break;
3597 case 'M':
3598 shift = 20;
3599 break;
3600 case 'G':
3601 shift = 30;
3602 break;
3603 }
3604 if (shift) {
3605 unsigned long unshifted = reserved_va;
3606 p++;
3607 reserved_va <<= shift;
3608 if (((reserved_va >> shift) != unshifted)
3609#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3610 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3611#endif
3612 ) {
3613 fprintf(stderr, "Reserved virtual address too big\n");
3614 exit(1);
3615 }
3616 }
3617 if (*p) {
3618 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3619 exit(1);
3620 }
3621}
3622#endif
3623
3624static void handle_arg_singlestep(const char *arg)
3625{
3626 singlestep = 1;
3627}
3628
3629static void handle_arg_strace(const char *arg)
3630{
3631 do_strace = 1;
3632}
3633
3634static void handle_arg_version(const char *arg)
3635{
2e59915d 3636 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3637 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3638 exit(0);
fc9c5412
JS		 3639}
3640
3641struct qemu_argument {
3642 const char *argv;
3643 const char *env;
3644 bool has_arg;
3645 void (*handle_opt)(const char *arg);
3646 const char *example;
3647 const char *help;
3648};
3649
42644cee 3650static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3651 {"h", "", false, handle_arg_help,
3652 "", "print this help"},
3653 {"g", "QEMU_GDB", true, handle_arg_gdb,
3654 "port", "wait gdb connection to 'port'"},
3655 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3656 "path", "set the elf interpreter prefix to 'path'"},
3657 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3658 "size", "set the stack size to 'size' bytes"},
3659 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3660 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3661 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3662 "var=value", "sets targets environment variable (see below)"},
3663 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3664 "var", "unsets targets environment variable (see below)"},
3665 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3666 "argv0", "forces target process argv[0] to be 'argv0'"},
3667 {"r", "QEMU_UNAME", true, handle_arg_uname,
3668 "uname", "set qemu uname release string to 'uname'"},
3669#if defined(CONFIG_USE_GUEST_BASE)
3670 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3671 "address", "set guest_base address to 'address'"},
3672 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3673 "size", "reserve 'size' bytes for guest virtual address space"},
3674#endif
3675 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3676 "item[,...]", "enable logging of specified items "
3677 "(use '-d help' for a list of items)"},
50171d42 3678 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3679 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3680 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3681 "pagesize", "set the host page size to 'pagesize'"},
3682 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3683 "", "run in singlestep mode"},
3684 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3685 "", "log system calls"},
c5e4a5a9
MR		 3686 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3687 "", "Seed for pseudo-random number generator"},
fc9c5412 3688 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3689 "", "display version information and exit"},
fc9c5412
JS		 3690 {NULL, NULL, false, NULL, NULL, NULL}
3691};
3692
3693static void usage(void)
3694{
42644cee 3695 const struct qemu_argument *arginfo;
fc9c5412
JS		 3696 int maxarglen;
3697 int maxenvlen;
3698
2e59915d
PB		 3699 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3700 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3701 "\n"
3702 "Options and associated environment variables:\n"
3703 "\n");
3704
63ec54d7
PM		 3705 /* Calculate column widths. We must always have at least enough space
3706 * for the column header.
3707 */
3708 maxarglen = strlen("Argument");
3709 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3710
3711 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3712 int arglen = strlen(arginfo->argv);
3713 if (arginfo->has_arg) {
3714 arglen += strlen(arginfo->example) + 1;
3715 }
fc9c5412
JS		 3716 if (strlen(arginfo->env) > maxenvlen) {
3717 maxenvlen = strlen(arginfo->env);
3718 }
63ec54d7
PM		 3719 if (arglen > maxarglen) {
3720 maxarglen = arglen;
fc9c5412
JS		 3721 }
3722 }
3723
63ec54d7
PM		 3724 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3725 maxenvlen, "Env-variable");
fc9c5412
JS		 3726
3727 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3728 if (arginfo->has_arg) {
3729 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3730 (int)(maxarglen - strlen(arginfo->argv) - 1),
3731 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3732 } else {
63ec54d7 3733 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3734 maxenvlen, arginfo->env,
3735 arginfo->help);
3736 }
3737 }
3738
3739 printf("\n"
3740 "Defaults:\n"
3741 "QEMU_LD_PREFIX = %s\n"
989b697d 3742 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3743 interp_prefix,
989b697d 3744 guest_stack_size);
fc9c5412
JS		 3745
3746 printf("\n"
3747 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3748 "QEMU_UNSET_ENV environment variables to set and unset\n"
3749 "environment variables for the target process.\n"
3750 "It is possible to provide several variables by separating them\n"
3751 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3752 "provide the -E and -U options multiple times.\n"
3753 "The following lines are equivalent:\n"
3754 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3755 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3756 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3757 "Note that if you provide several changes to a single variable\n"
3758 "the last change will stay in effect.\n");
3759
3760 exit(1);
3761}
3762
3763static int parse_args(int argc, char **argv)
3764{
3765 const char *r;
3766 int optind;
42644cee 3767 const struct qemu_argument *arginfo;
fc9c5412
JS		 3768
3769 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3770 if (arginfo->env == NULL) {
3771 continue;
3772 }
3773
3774 r = getenv(arginfo->env);
3775 if (r != NULL) {
3776 arginfo->handle_opt(r);
3777 }
3778 }
3779
3780 optind = 1;
3781 for (;;) {
3782 if (optind >= argc) {
3783 break;
3784 }
3785 r = argv[optind];
3786 if (r[0] != '-') {
3787 break;
3788 }
3789 optind++;
3790 r++;
3791 if (!strcmp(r, "-")) {
3792 break;
3793 }
3794
3795 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3796 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3797 if (arginfo->has_arg) {
1386d4c0
PM		 3798 if (optind >= argc) {
3799 usage();
3800 }
3801 arginfo->handle_opt(argv[optind]);
fc9c5412 3802 optind++;
1386d4c0
PM		 3803 } else {
3804 arginfo->handle_opt(NULL);
fc9c5412 3805 }
fc9c5412
JS		 3806 break;
3807 }
3808 }
3809
3810 /* no option matched the current argv */
3811 if (arginfo->handle_opt == NULL) {
3812 usage();
3813 }
3814 }
3815
3816 if (optind >= argc) {
3817 usage();
3818 }
3819
3820 filename = argv[optind];
3821 exec_path = argv[optind];
3822
3823 return optind;
3824}
3825
902b3d5c 3826int main(int argc, char **argv, char **envp)
31e31b8a 3827{
01ffc75b 3828 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3829 struct image_info info1, *info = &info1;
edf8e2af 3830 struct linux_binprm bprm;
48e15fc2 3831 TaskState *ts;
9349b4f9 3832 CPUArchState *env;
db6b81d4 3833 CPUState *cpu;
586314f2 3834 int optind;
04a6dfeb 3835 char **target_environ, **wrk;
7d8cec95
AJ		 3836 char **target_argv;
3837 int target_argc;
7d8cec95 3838 int i;
fd4d81dd 3839 int ret;
03cfd8fa 3840 int execfd;
b12b6a18 3841
ce008c1f
AF		 3842 module_call_init(MODULE_INIT_QOM);
3843
04a6dfeb
AJ		 3844 if ((envlist = envlist_create()) == NULL) {
3845 (void) fprintf(stderr, "Unable to allocate envlist\n");
3846 exit(1);
3847 }
3848
3849 /* add current environment into the list */
3850 for (wrk = environ; *wrk != NULL; wrk++) {
3851 (void) envlist_setenv(envlist, *wrk);
3852 }
3853
703e0e89
RH		 3854 /* Read the stack limit from the kernel. If it's "unlimited",
3855 then we can do little else besides use the default. */
3856 {
3857 struct rlimit lim;
3858 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3859 && lim.rlim_cur != RLIM_INFINITY
3860 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3861 guest_stack_size = lim.rlim_cur;
3862 }
3863 }
3864
b1f9be31 3865 cpu_model = NULL;
b5ec5ce0 3866#if defined(cpudef_setup)
3867 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3868#endif
3869
c5e4a5a9
MR		 3870 srand(time(NULL));
3871
fc9c5412 3872 optind = parse_args(argc, argv);
586314f2 3873
31e31b8a 3874 /* Zero out regs */
01ffc75b 3875 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3876
3877 /* Zero out image_info */
3878 memset(info, 0, sizeof(struct image_info));
3879
edf8e2af
MW		 3880 memset(&bprm, 0, sizeof (bprm));
3881
74cd30b8
FB		 3882 /* Scan interp_prefix dir for replacement files. */
3883 init_paths(interp_prefix);
3884
4a24a758
PM		 3885 init_qemu_uname_release();
3886
46027c07 3887 if (cpu_model == NULL) {
aaed909a 3888#if defined(TARGET_I386)
46027c07
FB		 3889#ifdef TARGET_X86_64
3890 cpu_model = "qemu64";
3891#else
3892 cpu_model = "qemu32";
3893#endif
aaed909a 3894#elif defined(TARGET_ARM)
088ab16c 3895 cpu_model = "any";
d2fbca94
GX		 3896#elif defined(TARGET_UNICORE32)
3897 cpu_model = "any";
aaed909a
FB		 3898#elif defined(TARGET_M68K)
3899 cpu_model = "any";
3900#elif defined(TARGET_SPARC)
3901#ifdef TARGET_SPARC64
3902 cpu_model = "TI UltraSparc II";
3903#else
3904 cpu_model = "Fujitsu MB86904";
46027c07 3905#endif
aaed909a
FB		 3906#elif defined(TARGET_MIPS)
3907#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 3908 cpu_model = "5KEf";
aaed909a
FB		 3909#else
3910 cpu_model = "24Kf";
3911#endif
d962783e
JL		 3912#elif defined TARGET_OPENRISC
3913 cpu_model = "or1200";
aaed909a 3914#elif defined(TARGET_PPC)
a74029f6
RH		 3915# ifdef TARGET_PPC64
3916 cpu_model = "POWER7";
3917# else
aaed909a 3918 cpu_model = "750";
a74029f6 3919# endif
aaed909a
FB		 3920#else
3921 cpu_model = "any";
3922#endif
3923 }
d5ab9713
JK		 3924 tcg_exec_init(0);
3925 cpu_exec_init_all();
83fb7adf
FB		 3926 /* NOTE: we need to init the CPU at this stage to get
3927 qemu_host_page_size */
aaed909a
FB		 3928 env = cpu_init(cpu_model);
3929 if (!env) {
3930 fprintf(stderr, "Unable to find CPU definition\n");
3931 exit(1);
3932 }
db6b81d4 3933 cpu = ENV_GET_CPU(env);
0ac46af3 3934 cpu_reset(cpu);
b55a37c9 3935
db6b81d4 3936 thread_cpu = cpu;
3b46e624 3937
b6741956
FB		 3938 if (getenv("QEMU_STRACE")) {
3939 do_strace = 1;
b92c47c1
TS		 3940 }
3941
c5e4a5a9
MR		 3942 if (getenv("QEMU_RAND_SEED")) {
3943 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3944 }
3945
04a6dfeb
AJ		 3946 target_environ = envlist_to_environ(envlist, NULL);
3947 envlist_free(envlist);
b12b6a18 3948
379f6698
PB		 3949#if defined(CONFIG_USE_GUEST_BASE)
3950 /*
3951 * Now that page sizes are configured in cpu_init() we can do
3952 * proper page alignment for guest_base.
3953 */
3954 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3955
806d1021
MI		 3956 if (reserved_va || have_guest_base) {
3957 guest_base = init_guest_space(guest_base, reserved_va, 0,
3958 have_guest_base);
3959 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3960 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3961 "space for use as guest address space (check your virtual "
3962 "memory ulimit setting or reserve less using -R option)\n",
3963 reserved_va);
68a1c816
PB		 3964 exit(1);
3965 }
97cc7560 3966
806d1021
MI		 3967 if (reserved_va) {
3968 mmap_next_start = reserved_va;
97cc7560
DDAG		 3969 }
3970 }
14f24e14 3971#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3972
3973 /*
3974 * Read in mmap_min_addr kernel parameter. This value is used
3975 * When loading the ELF image to determine whether guest_base
14f24e14 3976 * is needed. It is also used in mmap_find_vma.
379f6698 3977 */
14f24e14 3978 {
379f6698
PB		 3979 FILE *fp;
3980
3981 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3982 unsigned long tmp;
3983 if (fscanf(fp, "%lu", &tmp) == 1) {
3984 mmap_min_addr = tmp;
3985 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3986 }
3987 fclose(fp);
3988 }
3989 }
379f6698 3990
7d8cec95
AJ		 3991 /*
3992 * Prepare copy of argv vector for target.
3993 */
3994 target_argc = argc - optind;
3995 target_argv = calloc(target_argc + 1, sizeof (char *));
3996 if (target_argv == NULL) {
3997 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3998 exit(1);
3999 }
4000
4001 /*
4002 * If argv0 is specified (using '-0' switch) we replace
4003 * argv[0] pointer with the given one.
4004 */
4005 i = 0;
4006 if (argv0 != NULL) {
4007 target_argv[i++] = strdup(argv0);
4008 }
4009 for (; i < target_argc; i++) {
4010 target_argv[i] = strdup(argv[optind + i]);
4011 }
4012 target_argv[target_argc] = NULL;
4013
7267c094 4014 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4015 init_task_state(ts);
4016 /* build Task State */
4017 ts->info = info;
4018 ts->bprm = &bprm;
0429a971 4019 cpu->opaque = ts;
edf8e2af
MW		 4020 task_settid(ts);
4021
0b959cf5
RH		 4022 execfd = qemu_getauxval(AT_EXECFD);
4023 if (execfd == 0) {
03cfd8fa 4024 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4025 if (execfd < 0) {
4026 printf("Error while loading %s: %s\n", filename, strerror(errno));
4027 _exit(1);
4028 }
03cfd8fa
LV		 4029 }
4030
4031 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4032 info, &bprm);
4033 if (ret != 0) {
885c1d10 4034 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4035 _exit(1);
4036 }
4037
4038 for (wrk = target_environ; *wrk; wrk++) {
4039 free(*wrk);
31e31b8a 4040 }
3b46e624 4041
b12b6a18
TS		 4042 free(target_environ);
4043
2e77eac6 4044 if (qemu_log_enabled()) {
379f6698
PB		 4045#if defined(CONFIG_USE_GUEST_BASE)
4046 qemu_log("guest_base 0x%lx\n", guest_base);
4047#endif
2e77eac6
BS		 4048 log_page_dump();
4049
4050 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4051 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4052 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4053 info->start_code);
4054 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4055 info->start_data);
4056 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4057 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4058 info->start_stack);
4059 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4060 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4061 }
31e31b8a 4062
53a5960a 4063 target_set_brk(info->brk);
31e31b8a 4064 syscall_init();
66fb9763 4065 signal_init();
31e31b8a 4066
9002ec79
RH		 4067#if defined(CONFIG_USE_GUEST_BASE)
4068 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4069 generating the prologue until now so that the prologue can take
4070 the real value of GUEST_BASE into account. */
4071 tcg_prologue_init(&tcg_ctx);
4072#endif
4073
b346ff46 4074#if defined(TARGET_I386)
3802ce26 4075 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4076 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4077 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4078 env->cr[4] |= CR4_OSFXSR_MASK;
4079 env->hflags |= HF_OSFXSR_MASK;
4080 }
d2fd1af7 4081#ifndef TARGET_ABI32
4dbc422b 4082 /* enable 64 bit mode if possible */
0514ef2f 4083 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4084 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4085 exit(1);
4086 }
d2fd1af7 4087 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4088 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4089 env->hflags |= HF_LMA_MASK;
4090#endif
1bde465e 4091
415e561f
FB		 4092 /* flags setup : we activate the IRQs by default as in user mode */
4093 env->eflags |= IF_MASK;
3b46e624 4094
6dbad63e 4095 /* linux register setup */
d2fd1af7 4096#ifndef TARGET_ABI32
84409ddb
JM		 4097 env->regs[R_EAX] = regs->rax;
4098 env->regs[R_EBX] = regs->rbx;
4099 env->regs[R_ECX] = regs->rcx;
4100 env->regs[R_EDX] = regs->rdx;
4101 env->regs[R_ESI] = regs->rsi;
4102 env->regs[R_EDI] = regs->rdi;
4103 env->regs[R_EBP] = regs->rbp;
4104 env->regs[R_ESP] = regs->rsp;
4105 env->eip = regs->rip;
4106#else
0ecfa993
FB		 4107 env->regs[R_EAX] = regs->eax;
4108 env->regs[R_EBX] = regs->ebx;
4109 env->regs[R_ECX] = regs->ecx;
4110 env->regs[R_EDX] = regs->edx;
4111 env->regs[R_ESI] = regs->esi;
4112 env->regs[R_EDI] = regs->edi;
4113 env->regs[R_EBP] = regs->ebp;
4114 env->regs[R_ESP] = regs->esp;
dab2ed99 4115 env->eip = regs->eip;
84409ddb 4116#endif
31e31b8a 4117
f4beb510 4118 /* linux interrupt setup */
e441570f
AZ		 4119#ifndef TARGET_ABI32
4120 env->idt.limit = 511;
4121#else
4122 env->idt.limit = 255;
4123#endif
4124 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4125 PROT_READ|PROT_WRITE,
4126 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4127 idt_table = g2h(env->idt.base);
f4beb510
FB		 4128 set_idt(0, 0);
4129 set_idt(1, 0);
4130 set_idt(2, 0);
4131 set_idt(3, 3);
4132 set_idt(4, 3);
ec95da6c 4133 set_idt(5, 0);
f4beb510
FB		 4134 set_idt(6, 0);
4135 set_idt(7, 0);
4136 set_idt(8, 0);
4137 set_idt(9, 0);
4138 set_idt(10, 0);
4139 set_idt(11, 0);
4140 set_idt(12, 0);
4141 set_idt(13, 0);
4142 set_idt(14, 0);
4143 set_idt(15, 0);
4144 set_idt(16, 0);
4145 set_idt(17, 0);
4146 set_idt(18, 0);
4147 set_idt(19, 0);
4148 set_idt(0x80, 3);
4149
6dbad63e 4150 /* linux segment setup */
8d18e893
FB		 4151 {
4152 uint64_t *gdt_table;
e441570f
AZ		 4153 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4154 PROT_READ|PROT_WRITE,
4155 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4156 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4157 gdt_table = g2h(env->gdt.base);
d2fd1af7 4158#ifdef TARGET_ABI32
8d18e893
FB		 4159 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4160 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4161 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4162#else
4163 /* 64 bit code segment */
4164 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4165 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4166 DESC_L_MASK |
4167 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4168#endif
8d18e893
FB		 4169 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4170 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4171 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4172 }
6dbad63e 4173 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4174 cpu_x86_load_seg(env, R_SS, __USER_DS);
4175#ifdef TARGET_ABI32
6dbad63e
FB		 4176 cpu_x86_load_seg(env, R_DS, __USER_DS);
4177 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4178 cpu_x86_load_seg(env, R_FS, __USER_DS);
4179 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4180 /* This hack makes Wine work... */
4181 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4182#else
4183 cpu_x86_load_seg(env, R_DS, 0);
4184 cpu_x86_load_seg(env, R_ES, 0);
4185 cpu_x86_load_seg(env, R_FS, 0);
4186 cpu_x86_load_seg(env, R_GS, 0);
4187#endif
99033cae
AG		 4188#elif defined(TARGET_AARCH64)
4189 {
4190 int i;
4191
4192 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4193 fprintf(stderr,
4194 "The selected ARM CPU does not support 64 bit mode\n");
4195 exit(1);
4196 }
4197
4198 for (i = 0; i < 31; i++) {
4199 env->xregs[i] = regs->regs[i];
4200 }
4201 env->pc = regs->pc;
4202 env->xregs[31] = regs->sp;
4203 }
b346ff46
FB		 4204#elif defined(TARGET_ARM)
4205 {
4206 int i;
b5ff1b31 4207 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4208 for(i = 0; i < 16; i++) {
4209 env->regs[i] = regs->uregs[i];
4210 }
d8fd2954
PB		 4211 /* Enable BE8. */
4212 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4213 && (info->elf_flags & EF_ARM_BE8)) {
4214 env->bswap_code = 1;
4215 }
b346ff46 4216 }
d2fbca94
GX		 4217#elif defined(TARGET_UNICORE32)
4218 {
4219 int i;
4220 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4221 for (i = 0; i < 32; i++) {
4222 env->regs[i] = regs->uregs[i];
4223 }
4224 }
93ac68bc 4225#elif defined(TARGET_SPARC)
060366c5
FB		 4226 {
4227 int i;
4228 env->pc = regs->pc;
4229 env->npc = regs->npc;
4230 env->y = regs->y;
4231 for(i = 0; i < 8; i++)
4232 env->gregs[i] = regs->u_regs[i];
4233 for(i = 0; i < 8; i++)
4234 env->regwptr[i] = regs->u_regs[i + 8];
4235 }
67867308
FB		 4236#elif defined(TARGET_PPC)
4237 {
4238 int i;
3fc6c082 4239
0411a972
JM		 4240#if defined(TARGET_PPC64)
4241#if defined(TARGET_ABI32)
4242 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4243#else
0411a972
JM		 4244 env->msr |= (target_ulong)1 << MSR_SF;
4245#endif
84409ddb 4246#endif
67867308
FB		 4247 env->nip = regs->nip;
4248 for(i = 0; i < 32; i++) {
4249 env->gpr[i] = regs->gpr[i];
4250 }
4251 }
e6e5906b
PB		 4252#elif defined(TARGET_M68K)
4253 {
e6e5906b
PB		 4254 env->pc = regs->pc;
4255 env->dregs[0] = regs->d0;
4256 env->dregs[1] = regs->d1;
4257 env->dregs[2] = regs->d2;
4258 env->dregs[3] = regs->d3;
4259 env->dregs[4] = regs->d4;
4260 env->dregs[5] = regs->d5;
4261 env->dregs[6] = regs->d6;
4262 env->dregs[7] = regs->d7;
4263 env->aregs[0] = regs->a0;
4264 env->aregs[1] = regs->a1;
4265 env->aregs[2] = regs->a2;
4266 env->aregs[3] = regs->a3;
4267 env->aregs[4] = regs->a4;
4268 env->aregs[5] = regs->a5;
4269 env->aregs[6] = regs->a6;
4270 env->aregs[7] = regs->usp;
4271 env->sr = regs->sr;
4272 ts->sim_syscalls = 1;
4273 }
b779e29e
EI		 4274#elif defined(TARGET_MICROBLAZE)
4275 {
4276 env->regs[0] = regs->r0;
4277 env->regs[1] = regs->r1;
4278 env->regs[2] = regs->r2;
4279 env->regs[3] = regs->r3;
4280 env->regs[4] = regs->r4;
4281 env->regs[5] = regs->r5;
4282 env->regs[6] = regs->r6;
4283 env->regs[7] = regs->r7;
4284 env->regs[8] = regs->r8;
4285 env->regs[9] = regs->r9;
4286 env->regs[10] = regs->r10;
4287 env->regs[11] = regs->r11;
4288 env->regs[12] = regs->r12;
4289 env->regs[13] = regs->r13;
4290 env->regs[14] = regs->r14;
4291 env->regs[15] = regs->r15;
4292 env->regs[16] = regs->r16;
4293 env->regs[17] = regs->r17;
4294 env->regs[18] = regs->r18;
4295 env->regs[19] = regs->r19;
4296 env->regs[20] = regs->r20;
4297 env->regs[21] = regs->r21;
4298 env->regs[22] = regs->r22;
4299 env->regs[23] = regs->r23;
4300 env->regs[24] = regs->r24;
4301 env->regs[25] = regs->r25;
4302 env->regs[26] = regs->r26;
4303 env->regs[27] = regs->r27;
4304 env->regs[28] = regs->r28;
4305 env->regs[29] = regs->r29;
4306 env->regs[30] = regs->r30;
4307 env->regs[31] = regs->r31;
4308 env->sregs[SR_PC] = regs->pc;
4309 }
048f6b4d
FB		 4310#elif defined(TARGET_MIPS)
4311 {
4312 int i;
4313
4314 for(i = 0; i < 32; i++) {
b5dc7732 4315 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4316 }
0fddbbf2
NF		 4317 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4318 if (regs->cp0_epc & 1) {
4319 env->hflags |= MIPS_HFLAG_M16;
4320 }
048f6b4d 4321 }
d962783e
JL		 4322#elif defined(TARGET_OPENRISC)
4323 {
4324 int i;
4325
4326 for (i = 0; i < 32; i++) {
4327 env->gpr[i] = regs->gpr[i];
4328 }
4329
4330 env->sr = regs->sr;
4331 env->pc = regs->pc;
4332 }
fdf9b3e8
FB		 4333#elif defined(TARGET_SH4)
4334 {
4335 int i;
4336
4337 for(i = 0; i < 16; i++) {
4338 env->gregs[i] = regs->regs[i];
4339 }
4340 env->pc = regs->pc;
4341 }
7a3148a9
JM		 4342#elif defined(TARGET_ALPHA)
4343 {
4344 int i;
4345
4346 for(i = 0; i < 28; i++) {
992f48a0 4347 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4348 }
dad081ee 4349 env->ir[IR_SP] = regs->usp;
7a3148a9 4350 env->pc = regs->pc;
7a3148a9 4351 }
48733d19
TS		 4352#elif defined(TARGET_CRIS)
4353 {
4354 env->regs[0] = regs->r0;
4355 env->regs[1] = regs->r1;
4356 env->regs[2] = regs->r2;
4357 env->regs[3] = regs->r3;
4358 env->regs[4] = regs->r4;
4359 env->regs[5] = regs->r5;
4360 env->regs[6] = regs->r6;
4361 env->regs[7] = regs->r7;
4362 env->regs[8] = regs->r8;
4363 env->regs[9] = regs->r9;
4364 env->regs[10] = regs->r10;
4365 env->regs[11] = regs->r11;
4366 env->regs[12] = regs->r12;
4367 env->regs[13] = regs->r13;
4368 env->regs[14] = info->start_stack;
4369 env->regs[15] = regs->acr;
4370 env->pc = regs->erp;
4371 }
a4c075f1
UH		 4372#elif defined(TARGET_S390X)
4373 {
4374 int i;
4375 for (i = 0; i < 16; i++) {
4376 env->regs[i] = regs->gprs[i];
4377 }
4378 env->psw.mask = regs->psw.mask;
4379 env->psw.addr = regs->psw.addr;
4380 }
b346ff46
FB		 4381#else
4382#error unsupported target CPU
4383#endif
31e31b8a 4384
d2fbca94 4385#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4386 ts->stack_base = info->start_stack;
4387 ts->heap_base = info->brk;
4388 /* This will be filled in on the first SYS_HEAPINFO call. */
4389 ts->heap_limit = 0;
4390#endif
4391
74c33bed 4392 if (gdbstub_port) {
ff7a981a
PM		 4393 if (gdbserver_start(gdbstub_port) < 0) {
4394 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4395 gdbstub_port);
4396 exit(1);
4397 }
db6b81d4 4398 gdb_handlesig(cpu, 0);
1fddef4b 4399 }
1b6b029e
FB		 4400 cpu_loop(env);
4401 /* never exits */
31e31b8a
FB		 4402 return 0;
4403}
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