[qemu.git] / hw / ide / cmd646.c

/*
 * QEMU IDE Emulation: PCI cmd646 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "sysemu/block-backend.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

/* CMD646 specific */
#define CFR		0x50
#define   CFR_INTR_CH0	0x04
#define CNTRL		0x51
#define   CNTRL_EN_CH0	0x04
#define   CNTRL_EN_CH1	0x08
#define ARTTIM23	0x57
#define    ARTTIM23_INTR_CH1	0x10
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define   MRDMODE_BLK_CH0	0x10
#define   MRDMODE_BLK_CH1	0x20
#define UDIDETCR0	0x73
#define UDIDETCR1	0x7B

static void cmd646_update_irq(PCIDevice *pd);

static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }
    return ide_status_read(cmd646bar->bus, addr + 2);
}

static void cmd646_cmd_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (addr != 2 || size != 1) {
        return;
    }
    ide_cmd_write(cmd646bar->bus, addr + 2, data);
}

static const MemoryRegionOps cmd646_cmd_ops = {
    .read = cmd646_cmd_read,
    .write = cmd646_cmd_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        return ide_ioport_read(cmd646bar->bus, addr);
    } else if (addr == 0) {
        if (size == 2) {
            return ide_data_readw(cmd646bar->bus, addr);
        } else {
            return ide_data_readl(cmd646bar->bus, addr);
        }
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void cmd646_data_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned size)
{
    CMD646BAR *cmd646bar = opaque;

    if (size == 1) {
        ide_ioport_write(cmd646bar->bus, addr, data);
    } else if (addr == 0) {
        if (size == 2) {
            ide_data_writew(cmd646bar->bus, addr, data);
        } else {
            ide_data_writel(cmd646bar->bus, addr, data);
        }
    }
}

static const MemoryRegionOps cmd646_data_ops = {
    .read = cmd646_data_read,
    .write = cmd646_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
{
    IDEBus *bus = &d->bus[bus_num];
    CMD646BAR *bar = &d->cmd646_bar[bus_num];

    bar->bus = bus;
    bar->pci_dev = d;
    memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
                          "cmd646-cmd", 4);
    memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
                          "cmd646-data", 8);
}

static void cmd646_update_dma_interrupts(PCIDevice *pd)
{
    /* Sync DMA interrupt status from UDMA interrupt status */
    if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
        pd->config[CFR] |= CFR_INTR_CH0;
    } else {
        pd->config[CFR] &= ~CFR_INTR_CH0;
    }

    if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
        pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
    } else {
        pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
    }
}

static void cmd646_update_udma_interrupts(PCIDevice *pd)
{
    /* Sync UDMA interrupt status from DMA interrupt status */
    if (pd->config[CFR] & CFR_INTR_CH0) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
    }

    if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
    }
}

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 1:
        val = pci_dev->config[MRDMODE];
        break;
    case 2:
        val = bm->status;
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            val = pci_dev->config[UDIDETCR0];
        } else {
            val = pci_dev->config[UDIDETCR1];
        }
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
#endif
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 1:
        pci_dev->config[MRDMODE] =
            (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
        cmd646_update_dma_interrupts(pci_dev);
        cmd646_update_irq(pci_dev);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            pci_dev->config[UDIDETCR0] = val;
        } else {
            pci_dev->config[UDIDETCR1] = val;
        }
        break;
    }
}

static const MemoryRegionOps cmd646_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    BMDMAState *bm;
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
    for(i = 0;i < 2; i++) {
        bm = &d->bmdma[i];
        memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
                              "cmd646-bmdma-bus", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm,
                              "cmd646-bmdma-ioport", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void cmd646_update_irq(PCIDevice *pd)
{
    int pci_level;

    pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
                 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
        ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
         !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
    pci_set_irq(pd, pci_level);
}

/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    int irq_mask;

    irq_mask = MRDMODE_INTR_CH0 << channel;
    if (level) {
        pd->config[MRDMODE] |= irq_mask;
    } else {
        pd->config[MRDMODE] &= ~irq_mask;
    }
    cmd646_update_dma_interrupts(pd);
    cmd646_update_irq(pd);
}

static void cmd646_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    unsigned int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }
}

static uint32_t cmd646_pci_config_read(PCIDevice *d,
                                       uint32_t address, int len)
{
    return pci_default_read_config(d, address, len);
}

static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
                                    int l)
{
    uint32_t i;

    pci_default_write_config(d, addr, val, l);

    for (i = addr; i < addr + l; i++) {
        switch (i) {
        case CFR:
        case ARTTIM23:
            cmd646_update_udma_interrupts(d);
            break;
        case MRDMODE:
            cmd646_update_dma_interrupts(d);
            break;
        }
    }

    cmd646_update_irq(d);
}

/* CMD646 PCI IDE controller */
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
    }

    /* Set write-to-clear interrupt bits */
    dev->wmask[CFR] = 0x0;
    dev->w1cmask[CFR] = CFR_INTR_CH0;
    dev->wmask[ARTTIM23] = 0x0;
    dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
    dev->wmask[MRDMODE] = 0x0;
    dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;

    setup_cmd646_bar(d, 0);
    setup_cmd646_bar(d, 1);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
}

static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
    }
}

void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled)
{
    PCIDevice *dev;

    dev = pci_create(bus, -1, "cmd646-ide");
    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
    qdev_init_nofail(&dev->qdev);

    pci_ide_create_devs(dev, hd_table);
}

static Property cmd646_ide_properties[] = {
    DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_cmd646_ide_realize;
    k->exit = pci_cmd646_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_CMD;
    k->device_id = PCI_DEVICE_ID_CMD_646;
    k->revision = 0x07;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    k->config_read = cmd646_pci_config_read;
    k->config_write = cmd646_pci_config_write;
    dc->props = cmd646_ide_properties;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}

static const TypeInfo cmd646_ide_info = {
    .name          = "cmd646-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = cmd646_ide_class_init,
};

static void cmd646_ide_register_types(void)
{
    type_register_static(&cmd646_ide_info);
}

type_init(cmd646_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI cmd646 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
a2cb15b0	27	#include <hw/pci/pci.h>
0d09e41a	28	#include <hw/isa/isa.h>
4be74634	29	#include "sysemu/block-backend.h"
9c17d615 PB	30	#include "sysemu/sysemu.h"
9c17d615 PB	31	#include "sysemu/dma.h"
4c3df0ec JQ	32
	33	#include <hw/ide/pci.h>
	34
	35	/* CMD646 specific */
5bbc0a70 MCA	36	#define CFR 0x50
5bbc0a70 MCA	37	#define CFR_INTR_CH0 0x04
58f16a7b MCA	38	#define CNTRL 0x51
	39	#define CNTRL_EN_CH0 0x04
	40	#define CNTRL_EN_CH1 0x08
5bbc0a70 MCA	41	#define ARTTIM23 0x57
5bbc0a70 MCA	42	#define ARTTIM23_INTR_CH1 0x10
4c3df0ec JQ	43	#define MRDMODE 0x71
	44	#define MRDMODE_INTR_CH0 0x04
	45	#define MRDMODE_INTR_CH1 0x08
	46	#define MRDMODE_BLK_CH0 0x10
	47	#define MRDMODE_BLK_CH1 0x20
	48	#define UDIDETCR0 0x73
	49	#define UDIDETCR1 0x7B
	50
dab91a1e	51	static void cmd646_update_irq(PCIDevice *pd);
4c3df0ec	52
a8170e5e	53	static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
a9deb8c6	54	unsigned size)
4c3df0ec	55	{
a9deb8c6 AK	56	CMD646BAR *cmd646bar = opaque;
	57
	58	if (addr != 2 \|\| size != 1) {
	59	return ((uint64_t)1 << (size * 8)) - 1;
	60	}
	61	return ide_status_read(cmd646bar->bus, addr + 2);
	62	}
	63
a8170e5e	64	static void cmd646_cmd_write(void *opaque, hwaddr addr,
a9deb8c6 AK	65	uint64_t data, unsigned size)
	66	{
	67	CMD646BAR *cmd646bar = opaque;
	68
	69	if (addr != 2 \|\| size != 1) {
	70	return;
	71	}
	72	ide_cmd_write(cmd646bar->bus, addr + 2, data);
	73	}
	74
a348f108	75	static const MemoryRegionOps cmd646_cmd_ops = {
a9deb8c6 AK	76	.read = cmd646_cmd_read,
	77	.write = cmd646_cmd_write,
	78	.endianness = DEVICE_LITTLE_ENDIAN,
	79	};
	80
a8170e5e	81	static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
a9deb8c6 AK	82	unsigned size)
	83	{
	84	CMD646BAR *cmd646bar = opaque;
	85
	86	if (size == 1) {
	87	return ide_ioport_read(cmd646bar->bus, addr);
	88	} else if (addr == 0) {
	89	if (size == 2) {
	90	return ide_data_readw(cmd646bar->bus, addr);
4c3df0ec	91	} else {
a9deb8c6	92	return ide_data_readl(cmd646bar->bus, addr);
4c3df0ec JQ	93	}
4c3df0ec JQ	94	}
a9deb8c6	95	return ((uint64_t)1 << (size * 8)) - 1;
4c3df0ec JQ	96	}
4c3df0ec JQ	97
a8170e5e	98	static void cmd646_data_write(void *opaque, hwaddr addr,
a9deb8c6	99	uint64_t data, unsigned size)
61f58e59	100	{
a9deb8c6 AK	101	CMD646BAR *cmd646bar = opaque;
	102
	103	if (size == 1) {
0ed8b6f6	104	ide_ioport_write(cmd646bar->bus, addr, data);
a9deb8c6 AK	105	} else if (addr == 0) {
a9deb8c6 AK	106	if (size == 2) {
0ed8b6f6	107	ide_data_writew(cmd646bar->bus, addr, data);
a9deb8c6	108	} else {
0ed8b6f6	109	ide_data_writel(cmd646bar->bus, addr, data);
a9deb8c6 AK	110	}
	111	}
	112	}
	113
a348f108	114	static const MemoryRegionOps cmd646_data_ops = {
a9deb8c6 AK	115	.read = cmd646_data_read,
	116	.write = cmd646_data_write,
	117	.endianness = DEVICE_LITTLE_ENDIAN,
	118	};
	119
	120	static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
	121	{
	122	IDEBus *bus = &d->bus[bus_num];
	123	CMD646BAR *bar = &d->cmd646_bar[bus_num];
	124
	125	bar->bus = bus;
	126	bar->pci_dev = d;
1437c94b PB	127	memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
	128	"cmd646-cmd", 4);
	129	memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
	130	"cmd646-data", 8);
a9deb8c6 AK	131	}
a9deb8c6 AK	132
5bbc0a70 MCA	133	static void cmd646_update_dma_interrupts(PCIDevice *pd)
	134	{
	135	/* Sync DMA interrupt status from UDMA interrupt status */
	136	if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
	137	pd->config[CFR] \|= CFR_INTR_CH0;
	138	} else {
	139	pd->config[CFR] &= ~CFR_INTR_CH0;
	140	}
	141
	142	if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
	143	pd->config[ARTTIM23] \|= ARTTIM23_INTR_CH1;
	144	} else {
	145	pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
	146	}
	147	}
	148
271dddd1 MCA	149	static void cmd646_update_udma_interrupts(PCIDevice *pd)
	150	{
	151	/* Sync UDMA interrupt status from DMA interrupt status */
	152	if (pd->config[CFR] & CFR_INTR_CH0) {
	153	pd->config[MRDMODE] \|= MRDMODE_INTR_CH0;
	154	} else {
	155	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
	156	}
	157
	158	if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
	159	pd->config[MRDMODE] \|= MRDMODE_INTR_CH1;
	160	} else {
	161	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
	162	}
	163	}
	164
a8170e5e	165	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6 AK	166	unsigned size)
	167	{
	168	BMDMAState *bm = opaque;
f6c11d56	169	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
4c3df0ec JQ	170	uint32_t val;
4c3df0ec JQ	171
a9deb8c6 AK	172	if (size != 1) {
	173	return ((uint64_t)1 << (size * 8)) - 1;
	174	}
	175
4c3df0ec JQ	176	switch(addr & 3) {
	177	case 0:
	178	val = bm->cmd;
	179	break;
	180	case 1:
f6c11d56	181	val = pci_dev->config[MRDMODE];
4c3df0ec JQ	182	break;
	183	case 2:
	184	val = bm->status;
	185	break;
	186	case 3:
f6c11d56 AF	187	if (bm == &bm->pci_dev->bmdma[0]) {
f6c11d56 AF	188	val = pci_dev->config[UDIDETCR0];
4c3df0ec	189	} else {
f6c11d56	190	val = pci_dev->config[UDIDETCR1];
4c3df0ec JQ	191	}
	192	break;
	193	default:
	194	val = 0xff;
	195	break;
	196	}
	197	#ifdef DEBUG_IDE
721da65c	198	printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
4c3df0ec JQ	199	#endif
	200	return val;
	201	}
	202
a8170e5e	203	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	204	uint64_t val, unsigned size)
70ae65f5	205	{
a9deb8c6	206	BMDMAState *bm = opaque;
f6c11d56	207	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
70ae65f5	208
a9deb8c6 AK	209	if (size != 1) {
	210	return;
	211	}
70ae65f5	212
4c3df0ec	213	#ifdef DEBUG_IDE
721da65c	214	printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
4c3df0ec JQ	215	#endif
4c3df0ec JQ	216	switch(addr & 3) {
50a48094	217	case 0:
a9deb8c6	218	bmdma_cmd_writeb(bm, val);
50a48094	219	break;
4c3df0ec	220	case 1:
f6c11d56 AF	221	pci_dev->config[MRDMODE] =
f6c11d56 AF	222	(pci_dev->config[MRDMODE] & ~0x30) \| (val & 0x30);
5bbc0a70	223	cmd646_update_dma_interrupts(pci_dev);
dab91a1e	224	cmd646_update_irq(pci_dev);
4c3df0ec JQ	225	break;
	226	case 2:
	227	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	228	break;
	229	case 3:
f6c11d56 AF	230	if (bm == &bm->pci_dev->bmdma[0]) {
	231	pci_dev->config[UDIDETCR0] = val;
	232	} else {
	233	pci_dev->config[UDIDETCR1] = val;
	234	}
4c3df0ec JQ	235	break;
	236	}
	237	}
	238
a348f108	239	static const MemoryRegionOps cmd646_bmdma_ops = {
a9deb8c6 AK	240	.read = bmdma_read,
	241	.write = bmdma_write,
	242	};
70ae65f5	243
a9deb8c6	244	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	245	{
a9deb8c6	246	BMDMAState *bm;
4c3df0ec JQ	247	int i;
4c3df0ec JQ	248
1437c94b	249	memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
4c3df0ec	250	for(i = 0;i < 2; i++) {
a9deb8c6	251	bm = &d->bmdma[i];
1437c94b	252	memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
a9deb8c6 AK	253	"cmd646-bmdma-bus", 4);
a9deb8c6 AK	254	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	255	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	256	&bmdma_addr_ioport_ops, bm,
a9deb8c6 AK	257	"cmd646-bmdma-ioport", 4);
a9deb8c6 AK	258	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	259	}
	260	}
	261
dab91a1e	262	static void cmd646_update_irq(PCIDevice *pd)
4c3df0ec JQ	263	{
4c3df0ec JQ	264	int pci_level;
f6c11d56 AF	265
	266	pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
	267	!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) \|\|
	268	((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
	269	!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
9e64f8a3	270	pci_set_irq(pd, pci_level);
4c3df0ec JQ	271	}
	272
	273	/* the PCI irq level is the logical OR of the two channels */
	274	static void cmd646_set_irq(void *opaque, int channel, int level)
	275	{
	276	PCIIDEState *d = opaque;
f6c11d56	277	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec JQ	278	int irq_mask;
	279
	280	irq_mask = MRDMODE_INTR_CH0 << channel;
f6c11d56 AF	281	if (level) {
	282	pd->config[MRDMODE] \|= irq_mask;
	283	} else {
	284	pd->config[MRDMODE] &= ~irq_mask;
	285	}
5bbc0a70	286	cmd646_update_dma_interrupts(pd);
dab91a1e	287	cmd646_update_irq(pd);
4c3df0ec JQ	288	}
	289
	290	static void cmd646_reset(void *opaque)
	291	{
	292	PCIIDEState *d = opaque;
	293	unsigned int i;
	294
4a643563 BS	295	for (i = 0; i < 2; i++) {
4a643563 BS	296	ide_bus_reset(&d->bus[i]);
4a643563	297	}
4c3df0ec JQ	298	}
4c3df0ec JQ	299
1d113ef8 MCA	300	static uint32_t cmd646_pci_config_read(PCIDevice *d,
	301	uint32_t address, int len)
	302	{
	303	return pci_default_read_config(d, address, len);
	304	}
	305
	306	static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
	307	int l)
	308	{
	309	uint32_t i;
	310
	311	pci_default_write_config(d, addr, val, l);
	312
	313	for (i = addr; i < addr + l; i++) {
	314	switch (i) {
271dddd1 MCA	315	case CFR:
	316	case ARTTIM23:
	317	cmd646_update_udma_interrupts(d);
	318	break;
1d113ef8 MCA	319	case MRDMODE:
	320	cmd646_update_dma_interrupts(d);
	321	break;
	322	}
	323	}
	324
	325	cmd646_update_irq(d);
	326	}
	327
4c3df0ec	328	/* CMD646 PCI IDE controller */
9af21dbe	329	static void pci_cmd646_ide_realize(PCIDevice dev, Error *errp)
4c3df0ec	330	{
f6c11d56 AF	331	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	332	uint8_t *pci_conf = dev->config;
4c3df0ec	333	qemu_irq *irq;
61d9d6b0	334	int i;
4c3df0ec	335
409570a7	336	pci_conf[PCI_CLASS_PROG] = 0x8f;
4c3df0ec	337
58f16a7b	338	pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
4c3df0ec JQ	339	if (d->secondary) {
4c3df0ec JQ	340	/* XXX: if not enabled, really disable the seconday IDE controller */
58f16a7b	341	pci_conf[CNTRL] \|= CNTRL_EN_CH1; /* enable IDE1 */
4c3df0ec JQ	342	}
4c3df0ec JQ	343
1d113ef8	344	/* Set write-to-clear interrupt bits */
271dddd1 MCA	345	dev->wmask[CFR] = 0x0;
	346	dev->w1cmask[CFR] = CFR_INTR_CH0;
	347	dev->wmask[ARTTIM23] = 0x0;
	348	dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
1d113ef8 MCA	349	dev->wmask[MRDMODE] = 0x0;
	350	dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1;
	351
a9deb8c6 AK	352	setup_cmd646_bar(d, 0);
a9deb8c6 AK	353	setup_cmd646_bar(d, 1);
e824b2cc AK	354	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
	355	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
	356	pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
	357	pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
a9deb8c6	358	bmdma_setup_bar(d);
e824b2cc	359	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	360
409570a7 MT	361	/* TODO: RST# value should be 0 */
409570a7 MT	362	pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
4c3df0ec JQ	363
4c3df0ec JQ	364	irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
61d9d6b0	365	for (i = 0; i < 2; i++) {
c6baf942	366	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
61d9d6b0 SH	367	ide_init2(&d->bus[i], irq[i]);
61d9d6b0 SH	368
a9deb8c6	369	bmdma_init(&d->bus[i], &d->bmdma[i], d);
f56b18c0	370	d->bmdma[i].bus = &d->bus[i];
f878c916	371	ide_register_restart_cb(&d->bus[i]);
61d9d6b0	372	}
4c3df0ec	373
f6c11d56	374	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
4c3df0ec	375	qemu_register_reset(cmd646_reset, d);
4c3df0ec JQ	376	}
4c3df0ec JQ	377
f90c2bcd	378	static void pci_cmd646_ide_exitfn(PCIDevice *dev)
a9deb8c6	379	{
f6c11d56	380	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	381	unsigned i;
	382
	383	for (i = 0; i < 2; ++i) {
	384	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
a9deb8c6	385	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
a9deb8c6	386	}
a9deb8c6 AK	387	}
a9deb8c6 AK	388
4c3df0ec JQ	389	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
	390	int secondary_ide_enabled)
	391	{
	392	PCIDevice *dev;
	393
556cd098	394	dev = pci_create(bus, -1, "cmd646-ide");
4c3df0ec JQ	395	qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
	396	qdev_init_nofail(&dev->qdev);
	397
	398	pci_ide_create_devs(dev, hd_table);
	399	}
	400
40021f08 AL	401	static Property cmd646_ide_properties[] = {
	402	DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
	403	DEFINE_PROP_END_OF_LIST(),
	404	};
	405
	406	static void cmd646_ide_class_init(ObjectClass klass, void data)
	407	{
39bffca2	408	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	409	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	410
9af21dbe	411	k->realize = pci_cmd646_ide_realize;
40021f08 AL	412	k->exit = pci_cmd646_ide_exitfn;
	413	k->vendor_id = PCI_VENDOR_ID_CMD;
	414	k->device_id = PCI_DEVICE_ID_CMD_646;
	415	k->revision = 0x07;
	416	k->class_id = PCI_CLASS_STORAGE_IDE;
1d113ef8 MCA	417	k->config_read = cmd646_pci_config_read;
1d113ef8 MCA	418	k->config_write = cmd646_pci_config_write;
39bffca2	419	dc->props = cmd646_ide_properties;
74623e73	420	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
40021f08 AL	421	}
40021f08 AL	422
8c43a6f0	423	static const TypeInfo cmd646_ide_info = {
39bffca2	424	.name = "cmd646-ide",
f6c11d56	425	.parent = TYPE_PCI_IDE,
39bffca2	426	.class_init = cmd646_ide_class_init,
4c3df0ec JQ	427	};
4c3df0ec JQ	428
83f7d43a	429	static void cmd646_ide_register_types(void)
4c3df0ec	430	{
39bffca2	431	type_register_static(&cmd646_ide_info);
4c3df0ec	432	}
83f7d43a AF	433
83f7d43a AF	434	type_init(cmd646_ide_register_types)