]>
Commit | Line | Data |
---|---|---|
4c3df0ec JQ |
1 | /* |
2 | * QEMU IDE Emulation: PCI cmd646 support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include <hw/hw.h> | |
26 | #include <hw/pc.h> | |
27 | #include <hw/pci.h> | |
28 | #include <hw/isa.h> | |
29 | #include "block.h" | |
30 | #include "block_int.h" | |
31 | #include "sysemu.h" | |
32 | #include "dma.h" | |
33 | ||
34 | #include <hw/ide/pci.h> | |
35 | ||
36 | /* CMD646 specific */ | |
37 | #define MRDMODE 0x71 | |
38 | #define MRDMODE_INTR_CH0 0x04 | |
39 | #define MRDMODE_INTR_CH1 0x08 | |
40 | #define MRDMODE_BLK_CH0 0x10 | |
41 | #define MRDMODE_BLK_CH1 0x20 | |
42 | #define UDIDETCR0 0x73 | |
43 | #define UDIDETCR1 0x7B | |
44 | ||
45 | static void cmd646_update_irq(PCIIDEState *d); | |
46 | ||
47 | static void ide_map(PCIDevice *pci_dev, int region_num, | |
48 | uint32_t addr, uint32_t size, int type) | |
49 | { | |
50 | PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); | |
51 | IDEBus *bus; | |
52 | ||
53 | if (region_num <= 3) { | |
54 | bus = &d->bus[(region_num >> 1)]; | |
55 | if (region_num & 1) { | |
56 | register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); | |
57 | register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); | |
58 | } else { | |
59 | register_ioport_write(addr, 8, 1, ide_ioport_write, bus); | |
60 | register_ioport_read(addr, 8, 1, ide_ioport_read, bus); | |
61 | ||
62 | /* data ports */ | |
63 | register_ioport_write(addr, 2, 2, ide_data_writew, bus); | |
64 | register_ioport_read(addr, 2, 2, ide_data_readw, bus); | |
65 | register_ioport_write(addr, 4, 4, ide_data_writel, bus); | |
66 | register_ioport_read(addr, 4, 4, ide_data_readl, bus); | |
67 | } | |
68 | } | |
69 | } | |
70 | ||
71 | static uint32_t bmdma_readb(void *opaque, uint32_t addr) | |
72 | { | |
73 | BMDMAState *bm = opaque; | |
74 | PCIIDEState *pci_dev; | |
75 | uint32_t val; | |
76 | ||
77 | switch(addr & 3) { | |
78 | case 0: | |
79 | val = bm->cmd; | |
80 | break; | |
81 | case 1: | |
82 | pci_dev = bm->pci_dev; | |
83 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
84 | val = pci_dev->dev.config[MRDMODE]; | |
85 | } else { | |
86 | val = 0xff; | |
87 | } | |
88 | break; | |
89 | case 2: | |
90 | val = bm->status; | |
91 | break; | |
92 | case 3: | |
93 | pci_dev = bm->pci_dev; | |
94 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
95 | if (bm == &pci_dev->bmdma[0]) | |
96 | val = pci_dev->dev.config[UDIDETCR0]; | |
97 | else | |
98 | val = pci_dev->dev.config[UDIDETCR1]; | |
99 | } else { | |
100 | val = 0xff; | |
101 | } | |
102 | break; | |
103 | default: | |
104 | val = 0xff; | |
105 | break; | |
106 | } | |
107 | #ifdef DEBUG_IDE | |
108 | printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); | |
109 | #endif | |
110 | return val; | |
111 | } | |
112 | ||
113 | static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) | |
114 | { | |
115 | BMDMAState *bm = opaque; | |
116 | PCIIDEState *pci_dev; | |
117 | #ifdef DEBUG_IDE | |
118 | printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); | |
119 | #endif | |
120 | switch(addr & 3) { | |
121 | case 1: | |
122 | pci_dev = bm->pci_dev; | |
123 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
124 | pci_dev->dev.config[MRDMODE] = | |
125 | (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); | |
126 | cmd646_update_irq(pci_dev); | |
127 | } | |
128 | break; | |
129 | case 2: | |
130 | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); | |
131 | break; | |
132 | case 3: | |
133 | pci_dev = bm->pci_dev; | |
134 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
135 | if (bm == &pci_dev->bmdma[0]) | |
136 | pci_dev->dev.config[UDIDETCR0] = val; | |
137 | else | |
138 | pci_dev->dev.config[UDIDETCR1] = val; | |
139 | } | |
140 | break; | |
141 | } | |
142 | } | |
143 | ||
144 | static void bmdma_map(PCIDevice *pci_dev, int region_num, | |
145 | uint32_t addr, uint32_t size, int type) | |
146 | { | |
147 | PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); | |
148 | int i; | |
149 | ||
150 | for(i = 0;i < 2; i++) { | |
151 | BMDMAState *bm = &d->bmdma[i]; | |
152 | d->bus[i].bmdma = bm; | |
153 | bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); | |
154 | bm->bus = d->bus+i; | |
155 | qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); | |
156 | ||
157 | register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); | |
158 | ||
159 | register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); | |
160 | register_ioport_read(addr, 4, 1, bmdma_readb, bm); | |
161 | ||
162 | register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); | |
163 | register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); | |
164 | register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); | |
165 | register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); | |
166 | register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); | |
167 | register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); | |
168 | addr += 8; | |
169 | } | |
170 | } | |
171 | ||
172 | /* XXX: call it also when the MRDMODE is changed from the PCI config | |
173 | registers */ | |
174 | static void cmd646_update_irq(PCIIDEState *d) | |
175 | { | |
176 | int pci_level; | |
177 | pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && | |
178 | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || | |
179 | ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && | |
180 | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); | |
181 | qemu_set_irq(d->dev.irq[0], pci_level); | |
182 | } | |
183 | ||
184 | /* the PCI irq level is the logical OR of the two channels */ | |
185 | static void cmd646_set_irq(void *opaque, int channel, int level) | |
186 | { | |
187 | PCIIDEState *d = opaque; | |
188 | int irq_mask; | |
189 | ||
190 | irq_mask = MRDMODE_INTR_CH0 << channel; | |
191 | if (level) | |
192 | d->dev.config[MRDMODE] |= irq_mask; | |
193 | else | |
194 | d->dev.config[MRDMODE] &= ~irq_mask; | |
195 | cmd646_update_irq(d); | |
196 | } | |
197 | ||
198 | static void cmd646_reset(void *opaque) | |
199 | { | |
200 | PCIIDEState *d = opaque; | |
201 | unsigned int i; | |
202 | ||
203 | for (i = 0; i < 2; i++) | |
204 | ide_dma_cancel(&d->bmdma[i]); | |
205 | } | |
206 | ||
207 | /* CMD646 PCI IDE controller */ | |
208 | static int pci_cmd646_ide_initfn(PCIDevice *dev) | |
209 | { | |
210 | PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); | |
211 | uint8_t *pci_conf = d->dev.config; | |
212 | qemu_irq *irq; | |
213 | ||
214 | d->type = IDE_TYPE_CMD646; | |
215 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); | |
216 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); | |
217 | ||
218 | pci_conf[0x08] = 0x07; // IDE controller revision | |
219 | pci_conf[0x09] = 0x8f; | |
220 | ||
221 | pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); | |
222 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type | |
223 | ||
224 | pci_conf[0x51] = 0x04; // enable IDE0 | |
225 | if (d->secondary) { | |
226 | /* XXX: if not enabled, really disable the seconday IDE controller */ | |
227 | pci_conf[0x51] |= 0x08; /* enable IDE1 */ | |
228 | } | |
229 | ||
230 | pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); | |
231 | pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); | |
232 | pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); | |
233 | pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); | |
234 | pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); | |
235 | ||
236 | pci_conf[0x3d] = 0x01; // interrupt on pin 1 | |
237 | ||
238 | irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); | |
239 | ide_bus_new(&d->bus[0], &d->dev.qdev); | |
240 | ide_bus_new(&d->bus[1], &d->dev.qdev); | |
241 | ide_init2(&d->bus[0], NULL, NULL, irq[0]); | |
242 | ide_init2(&d->bus[1], NULL, NULL, irq[1]); | |
243 | ||
244 | register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); | |
245 | qemu_register_reset(cmd646_reset, d); | |
246 | cmd646_reset(d); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, | |
251 | int secondary_ide_enabled) | |
252 | { | |
253 | PCIDevice *dev; | |
254 | ||
255 | dev = pci_create(bus, -1, "CMD646 IDE"); | |
256 | qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); | |
257 | qdev_init_nofail(&dev->qdev); | |
258 | ||
259 | pci_ide_create_devs(dev, hd_table); | |
260 | } | |
261 | ||
262 | static PCIDeviceInfo cmd646_ide_info[] = { | |
263 | { | |
264 | .qdev.name = "CMD646 IDE", | |
265 | .qdev.size = sizeof(PCIIDEState), | |
266 | .init = pci_cmd646_ide_initfn, | |
267 | .qdev.props = (Property[]) { | |
268 | DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), | |
269 | DEFINE_PROP_END_OF_LIST(), | |
270 | }, | |
271 | },{ | |
272 | /* end of list */ | |
273 | } | |
274 | }; | |
275 | ||
276 | static void cmd646_ide_register(void) | |
277 | { | |
278 | pci_qdev_register_many(cmd646_ide_info); | |
279 | } | |
280 | device_init(cmd646_ide_register); |