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3cbee15b 1/*
4d7ca41e 2 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
3cbee15b
JM
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
87ecb68b
PB
25#include "hw.h"
26#include "ppc.h"
3cbee15b 27#include "ppc_mac.h"
28ce5ce6 28#include "mac_dbdma.h"
87ecb68b
PB
29#include "nvram.h"
30#include "pc.h"
31#include "sysemu.h"
32#include "net.h"
33#include "isa.h"
34#include "pci.h"
35#include "boards.h"
271dd5e0 36#include "fw_cfg.h"
7fa9ae1a 37#include "escc.h"
977e1244 38#include "ide.h"
3cbee15b 39
e4bcb14c 40#define MAX_IDE_BUS 2
a748ab6d 41#define VGA_BIOS_SIZE 65536
271dd5e0
BS
42#define CFG_ADDR 0xf0000510
43
3cbee15b
JM
44/* temporary frame buffer OSI calls for the video.x driver. The right
45 solution is to modify the driver to use VGA PCI I/Os */
46/* XXX: to be removed. This is no way related to emulation */
47static int vga_osi_call (CPUState *env)
48{
49 static int vga_vbl_enabled;
50 int linesize;
51
b11ebf64
BS
52#if 0
53 printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
54#endif
3cbee15b
JM
55
56 /* same handler as PearPC, coming from the original MOL video
57 driver. */
58 switch(env->gpr[5]) {
59 case 4:
60 break;
61 case 28: /* set_vmode */
62 if (env->gpr[6] != 1 || env->gpr[7] != 0)
63 env->gpr[3] = 1;
64 else
65 env->gpr[3] = 0;
66 break;
67 case 29: /* get_vmode_info */
68 if (env->gpr[6] != 0) {
69 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
70 env->gpr[3] = 1;
71 break;
72 }
73 }
74 env->gpr[3] = 0;
75 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
76 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
77 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
78 env->gpr[7] = 85 << 16; /* refresh rate */
79 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
80 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
81 linesize = (linesize + 3) & ~3;
82 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
83 break;
84 case 31: /* set_video power */
85 env->gpr[3] = 0;
86 break;
87 case 39: /* video_ctrl */
88 if (env->gpr[6] == 0 || env->gpr[6] == 1)
89 vga_vbl_enabled = env->gpr[6];
90 env->gpr[3] = 0;
91 break;
92 case 47:
93 break;
94 case 59: /* set_color */
95 /* R6 = index, R7 = RGB */
96 env->gpr[3] = 0;
97 break;
98 case 64: /* get color */
99 /* R6 = index */
100 env->gpr[3] = 0;
101 break;
102 case 116: /* set hwcursor */
103 /* R6 = x, R7 = y, R8 = visible, R9 = data */
104 break;
105 default:
b11ebf64 106 fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
aae9366a 107 ppc_dump_gpr(env, 5));
3cbee15b
JM
108 break;
109 }
110
111 return 1; /* osi_call handled */
112}
113
513f789f
BS
114static int fw_cfg_boot_set(void *opaque, const char *boot_device)
115{
116 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
117 return 0;
118}
119
fbe1b595 120static void ppc_heathrow_init (ram_addr_t ram_size,
3023f332 121 const char *boot_device,
3cbee15b
JM
122 const char *kernel_filename,
123 const char *kernel_cmdline,
124 const char *initrd_filename,
125 const char *cpu_model)
126{
aaed909a 127 CPUState *env = NULL, *envs[MAX_CPUS];
5cea8590 128 char *filename;
3cbee15b 129 qemu_irq *pic, **heathrow_irqs;
3cbee15b 130 int linux_boot, i;
b584726d 131 ram_addr_t ram_offset, bios_offset, vga_bios_offset;
7373048c
BS
132 uint32_t kernel_base, initrd_base;
133 int32_t kernel_size, initrd_size;
3cbee15b
JM
134 PCIBus *pci_bus;
135 MacIONVRAMState *nvr;
136 int vga_bios_size, bios_size;
3cbee15b 137 int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
7fa9ae1a 138 int escc_mem_index, ide_mem_index[2];
513f789f 139 uint16_t ppc_boot_device;
e4bcb14c 140 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
751c6a17 141 DriveInfo *dinfo;
271dd5e0 142 void *fw_cfg;
28ce5ce6 143 void *dbdma;
44654490 144 uint8_t *vga_bios_ptr;
3cbee15b
JM
145
146 linux_boot = (kernel_filename != NULL);
147
148 /* init CPUs */
3cbee15b 149 if (cpu_model == NULL)
f2fde45a 150 cpu_model = "G3";
3cbee15b 151 for (i = 0; i < smp_cpus; i++) {
aaed909a
FB
152 env = cpu_init(cpu_model);
153 if (!env) {
154 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
155 exit(1);
156 }
b0fb43d8
AJ
157 /* Set time-base frequency to 16.6 Mhz */
158 cpu_ppc_tb_init(env, 16600000UL);
3cbee15b 159 env->osi_call = vga_osi_call;
a08d4367 160 qemu_register_reset(&cpu_ppc_reset, env);
3cbee15b
JM
161 envs[i] = env;
162 }
163
164 /* allocate RAM */
6b4079f8
AJ
165 if (ram_size > (2047 << 20)) {
166 fprintf(stderr,
167 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
168 ((unsigned int)ram_size / (1 << 20)));
169 exit(1);
170 }
171
a748ab6d
AJ
172 ram_offset = qemu_ram_alloc(ram_size);
173 cpu_register_physical_memory(0, ram_size, ram_offset);
174
3cbee15b 175 /* allocate and load BIOS */
a748ab6d 176 bios_offset = qemu_ram_alloc(BIOS_SIZE);
3cbee15b 177 if (bios_name == NULL)
992e5acd 178 bios_name = PROM_FILENAME;
5cea8590 179 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
992e5acd
BS
180 cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
181
182 /* Load OpenBIOS (ELF) */
5cea8590
PB
183 if (filename) {
184 bios_size = load_elf(filename, 0, NULL, NULL, NULL);
185 qemu_free(filename);
186 } else {
187 bios_size = -1;
188 }
3cbee15b 189 if (bios_size < 0 || bios_size > BIOS_SIZE) {
5cea8590 190 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
3cbee15b
JM
191 exit(1);
192 }
3cbee15b
JM
193
194 /* allocate and load VGA BIOS */
a748ab6d 195 vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
44654490 196 vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
5cea8590
PB
197 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
198 if (filename) {
199 vga_bios_size = load_image(filename, vga_bios_ptr + 8);
200 qemu_free(filename);
201 } else {
202 vga_bios_size = -1;
203 }
3cbee15b
JM
204 if (vga_bios_size < 0) {
205 /* if no bios is present, we can still work */
5cea8590
PB
206 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
207 VGABIOS_FILENAME);
3cbee15b
JM
208 vga_bios_size = 0;
209 } else {
210 /* set a specific header (XXX: find real Apple format for NDRV
211 drivers) */
44654490
PB
212 vga_bios_ptr[0] = 'N';
213 vga_bios_ptr[1] = 'D';
214 vga_bios_ptr[2] = 'R';
215 vga_bios_ptr[3] = 'V';
216 cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
3cbee15b 217 vga_bios_size += 8;
a7b022e0
AG
218
219 /* Round to page boundary */
220 vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
221 TARGET_PAGE_MASK;
3cbee15b 222 }
3cbee15b
JM
223
224 if (linux_boot) {
36bee1e3 225 uint64_t lowaddr = 0;
3cbee15b 226 kernel_base = KERNEL_LOAD_ADDR;
36bee1e3
AJ
227 /* Now we can load the kernel. The first step tries to load the kernel
228 supposing PhysAddr = 0x00000000. If that was wrong the kernel is
229 loaded again, the new PhysAddr being computed from lowaddr. */
230 kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
231 if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
232 kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
660f11be 233 NULL, NULL, NULL);
36bee1e3 234 }
52f163b7
BS
235 if (kernel_size < 0)
236 kernel_size = load_aout(kernel_filename, kernel_base,
237 ram_size - kernel_base);
238 if (kernel_size < 0)
239 kernel_size = load_image_targphys(kernel_filename,
240 kernel_base,
241 ram_size - kernel_base);
3cbee15b 242 if (kernel_size < 0) {
2ac71179 243 hw_error("qemu: could not load kernel '%s'\n",
3cbee15b
JM
244 kernel_filename);
245 exit(1);
246 }
247 /* load initrd */
248 if (initrd_filename) {
249 initrd_base = INITRD_LOAD_ADDR;
dcac9679
PB
250 initrd_size = load_image_targphys(initrd_filename, initrd_base,
251 ram_size - initrd_base);
3cbee15b 252 if (initrd_size < 0) {
2ac71179
PB
253 hw_error("qemu: could not load initial ram disk '%s'\n",
254 initrd_filename);
3cbee15b
JM
255 exit(1);
256 }
257 } else {
258 initrd_base = 0;
259 initrd_size = 0;
260 }
6ac0e82d 261 ppc_boot_device = 'm';
3cbee15b
JM
262 } else {
263 kernel_base = 0;
264 kernel_size = 0;
265 initrd_base = 0;
266 initrd_size = 0;
28c5af54 267 ppc_boot_device = '\0';
0d913fdb 268 for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54 269 /* TOFIX: for now, the second IDE channel is not properly
0d913fdb 270 * used by OHW. The Mac floppy disk are not emulated.
28c5af54
JM
271 * For now, OHW cannot boot from the network.
272 */
273#if 0
0d913fdb
JM
274 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
275 ppc_boot_device = boot_device[i];
28c5af54 276 break;
0d913fdb 277 }
28c5af54 278#else
0d913fdb
JM
279 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
280 ppc_boot_device = boot_device[i];
28c5af54 281 break;
0d913fdb 282 }
28c5af54
JM
283#endif
284 }
285 if (ppc_boot_device == '\0') {
8a901def 286 fprintf(stderr, "No valid boot device for G3 Beige machine\n");
28c5af54
JM
287 exit(1);
288 }
3cbee15b
JM
289 }
290
291 isa_mem_base = 0x80000000;
aae9366a 292
3cbee15b
JM
293 /* Register 2 MB of ISA IO space */
294 isa_mmio_init(0xfe000000, 0x00200000);
295
296 /* XXX: we register only 1 output pin for heathrow PIC */
297 heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
298 heathrow_irqs[0] =
299 qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
300 /* Connect the heathrow PIC outputs to the 6xx bus */
301 for (i = 0; i < smp_cpus; i++) {
302 switch (PPC_INPUT(env)) {
303 case PPC_FLAGS_INPUT_6xx:
304 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
305 heathrow_irqs[i][0] =
306 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
307 break;
308 default:
2ac71179 309 hw_error("Bus model not supported on OldWorld Mac machine\n");
3cbee15b
JM
310 }
311 }
312
313 /* init basic PC hardware */
314 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
2ac71179 315 hw_error("Only 6xx bus is supported on heathrow machine\n");
3cbee15b
JM
316 }
317 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
318 pci_bus = pci_grackle_init(0xfec00000, pic);
fbe1b595 319 pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
aae9366a 320
aeeb69c7 321 escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
7fa9ae1a 322 serial_hds[1], ESCC_CLOCK, 4);
aae9366a 323
cb457d76 324 for(i = 0; i < nb_nics; i++)
5607c388 325 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
0d913fdb 326
e4bcb14c
TS
327
328 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
329 fprintf(stderr, "qemu: too many IDE bus\n");
330 exit(1);
331 }
bd4524ed
AJ
332
333 /* First IDE channel is a MAC IDE on the MacIO bus */
751c6a17
GH
334 dinfo = drive_get(IF_IDE, 0, 0);
335 hd[0] = dinfo ? dinfo->bdrv : NULL;
336 dinfo = drive_get(IF_IDE, 0, 1);
337 hd[1] = dinfo ? dinfo->bdrv : NULL;
bd4524ed
AJ
338 dbdma = DBDMA_init(&dbdma_mem_index);
339 ide_mem_index[0] = -1;
340 ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
e4bcb14c 341
bd4524ed 342 /* Second IDE channel is a CMD646 on the PCI bus */
751c6a17
GH
343 dinfo = drive_get(IF_IDE, 1, 0);
344 hd[0] = dinfo ? dinfo->bdrv : NULL;
345 dinfo = drive_get(IF_IDE, 1, 1);
346 hd[1] = dinfo ? dinfo->bdrv : NULL;
bd4524ed
AJ
347 hd[3] = hd[2] = NULL;
348 pci_cmd646_ide_init(pci_bus, hd, 0);
3cbee15b
JM
349
350 /* cuda also initialize ADB */
351 cuda_init(&cuda_mem_index, pic[0x12]);
352
353 adb_kbd_init(&adb_bus);
354 adb_mouse_init(&adb_bus);
aae9366a 355
68af3f24 356 nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
3cbee15b
JM
357 pmac_format_nvram_partition(nvr, 0x2000);
358
4ebcf884
BS
359 macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
360 dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
361 escc_mem_index);
3cbee15b
JM
362
363 if (usb_enabled) {
364 usb_ohci_init_pci(pci_bus, 3, -1);
365 }
366
367 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
368 graphic_depth = 15;
369
3cbee15b
JM
370 /* No PCI init: the BIOS will do it */
371
271dd5e0
BS
372 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
373 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
374 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
375 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
513f789f
BS
376 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
377 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
378 if (kernel_cmdline) {
379 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
380 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
381 } else {
382 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
383 }
384 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
385 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
386 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
7f1aec5f
LV
387
388 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
389 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
390 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
391
513f789f 392 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
3cbee15b
JM
393}
394
f80f9ec9 395static QEMUMachine heathrow_machine = {
4d7ca41e 396 .name = "g3beige",
4b32e168
AL
397 .desc = "Heathrow based PowerMAC",
398 .init = ppc_heathrow_init,
3d878caa 399 .max_cpus = MAX_CPUS,
0c257437 400 .is_default = 1,
3cbee15b 401};
f80f9ec9
AL
402
403static void heathrow_machine_init(void)
404{
405 qemu_register_machine(&heathrow_machine);
406}
407
408machine_init(heathrow_machine_init);
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