]>
Commit | Line | Data |
---|---|---|
3cbee15b | 1 | /* |
4d7ca41e | 2 | * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator |
3cbee15b JM |
3 | * |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "ppc.h" | |
3cbee15b | 27 | #include "ppc_mac.h" |
28ce5ce6 | 28 | #include "mac_dbdma.h" |
87ecb68b PB |
29 | #include "nvram.h" |
30 | #include "pc.h" | |
31 | #include "sysemu.h" | |
32 | #include "net.h" | |
33 | #include "isa.h" | |
34 | #include "pci.h" | |
35 | #include "boards.h" | |
271dd5e0 | 36 | #include "fw_cfg.h" |
7fa9ae1a | 37 | #include "escc.h" |
3cbee15b | 38 | |
e4bcb14c | 39 | #define MAX_IDE_BUS 2 |
a748ab6d | 40 | #define VGA_BIOS_SIZE 65536 |
271dd5e0 BS |
41 | #define CFG_ADDR 0xf0000510 |
42 | ||
3cbee15b JM |
43 | /* temporary frame buffer OSI calls for the video.x driver. The right |
44 | solution is to modify the driver to use VGA PCI I/Os */ | |
45 | /* XXX: to be removed. This is no way related to emulation */ | |
46 | static int vga_osi_call (CPUState *env) | |
47 | { | |
48 | static int vga_vbl_enabled; | |
49 | int linesize; | |
50 | ||
aae9366a | 51 | // printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5)); |
3cbee15b JM |
52 | |
53 | /* same handler as PearPC, coming from the original MOL video | |
54 | driver. */ | |
55 | switch(env->gpr[5]) { | |
56 | case 4: | |
57 | break; | |
58 | case 28: /* set_vmode */ | |
59 | if (env->gpr[6] != 1 || env->gpr[7] != 0) | |
60 | env->gpr[3] = 1; | |
61 | else | |
62 | env->gpr[3] = 0; | |
63 | break; | |
64 | case 29: /* get_vmode_info */ | |
65 | if (env->gpr[6] != 0) { | |
66 | if (env->gpr[6] != 1 || env->gpr[7] != 0) { | |
67 | env->gpr[3] = 1; | |
68 | break; | |
69 | } | |
70 | } | |
71 | env->gpr[3] = 0; | |
72 | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ | |
73 | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ | |
74 | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ | |
75 | env->gpr[7] = 85 << 16; /* refresh rate */ | |
76 | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ | |
77 | linesize = ((graphic_depth + 7) >> 3) * graphic_width; | |
78 | linesize = (linesize + 3) & ~3; | |
79 | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ | |
80 | break; | |
81 | case 31: /* set_video power */ | |
82 | env->gpr[3] = 0; | |
83 | break; | |
84 | case 39: /* video_ctrl */ | |
85 | if (env->gpr[6] == 0 || env->gpr[6] == 1) | |
86 | vga_vbl_enabled = env->gpr[6]; | |
87 | env->gpr[3] = 0; | |
88 | break; | |
89 | case 47: | |
90 | break; | |
91 | case 59: /* set_color */ | |
92 | /* R6 = index, R7 = RGB */ | |
93 | env->gpr[3] = 0; | |
94 | break; | |
95 | case 64: /* get color */ | |
96 | /* R6 = index */ | |
97 | env->gpr[3] = 0; | |
98 | break; | |
99 | case 116: /* set hwcursor */ | |
100 | /* R6 = x, R7 = y, R8 = visible, R9 = data */ | |
101 | break; | |
102 | default: | |
aae9366a JM |
103 | fprintf(stderr, "unsupported OSI call R5=" REGX "\n", |
104 | ppc_dump_gpr(env, 5)); | |
3cbee15b JM |
105 | break; |
106 | } | |
107 | ||
108 | return 1; /* osi_call handled */ | |
109 | } | |
110 | ||
513f789f BS |
111 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
112 | { | |
113 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
114 | return 0; | |
115 | } | |
116 | ||
fbe1b595 | 117 | static void ppc_heathrow_init (ram_addr_t ram_size, |
3023f332 | 118 | const char *boot_device, |
3cbee15b JM |
119 | const char *kernel_filename, |
120 | const char *kernel_cmdline, | |
121 | const char *initrd_filename, | |
122 | const char *cpu_model) | |
123 | { | |
aaed909a | 124 | CPUState *env = NULL, *envs[MAX_CPUS]; |
3cbee15b JM |
125 | char buf[1024]; |
126 | qemu_irq *pic, **heathrow_irqs; | |
3cbee15b | 127 | int linux_boot, i; |
b584726d | 128 | ram_addr_t ram_offset, bios_offset, vga_bios_offset; |
7373048c BS |
129 | uint32_t kernel_base, initrd_base; |
130 | int32_t kernel_size, initrd_size; | |
3cbee15b JM |
131 | PCIBus *pci_bus; |
132 | MacIONVRAMState *nvr; | |
133 | int vga_bios_size, bios_size; | |
3cbee15b | 134 | int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index; |
7fa9ae1a | 135 | int escc_mem_index, ide_mem_index[2]; |
513f789f | 136 | uint16_t ppc_boot_device; |
e4bcb14c TS |
137 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
138 | int index; | |
271dd5e0 | 139 | void *fw_cfg; |
28ce5ce6 | 140 | void *dbdma; |
44654490 | 141 | uint8_t *vga_bios_ptr; |
3cbee15b JM |
142 | |
143 | linux_boot = (kernel_filename != NULL); | |
144 | ||
145 | /* init CPUs */ | |
3cbee15b | 146 | if (cpu_model == NULL) |
f2fde45a | 147 | cpu_model = "G3"; |
3cbee15b | 148 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
149 | env = cpu_init(cpu_model); |
150 | if (!env) { | |
151 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
152 | exit(1); | |
153 | } | |
b0fb43d8 AJ |
154 | /* Set time-base frequency to 16.6 Mhz */ |
155 | cpu_ppc_tb_init(env, 16600000UL); | |
3cbee15b JM |
156 | env->osi_call = vga_osi_call; |
157 | qemu_register_reset(&cpu_ppc_reset, env); | |
3cbee15b JM |
158 | envs[i] = env; |
159 | } | |
160 | ||
161 | /* allocate RAM */ | |
6b4079f8 AJ |
162 | if (ram_size > (2047 << 20)) { |
163 | fprintf(stderr, | |
164 | "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", | |
165 | ((unsigned int)ram_size / (1 << 20))); | |
166 | exit(1); | |
167 | } | |
168 | ||
a748ab6d AJ |
169 | ram_offset = qemu_ram_alloc(ram_size); |
170 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
171 | ||
3cbee15b | 172 | /* allocate and load BIOS */ |
a748ab6d | 173 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
3cbee15b | 174 | if (bios_name == NULL) |
992e5acd | 175 | bios_name = PROM_FILENAME; |
3cbee15b | 176 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
992e5acd BS |
177 | cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); |
178 | ||
179 | /* Load OpenBIOS (ELF) */ | |
180 | bios_size = load_elf(buf, 0, NULL, NULL, NULL); | |
3cbee15b | 181 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
2ac71179 | 182 | hw_error("qemu: could not load PowerPC bios '%s'\n", buf); |
3cbee15b JM |
183 | exit(1); |
184 | } | |
3cbee15b JM |
185 | |
186 | /* allocate and load VGA BIOS */ | |
a748ab6d | 187 | vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE); |
44654490 | 188 | vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset); |
3cbee15b | 189 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
44654490 | 190 | vga_bios_size = load_image(buf, vga_bios_ptr + 8); |
3cbee15b JM |
191 | if (vga_bios_size < 0) { |
192 | /* if no bios is present, we can still work */ | |
193 | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf); | |
194 | vga_bios_size = 0; | |
195 | } else { | |
196 | /* set a specific header (XXX: find real Apple format for NDRV | |
197 | drivers) */ | |
44654490 PB |
198 | vga_bios_ptr[0] = 'N'; |
199 | vga_bios_ptr[1] = 'D'; | |
200 | vga_bios_ptr[2] = 'R'; | |
201 | vga_bios_ptr[3] = 'V'; | |
202 | cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size); | |
3cbee15b JM |
203 | vga_bios_size += 8; |
204 | } | |
3cbee15b JM |
205 | |
206 | if (linux_boot) { | |
36bee1e3 | 207 | uint64_t lowaddr = 0; |
3cbee15b | 208 | kernel_base = KERNEL_LOAD_ADDR; |
36bee1e3 AJ |
209 | /* Now we can load the kernel. The first step tries to load the kernel |
210 | supposing PhysAddr = 0x00000000. If that was wrong the kernel is | |
211 | loaded again, the new PhysAddr being computed from lowaddr. */ | |
212 | kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL); | |
213 | if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) { | |
214 | kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr, | |
215 | NULL, 0, NULL); | |
216 | } | |
52f163b7 BS |
217 | if (kernel_size < 0) |
218 | kernel_size = load_aout(kernel_filename, kernel_base, | |
219 | ram_size - kernel_base); | |
220 | if (kernel_size < 0) | |
221 | kernel_size = load_image_targphys(kernel_filename, | |
222 | kernel_base, | |
223 | ram_size - kernel_base); | |
3cbee15b | 224 | if (kernel_size < 0) { |
2ac71179 | 225 | hw_error("qemu: could not load kernel '%s'\n", |
3cbee15b JM |
226 | kernel_filename); |
227 | exit(1); | |
228 | } | |
229 | /* load initrd */ | |
230 | if (initrd_filename) { | |
231 | initrd_base = INITRD_LOAD_ADDR; | |
dcac9679 PB |
232 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
233 | ram_size - initrd_base); | |
3cbee15b | 234 | if (initrd_size < 0) { |
2ac71179 PB |
235 | hw_error("qemu: could not load initial ram disk '%s'\n", |
236 | initrd_filename); | |
3cbee15b JM |
237 | exit(1); |
238 | } | |
239 | } else { | |
240 | initrd_base = 0; | |
241 | initrd_size = 0; | |
242 | } | |
6ac0e82d | 243 | ppc_boot_device = 'm'; |
3cbee15b JM |
244 | } else { |
245 | kernel_base = 0; | |
246 | kernel_size = 0; | |
247 | initrd_base = 0; | |
248 | initrd_size = 0; | |
28c5af54 | 249 | ppc_boot_device = '\0'; |
0d913fdb | 250 | for (i = 0; boot_device[i] != '\0'; i++) { |
28c5af54 | 251 | /* TOFIX: for now, the second IDE channel is not properly |
0d913fdb | 252 | * used by OHW. The Mac floppy disk are not emulated. |
28c5af54 JM |
253 | * For now, OHW cannot boot from the network. |
254 | */ | |
255 | #if 0 | |
0d913fdb JM |
256 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
257 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 258 | break; |
0d913fdb | 259 | } |
28c5af54 | 260 | #else |
0d913fdb JM |
261 | if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { |
262 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 263 | break; |
0d913fdb | 264 | } |
28c5af54 JM |
265 | #endif |
266 | } | |
267 | if (ppc_boot_device == '\0') { | |
8a901def | 268 | fprintf(stderr, "No valid boot device for G3 Beige machine\n"); |
28c5af54 JM |
269 | exit(1); |
270 | } | |
3cbee15b JM |
271 | } |
272 | ||
273 | isa_mem_base = 0x80000000; | |
aae9366a | 274 | |
3cbee15b JM |
275 | /* Register 2 MB of ISA IO space */ |
276 | isa_mmio_init(0xfe000000, 0x00200000); | |
277 | ||
278 | /* XXX: we register only 1 output pin for heathrow PIC */ | |
279 | heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); | |
280 | heathrow_irqs[0] = | |
281 | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); | |
282 | /* Connect the heathrow PIC outputs to the 6xx bus */ | |
283 | for (i = 0; i < smp_cpus; i++) { | |
284 | switch (PPC_INPUT(env)) { | |
285 | case PPC_FLAGS_INPUT_6xx: | |
286 | heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); | |
287 | heathrow_irqs[i][0] = | |
288 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; | |
289 | break; | |
290 | default: | |
2ac71179 | 291 | hw_error("Bus model not supported on OldWorld Mac machine\n"); |
3cbee15b JM |
292 | } |
293 | } | |
294 | ||
295 | /* init basic PC hardware */ | |
296 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
2ac71179 | 297 | hw_error("Only 6xx bus is supported on heathrow machine\n"); |
3cbee15b JM |
298 | } |
299 | pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); | |
300 | pci_bus = pci_grackle_init(0xfec00000, pic); | |
fbe1b595 | 301 | pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size); |
aae9366a | 302 | |
aeeb69c7 | 303 | escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], |
7fa9ae1a | 304 | serial_hds[1], ESCC_CLOCK, 4); |
aae9366a | 305 | |
cb457d76 AL |
306 | for(i = 0; i < nb_nics; i++) |
307 | pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); | |
0d913fdb | 308 | |
e4bcb14c TS |
309 | |
310 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
311 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
312 | exit(1); | |
313 | } | |
bd4524ed AJ |
314 | |
315 | /* First IDE channel is a MAC IDE on the MacIO bus */ | |
e4bcb14c TS |
316 | index = drive_get_index(IF_IDE, 0, 0); |
317 | if (index == -1) | |
318 | hd[0] = NULL; | |
319 | else | |
320 | hd[0] = drives_table[index].bdrv; | |
321 | index = drive_get_index(IF_IDE, 0, 1); | |
322 | if (index == -1) | |
323 | hd[1] = NULL; | |
324 | else | |
325 | hd[1] = drives_table[index].bdrv; | |
bd4524ed AJ |
326 | dbdma = DBDMA_init(&dbdma_mem_index); |
327 | ide_mem_index[0] = -1; | |
328 | ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); | |
e4bcb14c | 329 | |
bd4524ed | 330 | /* Second IDE channel is a CMD646 on the PCI bus */ |
e4bcb14c TS |
331 | index = drive_get_index(IF_IDE, 1, 0); |
332 | if (index == -1) | |
333 | hd[0] = NULL; | |
334 | else | |
335 | hd[0] = drives_table[index].bdrv; | |
336 | index = drive_get_index(IF_IDE, 1, 1); | |
337 | if (index == -1) | |
338 | hd[1] = NULL; | |
339 | else | |
340 | hd[1] = drives_table[index].bdrv; | |
bd4524ed AJ |
341 | hd[3] = hd[2] = NULL; |
342 | pci_cmd646_ide_init(pci_bus, hd, 0); | |
3cbee15b JM |
343 | |
344 | /* cuda also initialize ADB */ | |
345 | cuda_init(&cuda_mem_index, pic[0x12]); | |
346 | ||
347 | adb_kbd_init(&adb_bus); | |
348 | adb_mouse_init(&adb_bus); | |
aae9366a | 349 | |
68af3f24 | 350 | nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4); |
3cbee15b JM |
351 | pmac_format_nvram_partition(nvr, 0x2000); |
352 | ||
4ebcf884 BS |
353 | macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index, |
354 | dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index, | |
355 | escc_mem_index); | |
3cbee15b JM |
356 | |
357 | if (usb_enabled) { | |
358 | usb_ohci_init_pci(pci_bus, 3, -1); | |
359 | } | |
360 | ||
361 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) | |
362 | graphic_depth = 15; | |
363 | ||
3cbee15b JM |
364 | /* No PCI init: the BIOS will do it */ |
365 | ||
271dd5e0 BS |
366 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
367 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
368 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
369 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); | |
513f789f BS |
370 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
371 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
372 | if (kernel_cmdline) { | |
373 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
374 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
375 | } else { | |
376 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
377 | } | |
378 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
379 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
380 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); | |
381 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
3cbee15b JM |
382 | } |
383 | ||
f80f9ec9 | 384 | static QEMUMachine heathrow_machine = { |
4d7ca41e | 385 | .name = "g3beige", |
4b32e168 AL |
386 | .desc = "Heathrow based PowerMAC", |
387 | .init = ppc_heathrow_init, | |
3d878caa | 388 | .max_cpus = MAX_CPUS, |
3cbee15b | 389 | }; |
f80f9ec9 AL |
390 | |
391 | static void heathrow_machine_init(void) | |
392 | { | |
393 | qemu_register_machine(&heathrow_machine); | |
394 | } | |
395 | ||
396 | machine_init(heathrow_machine_init); |