[qemu.git] / hw / lm32 / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    LM32CPU *cpu = opaque;
    CPUState *cs = CPU(cpu);

    if (level) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(MachineState *machine)
{
    const char *kernel_filename = machine->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * KiB;
    size_t flash_size              = 32 * MiB;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * MiB;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    cpu = LM32_CPU(cpu_create(machine->cpu_type));

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init(serial_hd(1));

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                               &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(MachineState *machine)
{
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * KiB;
    size_t flash_size               = 32 * MiB;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * MiB;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    cpu = LM32_CPU(cpu_create(machine->cpu_type));

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL,
                                         "lm32_uclinux.sdram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init(serial_hd(1));

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                               &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_evr_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "LatticeMico32 EVR32 eval system";
    mc->init = lm32_evr_init;
    mc->is_default = 1;
    mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
}

static const TypeInfo lm32_evr_type = {
    .name = MACHINE_TYPE_NAME("lm32-evr"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_evr_class_init,
};

static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
    mc->init = lm32_uclinux_init;
    mc->is_default = 0;
    mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
}

static const TypeInfo lm32_uclinux_type = {
    .name = MACHINE_TYPE_NAME("lm32-uclinux"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_uclinux_class_init,
};

static void lm32_machine_init(void)
{
    type_register_static(&lm32_evr_type);
    type_register_static(&lm32_uclinux_type);
}

type_init(lm32_machine_init)
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
ea99dde1	20	#include "qemu/osdep.h"
fc0187cb	21	#include "qemu/units.h"
0a094a54	22	#include "qemu/error-report.h"
4771d756 PB	23	#include "qemu-common.h"
4771d756 PB	24	#include "cpu.h"
83c9f4ca PB	25	#include "hw/sysbus.h"
83c9f4ca PB	26	#include "hw/hw.h"
0d09e41a	27	#include "hw/block/flash.h"
bd2be150	28	#include "hw/devices.h"
83c9f4ca PB	29	#include "hw/boards.h"
83c9f4ca PB	30	#include "hw/loader.h"
d821732a	31	#include "elf.h"
47b43a1f PB	32	#include "lm32_hwsetup.h"
47b43a1f PB	33	#include "lm32.h"
022c62cb	34	#include "exec/address-spaces.h"
c2ddaa62	35	#include "sysemu/sysemu.h"
d821732a MW	36
d821732a MW	37	typedef struct {
b1435596	38	LM32CPU *cpu;
a8170e5e AK	39	hwaddr bootstrap_pc;
	40	hwaddr flash_base;
	41	hwaddr hwsetup_base;
	42	hwaddr initrd_base;
d821732a	43	size_t initrd_size;
a8170e5e	44	hwaddr cmdline_base;
d821732a MW	45	} ResetInfo;
	46
	47	static void cpu_irq_handler(void *opaque, int irq, int level)
	48	{
d8ed887b	49	LM32CPU *cpu = opaque;
d8ed887b	50	CPUState *cs = CPU(cpu);
d821732a MW	51
d821732a MW	52	if (level) {
c3affe56	53	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a	54	} else {
d8ed887b	55	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a MW	56	}
	57	}
	58
	59	static void main_cpu_reset(void *opaque)
	60	{
	61	ResetInfo *reset_info = opaque;
b1435596	62	CPULM32State *env = &reset_info->cpu->env;
d821732a	63
b1435596	64	cpu_reset(CPU(reset_info->cpu));
d821732a MW	65
	66	/* init defaults */
	67	env->pc = (uint32_t)reset_info->bootstrap_pc;
	68	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	69	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	70	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	71	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	72	reset_info->initrd_size);
	73	env->eba = reset_info->flash_base;
	74	env->deba = reset_info->flash_base;
	75	}
	76
3ef96221	77	static void lm32_evr_init(MachineState *machine)
d821732a	78	{
3ef96221	79	const char *kernel_filename = machine->kernel_filename;
47dc4fa2	80	LM32CPU *cpu;
93a67402	81	CPULM32State *env;
d821732a	82	DriveInfo *dinfo;
88fa8031 AK	83	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	84	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	85	qemu_irq irq[32];
d821732a MW	86	ResetInfo *reset_info;
	87	int i;
	88
	89	/* memory map */
a8170e5e	90	hwaddr flash_base = 0x04000000;
fc0187cb PMD	91	size_t flash_sector_size = 256 * KiB;
fc0187cb PMD	92	size_t flash_size = 32 * MiB;
a8170e5e	93	hwaddr ram_base = 0x08000000;
fc0187cb	94	size_t ram_size = 64 * MiB;
a8170e5e AK	95	hwaddr timer0_base = 0x80002000;
	96	hwaddr uart0_base = 0x80006000;
	97	hwaddr timer1_base = 0x8000a000;
d821732a MW	98	int uart0_irq = 0;
	99	int timer0_irq = 1;
	100	int timer1_irq = 3;
	101
7267c094	102	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a	103
6e0f9a23	104	cpu = LM32_CPU(cpu_create(machine->cpu_type));
f41152bd	105
47dc4fa2	106	env = &cpu->env;
b1435596	107	reset_info->cpu = cpu;
d821732a MW	108
	109	reset_info->flash_base = flash_base;
	110
b7ccb83f DM	111	memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
b7ccb83f DM	112	ram_size);
88fa8031	113	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	114
d821732a MW	115	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	116	/* Spansion S29NS128P */
cfe5f011	117	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
4be74634	118	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	119	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	120	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	121
d821732a MW	122	/* create irq lines */
d4ef00af	123	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
d821732a MW	124	for (i = 0; i < 32; i++) {
	125	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	126	}
	127
9bca0edb	128	lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
d821732a MW	129	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	130	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	131
	132	/* make sure juart isn't the first chardev */
9bca0edb	133	env->juart_state = lm32_juart_init(serial_hd(1));
d821732a MW	134
	135	reset_info->bootstrap_pc = flash_base;
	136
	137	if (kernel_filename) {
	138	uint64_t entry;
	139	int kernel_size;
	140
4366e1db LM	141	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
4366e1db LM	142	&entry, NULL, NULL,
7ef295ea	143	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	144	reset_info->bootstrap_pc = entry;
	145
	146	if (kernel_size < 0) {
	147	kernel_size = load_image_targphys(kernel_filename, ram_base,
	148	ram_size);
	149	reset_info->bootstrap_pc = ram_base;
	150	}
	151
	152	if (kernel_size < 0) {
0a094a54	153	error_report("could not load kernel '%s'", kernel_filename);
d821732a MW	154	exit(1);
	155	}
	156	}
	157
	158	qemu_register_reset(main_cpu_reset, reset_info);
	159	}
	160
3ef96221	161	static void lm32_uclinux_init(MachineState *machine)
d821732a	162	{
3ef96221 MA	163	const char *kernel_filename = machine->kernel_filename;
	164	const char *kernel_cmdline = machine->kernel_cmdline;
	165	const char *initrd_filename = machine->initrd_filename;
47dc4fa2	166	LM32CPU *cpu;
93a67402	167	CPULM32State *env;
d821732a	168	DriveInfo *dinfo;
88fa8031 AK	169	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	170	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	171	qemu_irq irq[32];
d821732a MW	172	HWSetup *hw;
	173	ResetInfo *reset_info;
	174	int i;
	175
	176	/* memory map */
a8170e5e	177	hwaddr flash_base = 0x04000000;
fc0187cb PMD	178	size_t flash_sector_size = 256 * KiB;
fc0187cb PMD	179	size_t flash_size = 32 * MiB;
a8170e5e	180	hwaddr ram_base = 0x08000000;
fc0187cb	181	size_t ram_size = 64 * MiB;
a8170e5e AK	182	hwaddr uart0_base = 0x80000000;
	183	hwaddr timer0_base = 0x80002000;
	184	hwaddr timer1_base = 0x80010000;
	185	hwaddr timer2_base = 0x80012000;
d821732a MW	186	int uart0_irq = 0;
	187	int timer0_irq = 1;
	188	int timer1_irq = 20;
	189	int timer2_irq = 21;
a8170e5e AK	190	hwaddr hwsetup_base = 0x0bffe000;
	191	hwaddr cmdline_base = 0x0bfff000;
	192	hwaddr initrd_base = 0x08400000;
d821732a MW	193	size_t initrd_max = 0x01000000;
d821732a MW	194
7267c094	195	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a	196
6e0f9a23	197	cpu = LM32_CPU(cpu_create(machine->cpu_type));
f41152bd	198
47dc4fa2	199	env = &cpu->env;
b1435596	200	reset_info->cpu = cpu;
d821732a MW	201
	202	reset_info->flash_base = flash_base;
	203
b7ccb83f DM	204	memory_region_allocate_system_memory(phys_ram, NULL,
b7ccb83f DM	205	"lm32_uclinux.sdram", ram_size);
88fa8031	206	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	207
d821732a MW	208	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	209	/* Spansion S29NS128P */
cfe5f011	210	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
4be74634	211	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	212	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	213	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	214
d821732a MW	215	/* create irq lines */
d4ef00af	216	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
d821732a MW	217	for (i = 0; i < 32; i++) {
	218	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	219	}
	220
9bca0edb	221	lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
d821732a MW	222	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	223	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	224	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	225
	226	/* make sure juart isn't the first chardev */
9bca0edb	227	env->juart_state = lm32_juart_init(serial_hd(1));
d821732a MW	228
	229	reset_info->bootstrap_pc = flash_base;
	230
	231	if (kernel_filename) {
	232	uint64_t entry;
	233	int kernel_size;
	234
4366e1db LM	235	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
4366e1db LM	236	&entry, NULL, NULL,
7ef295ea	237	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	238	reset_info->bootstrap_pc = entry;
	239
	240	if (kernel_size < 0) {
	241	kernel_size = load_image_targphys(kernel_filename, ram_base,
	242	ram_size);
	243	reset_info->bootstrap_pc = ram_base;
	244	}
	245
	246	if (kernel_size < 0) {
0a094a54	247	error_report("could not load kernel '%s'", kernel_filename);
d821732a MW	248	exit(1);
	249	}
	250	}
	251
	252	/* generate a rom with the hardware description */
	253	hw = hwsetup_init();
	254	hwsetup_add_cpu(hw, "LM32", 75000000);
	255	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	256	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	257	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	258	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	259	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	260	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	261	hwsetup_add_trailer(hw);
	262	hwsetup_create_rom(hw, hwsetup_base);
	263	hwsetup_free(hw);
	264
	265	reset_info->hwsetup_base = hwsetup_base;
	266
	267	if (kernel_cmdline && strlen(kernel_cmdline)) {
	268	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	269	kernel_cmdline);
	270	reset_info->cmdline_base = cmdline_base;
	271	}
	272
	273	if (initrd_filename) {
	274	size_t initrd_size;
	275	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	276	initrd_max);
	277	reset_info->initrd_base = initrd_base;
	278	reset_info->initrd_size = initrd_size;
	279	}
	280
	281	qemu_register_reset(main_cpu_reset, reset_info);
	282	}
	283
8a661aea	284	static void lm32_evr_class_init(ObjectClass oc, void data)
d821732a	285	{
8a661aea AF	286	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	287
e264d29d EH	288	mc->desc = "LatticeMico32 EVR32 eval system";
	289	mc->init = lm32_evr_init;
	290	mc->is_default = 1;
6e0f9a23	291	mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
d821732a MW	292	}
d821732a MW	293
8a661aea AF	294	static const TypeInfo lm32_evr_type = {
	295	.name = MACHINE_TYPE_NAME("lm32-evr"),
	296	.parent = TYPE_MACHINE,
	297	.class_init = lm32_evr_class_init,
	298	};
e264d29d	299
8a661aea	300	static void lm32_uclinux_class_init(ObjectClass oc, void data)
e264d29d	301	{
8a661aea AF	302	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	303
e264d29d EH	304	mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
	305	mc->init = lm32_uclinux_init;
	306	mc->is_default = 0;
6e0f9a23	307	mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
e264d29d EH	308	}
e264d29d EH	309
8a661aea AF	310	static const TypeInfo lm32_uclinux_type = {
	311	.name = MACHINE_TYPE_NAME("lm32-uclinux"),
	312	.parent = TYPE_MACHINE,
	313	.class_init = lm32_uclinux_class_init,
	314	};
	315
	316	static void lm32_machine_init(void)
	317	{
	318	type_register_static(&lm32_evr_type);
	319	type_register_static(&lm32_uclinux_type);
	320	}
	321
0e6aac87	322	type_init(lm32_machine_init)