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target-ppc: Implement "compat" CPU option
[qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
51fb256a 45static const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 72const char *qemu_uname_release;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
d5975363
PB		 95/***********************************************************/
96/* Helper routines for implementing atomic operations. */
97
98/* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
c2764719 102static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 103static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106static int pending_cpus;
107
108/* Make sure everything is in a consistent state for calling fork(). */
109void fork_start(void)
110{
5e5f07e0 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 112 pthread_mutex_lock(&exclusive_lock);
d032d1b4 113 mmap_fork_start();
d5975363
PB		 114}
115
116void fork_end(int child)
117{
d032d1b4 118 mmap_fork_end(child);
d5975363 119 if (child) {
bdc44640 120 CPUState *cpu, *next_cpu;
d5975363
PB		 121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
bdc44640
AF		 123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
d5975363
PB		 128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 130 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 138 }
d5975363
PB		 139}
140
141/* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143static inline void exclusive_idle(void)
144{
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148}
149
150/* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152static inline void start_exclusive(void)
153{
0315c31c
AF		 154 CPUState *other_cpu;
155
d5975363
PB		 156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
bdc44640 161 CPU_FOREACH(other_cpu) {
0315c31c 162 if (other_cpu->running) {
d5975363 163 pending_cpus++;
60a3e17a 164 cpu_exit(other_cpu);
d5975363
PB		 165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170}
171
172/* Finish an exclusive operation. */
173static inline void end_exclusive(void)
174{
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178}
179
180/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 181static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 182{
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
0315c31c 185 cpu->running = true;
d5975363
PB		 186 pthread_mutex_unlock(&exclusive_lock);
187}
188
189/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 190static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 191{
192 pthread_mutex_lock(&exclusive_lock);
0315c31c 193 cpu->running = false;
d5975363
PB		 194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202}
c2764719
PB		 203
204void cpu_list_lock(void)
205{
206 pthread_mutex_lock(&cpu_list_mutex);
207}
208
209void cpu_list_unlock(void)
210{
211 pthread_mutex_unlock(&cpu_list_mutex);
212}
d5975363
PB		 213
214
a541f297
FB		 215#ifdef TARGET_I386
216/***********************************************************/
217/* CPUX86 core interface */
218
05390248 219void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 220{
221}
222
28ab0e2e
FB		 223uint64_t cpu_get_tsc(CPUX86State *env)
224{
225 return cpu_get_real_ticks();
226}
227
5fafdf24 228static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 229 int flags)
6dbad63e 230{
f4beb510 231 unsigned int e1, e2;
53a5960a 232 uint32_t *p;
6dbad63e
FB		 233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 235 e2 |= flags;
53a5960a 236 p = ptr;
d538e8f5 237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
f4beb510
FB		 239}
240
e441570f 241static uint64_t *idt_table;
eb38c52c 242#ifdef TARGET_X86_64
d2fd1af7
FB		 243static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
f4beb510 245{
4dbc422b 246 uint32_t *p, e1, e2;
f4beb510
FB		 247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 249 p = ptr;
4dbc422b
FB		 250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
6dbad63e 254}
d2fd1af7
FB		 255/* only dpl matters as we do only user space emulation */
256static void set_idt(int n, unsigned int dpl)
257{
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259}
260#else
d2fd1af7
FB		 261static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263{
4dbc422b 264 uint32_t *p, e1, e2;
d2fd1af7
FB		 265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
4dbc422b
FB		 268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
d2fd1af7
FB		 270}
271
f4beb510
FB		 272/* only dpl matters as we do only user space emulation */
273static void set_idt(int n, unsigned int dpl)
274{
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276}
d2fd1af7 277#endif
31e31b8a 278
89e957e7 279void cpu_loop(CPUX86State *env)
1b6b029e 280{
db6b81d4 281 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 282 int trapnr;
992f48a0 283 abi_ulong pc;
c227f099 284 target_siginfo_t info;
851e67a1 285
1b6b029e 286 for(;;) {
bc8a22cc 287 trapnr = cpu_x86_exec(env);
bc8a22cc 288 switch(trapnr) {
f4beb510 289 case 0x80:
d2fd1af7 290 /* linux syscall from int $0x80 */
5fafdf24
TS		 291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
f4beb510
FB		 293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
5945cfcb
PM		 298 env->regs[R_EBP],
299 0, 0);
f4beb510 300 break;
d2fd1af7
FB		 301#ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
5ba18547 303 /* linux syscall from syscall instruction */
d2fd1af7
FB		 304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
5945cfcb
PM		 311 env->regs[9],
312 0, 0);
d2fd1af7
FB		 313 env->eip = env->exception_next_eip;
314 break;
315#endif
f4beb510
FB		 316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
624f7979 322 queue_signal(env, info.si_signo, &info);
f4beb510 323 break;
1b6b029e 324 case EXCP0D_GPF:
d2fd1af7 325 /* XXX: potential problem if ABI32 */
84409ddb 326#ifndef TARGET_X86_64
851e67a1 327 if (env->eflags & VM_MASK) {
89e957e7 328 handle_vm86_fault(env);
84409ddb
JM		 329 } else
330#endif
331 {
f4beb510
FB		 332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
624f7979 336 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 337 }
338 break;
b689bc57
FB		 339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 346 info._sifields._sigfault._addr = env->cr[2];
624f7979 347 queue_signal(env, info.si_signo, &info);
b689bc57 348 break;
9de5e440 349 case EXCP00_DIVZ:
84409ddb 350#ifndef TARGET_X86_64
bc8a22cc 351 if (env->eflags & VM_MASK) {
447db213 352 handle_vm86_trap(env, trapnr);
84409ddb
JM		 353 } else
354#endif
355 {
bc8a22cc
FB		 356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
624f7979 361 queue_signal(env, info.si_signo, &info);
bc8a22cc 362 }
9de5e440 363 break;
01df040b 364 case EXCP01_DB:
447db213 365 case EXCP03_INT3:
84409ddb 366#ifndef TARGET_X86_64
447db213
FB		 367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
447db213
FB		 372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
01df040b 374 if (trapnr == EXCP01_DB) {
447db213
FB		 375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
624f7979 381 queue_signal(env, info.si_signo, &info);
447db213
FB		 382 }
383 break;
9de5e440
FB		 384 case EXCP04_INTO:
385 case EXCP05_BOUND:
84409ddb 386#ifndef TARGET_X86_64
bc8a22cc 387 if (env->eflags & VM_MASK) {
447db213 388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
bc8a22cc
FB		 392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
b689bc57 394 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 395 info._sifields._sigfault._addr = 0;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440
FB		 398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
624f7979 404 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
1fddef4b
FB		 409 case EXCP_DEBUG:
410 {
411 int sig;
412
db6b81d4 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 420 }
421 }
422 break;
1b6b029e 423 default:
970a87a6 424 pc = env->segs[R_CS].base + env->eip;
5fafdf24 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 426 (long)pc, trapnr);
1b6b029e
FB		 427 abort();
428 }
66fb9763 429 process_pending_signals(env);
1b6b029e
FB		 430 }
431}
b346ff46
FB		 432#endif
433
434#ifdef TARGET_ARM
435
d8fd2954
PB		 436#define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444#define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
1861c454
PM		 452#ifdef TARGET_ABI32
453/* Commpage handling -- there is no commpage for AArch64 */
454
97cc7560
DDAG		 455/*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470{
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 486 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
abf1172f 491 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
abf1172f 496 env->exception.vaddress = addr;
97cc7560
DDAG		 497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
abf1172f 504 env->exception.vaddress = addr;
97cc7560
DDAG		 505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 526 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560
DDAG		 527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530}
531
fbb4a2e3
PB		 532/* Handle a jump to the kernel code page. */
533static int
534do_kernel_trap(CPUARMState *env)
535{
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
fbb4a2e3
PB		 550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
d5975363 566 end_exclusive();
fbb4a2e3
PB		 567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
e4fe830b 569 env->regs[0] = env->cp15.tpidrro_el0;
fbb4a2e3 570 break;
97cc7560
DDAG		 571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
fbb4a2e3
PB		 575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587}
588
fa2ef212 589/* Store exclusive handling for AArch32 */
426f5abc
PB		 590static int do_strex(CPUARMState *env)
591{
03d05e2d 592 uint64_t val;
426f5abc
PB		 593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
03d05e2d 598 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 599 goto fail;
600 }
03d05e2d
PM		 601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
426f5abc
PB		 607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
f7001a3b
AJ		 619 default:
620 abort();
426f5abc
PB		 621 }
622 if (segv) {
abf1172f 623 env->exception.vaddress = addr;
426f5abc
PB		 624 goto done;
625 }
426f5abc 626 if (size == 3) {
03d05e2d
PM		 627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
426f5abc 629 if (segv) {
abf1172f 630 env->exception.vaddress = addr + 4;
426f5abc
PB		 631 goto done;
632 }
03d05e2d 633 val = deposit64(val, 32, 32, valhi);
426f5abc 634 }
03d05e2d
PM		 635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
426f5abc
PB		 639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
abf1172f 653 env->exception.vaddress = addr;
426f5abc
PB		 654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 658 segv = put_user_u32(val, addr + 4);
426f5abc 659 if (segv) {
abf1172f 660 env->exception.vaddress = addr + 4;
426f5abc
PB		 661 goto done;
662 }
663 }
664 rc = 0;
665fail:
725b8a69 666 env->regs[15] += 4;
426f5abc
PB		 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668done:
669 end_exclusive();
670 return segv;
671}
672
b346ff46
FB		 673void cpu_loop(CPUARMState *env)
674{
0315c31c 675 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 676 int trapnr;
677 unsigned int n, insn;
c227f099 678 target_siginfo_t info;
b5ff1b31 679 uint32_t addr;
3b46e624 680
b346ff46 681 for(;;) {
0315c31c 682 cpu_exec_start(cs);
b346ff46 683 trapnr = cpu_arm_exec(env);
0315c31c 684 cpu_exec_end(cs);
b346ff46
FB		 685 switch(trapnr) {
686 case EXCP_UDEF:
c6981055 687 {
0429a971 688 TaskState *ts = cs->opaque;
c6981055 689 uint32_t opcode;
6d9a42be 690 int rc;
c6981055
FB		 691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
2f619698 694 /* FIXME - what to do if get_user() fails? */
d8fd2954 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 696
6d9a42be
AJ		 697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
c6981055
FB		 699 info.si_signo = SIGILL;
700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
624f7979 703 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
723 info.si_signo = SIGFPE;
724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
624f7979 734 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
c6981055
FB		 752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
b346ff46
FB		 756 break;
757 case EXCP_SWI:
06c949e6 758 case EXCP_BKPT:
b346ff46 759 {
ce4defa0 760 env->eabi = 1;
b346ff46 761 /* system call */
06c949e6
PB		 762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
2f619698 764 /* FIXME - what to do if get_user() fails? */
d8fd2954 765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
2f619698 769 /* FIXME - what to do if get_user() fails? */
d8fd2954 770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
192c7bd9 774 } else {
06c949e6 775 if (env->thumb) {
2f619698 776 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
06c949e6
PB		 779 n = insn & 0xff;
780 } else {
2f619698 781 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
06c949e6
PB		 784 n = insn & 0xffffff;
785 }
192c7bd9
FB		 786 }
787
6f1f31c0 788 if (n == ARM_NR_cacheflush) {
dcfd14b3 789 /* nop */
a4f81979
FB		 790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
3a1363ac 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 794 /* linux syscall */
ce4defa0 795 if (env->thumb || n == 0) {
192c7bd9
FB		 796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
ce4defa0 799 env->eabi = 0;
192c7bd9 800 }
fbb4a2e3
PB		 801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
dcfd14b3 804 /* nop */
fbb4a2e3
PB		 805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
810 default:
811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
812 n);
813 env->regs[0] = -TARGET_ENOSYS;
814 break;
815 }
816 } else {
817 env->regs[0] = do_syscall(env,
818 n,
819 env->regs[0],
820 env->regs[1],
821 env->regs[2],
822 env->regs[3],
823 env->regs[4],
5945cfcb
PM		 824 env->regs[5],
825 0, 0);
fbb4a2e3 826 }
b346ff46
FB		 827 } else {
828 goto error;
829 }
830 }
831 break;
43fff238
FB		 832 case EXCP_INTERRUPT:
833 /* just indicate that signals should be handled asap */
834 break;
abf1172f
PM		 835 case EXCP_STREX:
836 if (!do_strex(env)) {
837 break;
838 }
839 /* fall through for segv */
68016c62
FB		 840 case EXCP_PREFETCH_ABORT:
841 case EXCP_DATA_ABORT:
abf1172f 842 addr = env->exception.vaddress;
68016c62
FB		 843 {
844 info.si_signo = SIGSEGV;
845 info.si_errno = 0;
846 /* XXX: check env->error_code */
847 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 848 info._sifields._sigfault._addr = addr;
624f7979 849 queue_signal(env, info.si_signo, &info);
68016c62
FB		 850 }
851 break;
1fddef4b
FB		 852 case EXCP_DEBUG:
853 {
854 int sig;
855
db6b81d4 856 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 857 if (sig)
858 {
859 info.si_signo = sig;
860 info.si_errno = 0;
861 info.si_code = TARGET_TRAP_BRKPT;
624f7979 862 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 863 }
864 }
865 break;
fbb4a2e3
PB		 866 case EXCP_KERNEL_TRAP:
867 if (do_kernel_trap(env))
868 goto error;
869 break;
b346ff46
FB		 870 default:
871 error:
5fafdf24 872 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 873 trapnr);
878096ee 874 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 875 abort();
876 }
877 process_pending_signals(env);
878 }
879}
880
1861c454
PM		 881#else
882
fa2ef212
MM		 883/*
884 * Handle AArch64 store-release exclusive
885 *
886 * rs = gets the status result of store exclusive
887 * rt = is the register that is stored
888 * rt2 = is the second register store (in STP)
889 *
890 */
891static int do_strex_a64(CPUARMState *env)
892{
893 uint64_t val;
894 int size;
895 bool is_pair;
896 int rc = 1;
897 int segv = 0;
898 uint64_t addr;
899 int rs, rt, rt2;
900
901 start_exclusive();
902 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
903 size = extract32(env->exclusive_info, 0, 2);
904 is_pair = extract32(env->exclusive_info, 2, 1);
905 rs = extract32(env->exclusive_info, 4, 5);
906 rt = extract32(env->exclusive_info, 9, 5);
907 rt2 = extract32(env->exclusive_info, 14, 5);
908
909 addr = env->exclusive_addr;
910
911 if (addr != env->exclusive_test) {
912 goto finish;
913 }
914
915 switch (size) {
916 case 0:
917 segv = get_user_u8(val, addr);
918 break;
919 case 1:
920 segv = get_user_u16(val, addr);
921 break;
922 case 2:
923 segv = get_user_u32(val, addr);
924 break;
925 case 3:
926 segv = get_user_u64(val, addr);
927 break;
928 default:
929 abort();
930 }
931 if (segv) {
abf1172f 932 env->exception.vaddress = addr;
fa2ef212
MM		 933 goto error;
934 }
935 if (val != env->exclusive_val) {
936 goto finish;
937 }
938 if (is_pair) {
939 if (size == 2) {
940 segv = get_user_u32(val, addr + 4);
941 } else {
942 segv = get_user_u64(val, addr + 8);
943 }
944 if (segv) {
abf1172f 945 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 946 goto error;
947 }
948 if (val != env->exclusive_high) {
949 goto finish;
950 }
951 }
2ea5a2ca
JG		 952 /* handle the zero register */
953 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 954 switch (size) {
955 case 0:
956 segv = put_user_u8(val, addr);
957 break;
958 case 1:
959 segv = put_user_u16(val, addr);
960 break;
961 case 2:
962 segv = put_user_u32(val, addr);
963 break;
964 case 3:
965 segv = put_user_u64(val, addr);
966 break;
967 }
968 if (segv) {
969 goto error;
970 }
971 if (is_pair) {
2ea5a2ca
JG		 972 /* handle the zero register */
973 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 974 if (size == 2) {
975 segv = put_user_u32(val, addr + 4);
976 } else {
977 segv = put_user_u64(val, addr + 8);
978 }
979 if (segv) {
abf1172f 980 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 981 goto error;
982 }
983 }
984 rc = 0;
985finish:
986 env->pc += 4;
987 /* rs == 31 encodes a write to the ZR, thus throwing away
988 * the status return. This is rather silly but valid.
989 */
990 if (rs < 31) {
991 env->xregs[rs] = rc;
992 }
993error:
994 /* instruction faulted, PC does not advance */
995 /* either way a strex releases any exclusive lock we have */
996 env->exclusive_addr = -1;
997 end_exclusive();
998 return segv;
999}
1000
1861c454
PM		 1001/* AArch64 main loop */
1002void cpu_loop(CPUARMState *env)
1003{
1004 CPUState *cs = CPU(arm_env_get_cpu(env));
1005 int trapnr, sig;
1006 target_siginfo_t info;
1007 uint32_t addr;
1008
1009 for (;;) {
1010 cpu_exec_start(cs);
1011 trapnr = cpu_arm_exec(env);
1012 cpu_exec_end(cs);
1013
1014 switch (trapnr) {
1015 case EXCP_SWI:
1016 env->xregs[0] = do_syscall(env,
1017 env->xregs[8],
1018 env->xregs[0],
1019 env->xregs[1],
1020 env->xregs[2],
1021 env->xregs[3],
1022 env->xregs[4],
1023 env->xregs[5],
1024 0, 0);
1025 break;
1026 case EXCP_INTERRUPT:
1027 /* just indicate that signals should be handled asap */
1028 break;
1029 case EXCP_UDEF:
1030 info.si_signo = SIGILL;
1031 info.si_errno = 0;
1032 info.si_code = TARGET_ILL_ILLOPN;
1033 info._sifields._sigfault._addr = env->pc;
1034 queue_signal(env, info.si_signo, &info);
1035 break;
abf1172f
PM		 1036 case EXCP_STREX:
1037 if (!do_strex_a64(env)) {
1038 break;
1039 }
1040 /* fall through for segv */
1861c454 1041 case EXCP_PREFETCH_ABORT:
1861c454 1042 case EXCP_DATA_ABORT:
abf1172f 1043 addr = env->exception.vaddress;
1861c454
PM		 1044 info.si_signo = SIGSEGV;
1045 info.si_errno = 0;
1046 /* XXX: check env->error_code */
1047 info.si_code = TARGET_SEGV_MAPERR;
1048 info._sifields._sigfault._addr = addr;
1049 queue_signal(env, info.si_signo, &info);
1050 break;
1051 case EXCP_DEBUG:
1052 case EXCP_BKPT:
1053 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1054 if (sig) {
1055 info.si_signo = sig;
1056 info.si_errno = 0;
1057 info.si_code = TARGET_TRAP_BRKPT;
1058 queue_signal(env, info.si_signo, &info);
1059 }
1060 break;
1861c454
PM		 1061 default:
1062 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1063 trapnr);
1064 cpu_dump_state(cs, stderr, fprintf, 0);
1065 abort();
1066 }
1067 process_pending_signals(env);
fa2ef212
MM		 1068 /* Exception return on AArch64 always clears the exclusive monitor,
1069 * so any return to running guest code implies this.
1070 * A strex (successful or otherwise) also clears the monitor, so
1071 * we don't need to specialcase EXCP_STREX.
1072 */
1073 env->exclusive_addr = -1;
1861c454
PM		 1074 }
1075}
1076#endif /* ndef TARGET_ABI32 */
1077
b346ff46 1078#endif
1b6b029e 1079
d2fbca94
GX		 1080#ifdef TARGET_UNICORE32
1081
05390248 1082void cpu_loop(CPUUniCore32State *env)
d2fbca94 1083{
0315c31c 1084 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1085 int trapnr;
1086 unsigned int n, insn;
1087 target_siginfo_t info;
1088
1089 for (;;) {
0315c31c 1090 cpu_exec_start(cs);
d2fbca94 1091 trapnr = uc32_cpu_exec(env);
0315c31c 1092 cpu_exec_end(cs);
d2fbca94
GX		 1093 switch (trapnr) {
1094 case UC32_EXCP_PRIV:
1095 {
1096 /* system call */
1097 get_user_u32(insn, env->regs[31] - 4);
1098 n = insn & 0xffffff;
1099
1100 if (n >= UC32_SYSCALL_BASE) {
1101 /* linux syscall */
1102 n -= UC32_SYSCALL_BASE;
1103 if (n == UC32_SYSCALL_NR_set_tls) {
1104 cpu_set_tls(env, env->regs[0]);
1105 env->regs[0] = 0;
1106 } else {
1107 env->regs[0] = do_syscall(env,
1108 n,
1109 env->regs[0],
1110 env->regs[1],
1111 env->regs[2],
1112 env->regs[3],
1113 env->regs[4],
5945cfcb
PM		 1114 env->regs[5],
1115 0, 0);
d2fbca94
GX		 1116 }
1117 } else {
1118 goto error;
1119 }
1120 }
1121 break;
d48813dd
GX		 1122 case UC32_EXCP_DTRAP:
1123 case UC32_EXCP_ITRAP:
d2fbca94
GX		 1124 info.si_signo = SIGSEGV;
1125 info.si_errno = 0;
1126 /* XXX: check env->error_code */
1127 info.si_code = TARGET_SEGV_MAPERR;
1128 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1129 queue_signal(env, info.si_signo, &info);
1130 break;
1131 case EXCP_INTERRUPT:
1132 /* just indicate that signals should be handled asap */
1133 break;
1134 case EXCP_DEBUG:
1135 {
1136 int sig;
1137
db6b81d4 1138 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1139 if (sig) {
1140 info.si_signo = sig;
1141 info.si_errno = 0;
1142 info.si_code = TARGET_TRAP_BRKPT;
1143 queue_signal(env, info.si_signo, &info);
1144 }
1145 }
1146 break;
1147 default:
1148 goto error;
1149 }
1150 process_pending_signals(env);
1151 }
1152
1153error:
1154 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1155 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1156 abort();
1157}
1158#endif
1159
93ac68bc 1160#ifdef TARGET_SPARC
ed23fbd9 1161#define SPARC64_STACK_BIAS 2047
93ac68bc 1162
060366c5
FB		 1163//#define DEBUG_WIN
1164
2623cbaf
FB		 1165/* WARNING: dealing with register windows _is_ complicated. More info
1166 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1167static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1168{
1a14026e 1169 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1170 /* wrap handling : if cwp is on the last window, then we use the
1171 registers 'after' the end */
1a14026e
BS		 1172 if (index < 8 && env->cwp == env->nwindows - 1)
1173 index += 16 * env->nwindows;
060366c5
FB		 1174 return index;
1175}
1176
2623cbaf
FB		 1177/* save the register window 'cwp1' */
1178static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1179{
2623cbaf 1180 unsigned int i;
992f48a0 1181 abi_ulong sp_ptr;
3b46e624 1182
53a5960a 1183 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1184#ifdef TARGET_SPARC64
1185 if (sp_ptr & 3)
1186 sp_ptr += SPARC64_STACK_BIAS;
1187#endif
060366c5 1188#if defined(DEBUG_WIN)
2daf0284
BS		 1189 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1190 sp_ptr, cwp1);
060366c5 1191#endif
2623cbaf 1192 for(i = 0; i < 16; i++) {
2f619698
FB		 1193 /* FIXME - what to do if put_user() fails? */
1194 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1195 sp_ptr += sizeof(abi_ulong);
2623cbaf 1196 }
060366c5
FB		 1197}
1198
1199static void save_window(CPUSPARCState *env)
1200{
5ef54116 1201#ifndef TARGET_SPARC64
2623cbaf 1202 unsigned int new_wim;
1a14026e
BS		 1203 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1204 ((1LL << env->nwindows) - 1);
1205 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1206 env->wim = new_wim;
5ef54116 1207#else
1a14026e 1208 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1209 env->cansave++;
1210 env->canrestore--;
1211#endif
060366c5
FB		 1212}
1213
1214static void restore_window(CPUSPARCState *env)
1215{
eda52953
BS		 1216#ifndef TARGET_SPARC64
1217 unsigned int new_wim;
1218#endif
1219 unsigned int i, cwp1;
992f48a0 1220 abi_ulong sp_ptr;
3b46e624 1221
eda52953 1222#ifndef TARGET_SPARC64
1a14026e
BS		 1223 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1224 ((1LL << env->nwindows) - 1);
eda52953 1225#endif
3b46e624 1226
060366c5 1227 /* restore the invalid window */
1a14026e 1228 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1229 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1230#ifdef TARGET_SPARC64
1231 if (sp_ptr & 3)
1232 sp_ptr += SPARC64_STACK_BIAS;
1233#endif
060366c5 1234#if defined(DEBUG_WIN)
2daf0284
BS		 1235 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1236 sp_ptr, cwp1);
060366c5 1237#endif
2623cbaf 1238 for(i = 0; i < 16; i++) {
2f619698
FB		 1239 /* FIXME - what to do if get_user() fails? */
1240 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1241 sp_ptr += sizeof(abi_ulong);
2623cbaf 1242 }
5ef54116
FB		 1243#ifdef TARGET_SPARC64
1244 env->canrestore++;
1a14026e
BS		 1245 if (env->cleanwin < env->nwindows - 1)
1246 env->cleanwin++;
5ef54116 1247 env->cansave--;
eda52953
BS		 1248#else
1249 env->wim = new_wim;
5ef54116 1250#endif
060366c5
FB		 1251}
1252
1253static void flush_windows(CPUSPARCState *env)
1254{
1255 int offset, cwp1;
2623cbaf
FB		 1256
1257 offset = 1;
060366c5
FB		 1258 for(;;) {
1259 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1260 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1261#ifndef TARGET_SPARC64
060366c5
FB		 1262 if (env->wim & (1 << cwp1))
1263 break;
eda52953
BS		 1264#else
1265 if (env->canrestore == 0)
1266 break;
1267 env->cansave++;
1268 env->canrestore--;
1269#endif
2623cbaf 1270 save_window_offset(env, cwp1);
060366c5
FB		 1271 offset++;
1272 }
1a14026e 1273 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1274#ifndef TARGET_SPARC64
1275 /* set wim so that restore will reload the registers */
2623cbaf 1276 env->wim = 1 << cwp1;
eda52953 1277#endif
2623cbaf
FB		 1278#if defined(DEBUG_WIN)
1279 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1280#endif
2623cbaf 1281}
060366c5 1282
93ac68bc
FB		 1283void cpu_loop (CPUSPARCState *env)
1284{
878096ee 1285 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1286 int trapnr;
1287 abi_long ret;
c227f099 1288 target_siginfo_t info;
3b46e624 1289
060366c5
FB		 1290 while (1) {
1291 trapnr = cpu_sparc_exec (env);
3b46e624 1292
20132b96
RH		 1293 /* Compute PSR before exposing state. */
1294 if (env->cc_op != CC_OP_FLAGS) {
1295 cpu_get_psr(env);
1296 }
1297
060366c5 1298 switch (trapnr) {
5ef54116 1299#ifndef TARGET_SPARC64
5fafdf24 1300 case 0x88:
060366c5 1301 case 0x90:
5ef54116 1302#else
cb33da57 1303 case 0x110:
5ef54116
FB		 1304 case 0x16d:
1305#endif
060366c5 1306 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1307 env->regwptr[0], env->regwptr[1],
1308 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1309 env->regwptr[4], env->regwptr[5],
1310 0, 0);
2cc20260 1311 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1312#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1313 env->xcc |= PSR_CARRY;
1314#else
060366c5 1315 env->psr |= PSR_CARRY;
27908725 1316#endif
060366c5
FB		 1317 ret = -ret;
1318 } else {
992f48a0 1319#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1320 env->xcc &= ~PSR_CARRY;
1321#else
060366c5 1322 env->psr &= ~PSR_CARRY;
27908725 1323#endif
060366c5
FB		 1324 }
1325 env->regwptr[0] = ret;
1326 /* next instruction */
1327 env->pc = env->npc;
1328 env->npc = env->npc + 4;
1329 break;
1330 case 0x83: /* flush windows */
992f48a0
BS		 1331#ifdef TARGET_ABI32
1332 case 0x103:
1333#endif
2623cbaf 1334 flush_windows(env);
060366c5
FB		 1335 /* next instruction */
1336 env->pc = env->npc;
1337 env->npc = env->npc + 4;
1338 break;
3475187d 1339#ifndef TARGET_SPARC64
060366c5
FB		 1340 case TT_WIN_OVF: /* window overflow */
1341 save_window(env);
1342 break;
1343 case TT_WIN_UNF: /* window underflow */
1344 restore_window(env);
1345 break;
61ff6f58
FB		 1346 case TT_TFAULT:
1347 case TT_DFAULT:
1348 {
59f7182f 1349 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1350 info.si_errno = 0;
1351 /* XXX: check env->error_code */
1352 info.si_code = TARGET_SEGV_MAPERR;
1353 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1354 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1355 }
1356 break;
3475187d 1357#else
5ef54116
FB		 1358 case TT_SPILL: /* window overflow */
1359 save_window(env);
1360 break;
1361 case TT_FILL: /* window underflow */
1362 restore_window(env);
1363 break;
7f84a729
BS		 1364 case TT_TFAULT:
1365 case TT_DFAULT:
1366 {
59f7182f 1367 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1368 info.si_errno = 0;
1369 /* XXX: check env->error_code */
1370 info.si_code = TARGET_SEGV_MAPERR;
1371 if (trapnr == TT_DFAULT)
1372 info._sifields._sigfault._addr = env->dmmuregs[4];
1373 else
8194f35a 1374 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1375 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1376 }
1377 break;
27524dc3 1378#ifndef TARGET_ABI32
5bfb56b2
BS		 1379 case 0x16e:
1380 flush_windows(env);
1381 sparc64_get_context(env);
1382 break;
1383 case 0x16f:
1384 flush_windows(env);
1385 sparc64_set_context(env);
1386 break;
27524dc3 1387#endif
3475187d 1388#endif
48dc41eb
FB		 1389 case EXCP_INTERRUPT:
1390 /* just indicate that signals should be handled asap */
1391 break;
75f22e4e
RH		 1392 case TT_ILL_INSN:
1393 {
1394 info.si_signo = TARGET_SIGILL;
1395 info.si_errno = 0;
1396 info.si_code = TARGET_ILL_ILLOPC;
1397 info._sifields._sigfault._addr = env->pc;
1398 queue_signal(env, info.si_signo, &info);
1399 }
1400 break;
1fddef4b
FB		 1401 case EXCP_DEBUG:
1402 {
1403 int sig;
1404
db6b81d4 1405 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1406 if (sig)
1407 {
1408 info.si_signo = sig;
1409 info.si_errno = 0;
1410 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1411 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1412 }
1413 }
1414 break;
060366c5
FB		 1415 default:
1416 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1417 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1418 exit (1);
1419 }
1420 process_pending_signals (env);
1421 }
93ac68bc
FB		 1422}
1423
1424#endif
1425
67867308 1426#ifdef TARGET_PPC
05390248 1427static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1428{
1429 /* TO FIX */
1430 return 0;
1431}
3b46e624 1432
05390248 1433uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1434{
e3ea6529 1435 return cpu_ppc_get_tb(env);
9fddaa0c 1436}
3b46e624 1437
05390248 1438uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1439{
1440 return cpu_ppc_get_tb(env) >> 32;
1441}
3b46e624 1442
05390248 1443uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1444{
b711de95 1445 return cpu_ppc_get_tb(env);
9fddaa0c 1446}
5fafdf24 1447
05390248 1448uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1449{
a062e36c 1450 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1451}
76a66253 1452
05390248 1453uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1454__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1455
05390248 1456uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1457{
76a66253 1458 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1459}
76a66253 1460
a750fc0b 1461/* XXX: to be fixed */
73b01960 1462int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1463{
1464 return -1;
1465}
1466
73b01960 1467int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1468{
1469 return -1;
1470}
1471
001faf32
BS		 1472#define EXCP_DUMP(env, fmt, ...) \
1473do { \
a0762859 1474 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1475 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1476 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1477 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1478 if (qemu_log_enabled()) { \
a0762859 1479 log_cpu_state(cs, 0); \
eeacee4d 1480 } \
e1833e1f
JM		 1481} while (0)
1482
56f066bb
NF		 1483static int do_store_exclusive(CPUPPCState *env)
1484{
1485 target_ulong addr;
1486 target_ulong page_addr;
27b95bfe 1487 target_ulong val, val2 __attribute__((unused));
56f066bb
NF		 1488 int flags;
1489 int segv = 0;
1490
1491 addr = env->reserve_ea;
1492 page_addr = addr & TARGET_PAGE_MASK;
1493 start_exclusive();
1494 mmap_lock();
1495 flags = page_get_flags(page_addr);
1496 if ((flags & PAGE_READ) == 0) {
1497 segv = 1;
1498 } else {
1499 int reg = env->reserve_info & 0x1f;
1500 int size = (env->reserve_info >> 5) & 0xf;
1501 int stored = 0;
1502
1503 if (addr == env->reserve_addr) {
1504 switch (size) {
1505 case 1: segv = get_user_u8(val, addr); break;
1506 case 2: segv = get_user_u16(val, addr); break;
1507 case 4: segv = get_user_u32(val, addr); break;
1508#if defined(TARGET_PPC64)
1509 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1510 case 16: {
1511 segv = get_user_u64(val, addr);
1512 if (!segv) {
1513 segv = get_user_u64(val2, addr + 8);
1514 }
1515 break;
1516 }
56f066bb
NF		 1517#endif
1518 default: abort();
1519 }
1520 if (!segv && val == env->reserve_val) {
1521 val = env->gpr[reg];
1522 switch (size) {
1523 case 1: segv = put_user_u8(val, addr); break;
1524 case 2: segv = put_user_u16(val, addr); break;
1525 case 4: segv = put_user_u32(val, addr); break;
1526#if defined(TARGET_PPC64)
1527 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1528 case 16: {
1529 if (val2 == env->reserve_val2) {
1530 segv = put_user_u64(val, addr);
1531 if (!segv) {
1532 segv = put_user_u64(val2, addr + 8);
1533 }
1534 }
1535 break;
1536 }
56f066bb
NF		 1537#endif
1538 default: abort();
1539 }
1540 if (!segv) {
1541 stored = 1;
1542 }
1543 }
1544 }
1545 env->crf[0] = (stored << 1) | xer_so;
1546 env->reserve_addr = (target_ulong)-1;
1547 }
1548 if (!segv) {
1549 env->nip += 4;
1550 }
1551 mmap_unlock();
1552 end_exclusive();
1553 return segv;
1554}
1555
67867308
FB		 1556void cpu_loop(CPUPPCState *env)
1557{
0315c31c 1558 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1559 target_siginfo_t info;
61190b14 1560 int trapnr;
9e0e2f96 1561 target_ulong ret;
3b46e624 1562
67867308 1563 for(;;) {
0315c31c 1564 cpu_exec_start(cs);
67867308 1565 trapnr = cpu_ppc_exec(env);
0315c31c 1566 cpu_exec_end(cs);
67867308 1567 switch(trapnr) {
e1833e1f
JM		 1568 case POWERPC_EXCP_NONE:
1569 /* Just go on */
67867308 1570 break;
e1833e1f 1571 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1572 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1573 "Aborting\n");
61190b14 1574 break;
e1833e1f 1575 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1576 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1577 "Aborting\n");
1578 break;
1579 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1580 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1581 env->spr[SPR_DAR]);
1582 /* XXX: check this. Seems bugged */
2be0071f
FB		 1583 switch (env->error_code & 0xFF000000) {
1584 case 0x40000000:
61190b14
FB		 1585 info.si_signo = TARGET_SIGSEGV;
1586 info.si_errno = 0;
1587 info.si_code = TARGET_SEGV_MAPERR;
1588 break;
2be0071f 1589 case 0x04000000:
61190b14
FB		 1590 info.si_signo = TARGET_SIGILL;
1591 info.si_errno = 0;
1592 info.si_code = TARGET_ILL_ILLADR;
1593 break;
2be0071f 1594 case 0x08000000:
61190b14
FB		 1595 info.si_signo = TARGET_SIGSEGV;
1596 info.si_errno = 0;
1597 info.si_code = TARGET_SEGV_ACCERR;
1598 break;
61190b14
FB		 1599 default:
1600 /* Let's send a regular segfault... */
e1833e1f
JM		 1601 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1602 env->error_code);
61190b14
FB		 1603 info.si_signo = TARGET_SIGSEGV;
1604 info.si_errno = 0;
1605 info.si_code = TARGET_SEGV_MAPERR;
1606 break;
1607 }
67867308 1608 info._sifields._sigfault._addr = env->nip;
624f7979 1609 queue_signal(env, info.si_signo, &info);
67867308 1610 break;
e1833e1f 1611 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1612 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1613 "\n", env->spr[SPR_SRR0]);
e1833e1f 1614 /* XXX: check this */
2be0071f
FB		 1615 switch (env->error_code & 0xFF000000) {
1616 case 0x40000000:
61190b14 1617 info.si_signo = TARGET_SIGSEGV;
67867308 1618 info.si_errno = 0;
61190b14
FB		 1619 info.si_code = TARGET_SEGV_MAPERR;
1620 break;
2be0071f
FB		 1621 case 0x10000000:
1622 case 0x08000000:
61190b14
FB		 1623 info.si_signo = TARGET_SIGSEGV;
1624 info.si_errno = 0;
1625 info.si_code = TARGET_SEGV_ACCERR;
1626 break;
1627 default:
1628 /* Let's send a regular segfault... */
e1833e1f
JM		 1629 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1630 env->error_code);
61190b14
FB		 1631 info.si_signo = TARGET_SIGSEGV;
1632 info.si_errno = 0;
1633 info.si_code = TARGET_SEGV_MAPERR;
1634 break;
1635 }
1636 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1637 queue_signal(env, info.si_signo, &info);
67867308 1638 break;
e1833e1f 1639 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1640 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1641 "Aborting\n");
1642 break;
1643 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1644 EXCP_DUMP(env, "Unaligned memory access\n");
1645 /* XXX: check this */
61190b14 1646 info.si_signo = TARGET_SIGBUS;
67867308 1647 info.si_errno = 0;
61190b14
FB		 1648 info.si_code = TARGET_BUS_ADRALN;
1649 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1650 queue_signal(env, info.si_signo, &info);
67867308 1651 break;
e1833e1f
JM		 1652 case POWERPC_EXCP_PROGRAM: /* Program exception */
1653 /* XXX: check this */
61190b14 1654 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1655 case POWERPC_EXCP_FP:
1656 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1657 info.si_signo = TARGET_SIGFPE;
1658 info.si_errno = 0;
1659 switch (env->error_code & 0xF) {
e1833e1f 1660 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1661 info.si_code = TARGET_FPE_FLTOVF;
1662 break;
e1833e1f 1663 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1664 info.si_code = TARGET_FPE_FLTUND;
1665 break;
e1833e1f
JM		 1666 case POWERPC_EXCP_FP_ZX:
1667 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1668 info.si_code = TARGET_FPE_FLTDIV;
1669 break;
e1833e1f 1670 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1671 info.si_code = TARGET_FPE_FLTRES;
1672 break;
e1833e1f 1673 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1674 info.si_code = TARGET_FPE_FLTINV;
1675 break;
7c58044c 1676 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1677 case POWERPC_EXCP_FP_VXISI:
1678 case POWERPC_EXCP_FP_VXIDI:
1679 case POWERPC_EXCP_FP_VXIMZ:
1680 case POWERPC_EXCP_FP_VXVC:
1681 case POWERPC_EXCP_FP_VXSQRT:
1682 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1683 info.si_code = TARGET_FPE_FLTSUB;
1684 break;
1685 default:
e1833e1f
JM		 1686 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1687 env->error_code);
1688 break;
61190b14 1689 }
e1833e1f
JM		 1690 break;
1691 case POWERPC_EXCP_INVAL:
1692 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1693 info.si_signo = TARGET_SIGILL;
1694 info.si_errno = 0;
1695 switch (env->error_code & 0xF) {
e1833e1f 1696 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1697 info.si_code = TARGET_ILL_ILLOPC;
1698 break;
e1833e1f 1699 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1700 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1701 break;
e1833e1f 1702 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1703 info.si_code = TARGET_ILL_PRVREG;
1704 break;
e1833e1f 1705 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1706 info.si_code = TARGET_ILL_COPROC;
1707 break;
1708 default:
e1833e1f
JM		 1709 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1710 env->error_code & 0xF);
61190b14
FB		 1711 info.si_code = TARGET_ILL_ILLADR;
1712 break;
1713 }
1714 break;
e1833e1f
JM		 1715 case POWERPC_EXCP_PRIV:
1716 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1717 info.si_signo = TARGET_SIGILL;
1718 info.si_errno = 0;
1719 switch (env->error_code & 0xF) {
e1833e1f 1720 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1721 info.si_code = TARGET_ILL_PRVOPC;
1722 break;
e1833e1f 1723 case POWERPC_EXCP_PRIV_REG:
61190b14 1724 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1725 break;
61190b14 1726 default:
e1833e1f
JM		 1727 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1728 env->error_code & 0xF);
61190b14
FB		 1729 info.si_code = TARGET_ILL_PRVOPC;
1730 break;
1731 }
1732 break;
e1833e1f 1733 case POWERPC_EXCP_TRAP:
a47dddd7 1734 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1735 break;
61190b14
FB		 1736 default:
1737 /* Should not happen ! */
a47dddd7 1738 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1739 env->error_code);
1740 break;
61190b14
FB		 1741 }
1742 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1743 queue_signal(env, info.si_signo, &info);
67867308 1744 break;
e1833e1f
JM		 1745 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1746 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1747 info.si_signo = TARGET_SIGILL;
67867308 1748 info.si_errno = 0;
61190b14
FB		 1749 info.si_code = TARGET_ILL_COPROC;
1750 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1751 queue_signal(env, info.si_signo, &info);
67867308 1752 break;
e1833e1f 1753 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1754 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1755 "Aborting\n");
61190b14 1756 break;
e1833e1f
JM		 1757 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1758 EXCP_DUMP(env, "No APU instruction allowed\n");
1759 info.si_signo = TARGET_SIGILL;
1760 info.si_errno = 0;
1761 info.si_code = TARGET_ILL_COPROC;
1762 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1763 queue_signal(env, info.si_signo, &info);
61190b14 1764 break;
e1833e1f 1765 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1766 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1767 "Aborting\n");
61190b14 1768 break;
e1833e1f 1769 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1770 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1771 "Aborting\n");
1772 break;
1773 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1774 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1775 "Aborting\n");
1776 break;
1777 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1778 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1782 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1783 "Aborting\n");
1784 break;
e1833e1f
JM		 1785 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1786 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1787 info.si_signo = TARGET_SIGILL;
1788 info.si_errno = 0;
1789 info.si_code = TARGET_ILL_COPROC;
1790 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1791 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1792 break;
1793 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1794 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1795 break;
1796 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1797 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1798 break;
1799 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1800 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1801 break;
1802 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1803 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1804 "Aborting\n");
1805 break;
1806 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1807 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1811 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1812 "Aborting\n");
1813 break;
e1833e1f 1814 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1815 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1819 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1820 "while in user mode. Aborting\n");
1821 break;
e85e7c6e 1822 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1823 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1824 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1825 "while in user mode. Aborting\n");
1826 break;
e1833e1f
JM		 1827 case POWERPC_EXCP_TRACE: /* Trace exception */
1828 /* Nothing to do:
1829 * we use this exception to emulate step-by-step execution mode.
1830 */
1831 break;
e85e7c6e 1832 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1833 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1834 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1835 "while in user mode. Aborting\n");
1836 break;
1837 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1838 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1839 "while in user mode. Aborting\n");
1840 break;
1841 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1842 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1846 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1847 "while in user mode. Aborting\n");
1848 break;
e1833e1f
JM		 1849 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1850 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1851 info.si_signo = TARGET_SIGILL;
1852 info.si_errno = 0;
1853 info.si_code = TARGET_ILL_COPROC;
1854 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1855 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1856 break;
1857 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1858 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1859 "while in user mode. Aborting\n");
1860 break;
1861 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1862 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1863 "Aborting\n");
1864 break;
1865 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1866 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1867 "Aborting\n");
1868 break;
1869 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1870 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1871 break;
1872 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1873 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1874 "while in user-mode. Aborting");
1875 break;
1876 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1877 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1878 "Aborting");
1879 break;
1880 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1881 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1882 "Aborting");
1883 break;
1884 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1885 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1886 break;
1887 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1888 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1889 "not handled\n");
1890 break;
1891 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1892 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1893 "Aborting\n");
1894 break;
1895 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1896 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1897 "Aborting\n");
1898 break;
1899 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1900 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1901 break;
1902 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1903 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1904 break;
1905 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1906 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1907 break;
1908 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1909 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1910 "Aborting\n");
1911 break;
1912 case POWERPC_EXCP_STOP: /* stop translation */
1913 /* We did invalidate the instruction cache. Go on */
1914 break;
1915 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1916 /* We just stopped because of a branch. Go on */
1917 break;
1918 case POWERPC_EXCP_SYSCALL_USER:
1919 /* system call in user-mode emulation */
1920 /* WARNING:
1921 * PPC ABI uses overflow flag in cr0 to signal an error
1922 * in syscalls.
1923 */
e1833e1f
JM		 1924 env->crf[0] &= ~0x1;
1925 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1926 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1927 env->gpr[8], 0, 0);
9e0e2f96 1928 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1929 /* Returning from a successful sigreturn syscall.
1930 Avoid corrupting register state. */
1931 break;
1932 }
9e0e2f96 1933 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1934 env->crf[0] |= 0x1;
1935 ret = -ret;
61190b14 1936 }
e1833e1f 1937 env->gpr[3] = ret;
e1833e1f 1938 break;
56f066bb
NF		 1939 case POWERPC_EXCP_STCX:
1940 if (do_store_exclusive(env)) {
1941 info.si_signo = TARGET_SIGSEGV;
1942 info.si_errno = 0;
1943 info.si_code = TARGET_SEGV_MAPERR;
1944 info._sifields._sigfault._addr = env->nip;
1945 queue_signal(env, info.si_signo, &info);
1946 }
1947 break;
71f75756
AJ		 1948 case EXCP_DEBUG:
1949 {
1950 int sig;
1951
db6b81d4 1952 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1953 if (sig) {
1954 info.si_signo = sig;
1955 info.si_errno = 0;
1956 info.si_code = TARGET_TRAP_BRKPT;
1957 queue_signal(env, info.si_signo, &info);
1958 }
1959 }
1960 break;
56ba31ff
JM		 1961 case EXCP_INTERRUPT:
1962 /* just indicate that signals should be handled asap */
1963 break;
e1833e1f 1964 default:
a47dddd7 1965 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1966 break;
67867308
FB		 1967 }
1968 process_pending_signals(env);
1969 }
1970}
1971#endif
1972
048f6b4d
FB		 1973#ifdef TARGET_MIPS
1974
ff4f7382
RH		 1975# ifdef TARGET_ABI_MIPSO32
1976# define MIPS_SYS(name, args) args,
048f6b4d 1977static const uint8_t mips_syscall_args[] = {
29fb0f25 1978 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1979 MIPS_SYS(sys_exit , 1)
1980 MIPS_SYS(sys_fork , 0)
1981 MIPS_SYS(sys_read , 3)
1982 MIPS_SYS(sys_write , 3)
1983 MIPS_SYS(sys_open , 3) /* 4005 */
1984 MIPS_SYS(sys_close , 1)
1985 MIPS_SYS(sys_waitpid , 3)
1986 MIPS_SYS(sys_creat , 2)
1987 MIPS_SYS(sys_link , 2)
1988 MIPS_SYS(sys_unlink , 1) /* 4010 */
1989 MIPS_SYS(sys_execve , 0)
1990 MIPS_SYS(sys_chdir , 1)
1991 MIPS_SYS(sys_time , 1)
1992 MIPS_SYS(sys_mknod , 3)
1993 MIPS_SYS(sys_chmod , 2) /* 4015 */
1994 MIPS_SYS(sys_lchown , 3)
1995 MIPS_SYS(sys_ni_syscall , 0)
1996 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1997 MIPS_SYS(sys_lseek , 3)
1998 MIPS_SYS(sys_getpid , 0) /* 4020 */
1999 MIPS_SYS(sys_mount , 5)
868e34d7 2000 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2001 MIPS_SYS(sys_setuid , 1)
2002 MIPS_SYS(sys_getuid , 0)
2003 MIPS_SYS(sys_stime , 1) /* 4025 */
2004 MIPS_SYS(sys_ptrace , 4)
2005 MIPS_SYS(sys_alarm , 1)
2006 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2007 MIPS_SYS(sys_pause , 0)
2008 MIPS_SYS(sys_utime , 2) /* 4030 */
2009 MIPS_SYS(sys_ni_syscall , 0)
2010 MIPS_SYS(sys_ni_syscall , 0)
2011 MIPS_SYS(sys_access , 2)
2012 MIPS_SYS(sys_nice , 1)
2013 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2014 MIPS_SYS(sys_sync , 0)
2015 MIPS_SYS(sys_kill , 2)
2016 MIPS_SYS(sys_rename , 2)
2017 MIPS_SYS(sys_mkdir , 2)
2018 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2019 MIPS_SYS(sys_dup , 1)
2020 MIPS_SYS(sys_pipe , 0)
2021 MIPS_SYS(sys_times , 1)
2022 MIPS_SYS(sys_ni_syscall , 0)
2023 MIPS_SYS(sys_brk , 1) /* 4045 */
2024 MIPS_SYS(sys_setgid , 1)
2025 MIPS_SYS(sys_getgid , 0)
2026 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2027 MIPS_SYS(sys_geteuid , 0)
2028 MIPS_SYS(sys_getegid , 0) /* 4050 */
2029 MIPS_SYS(sys_acct , 0)
868e34d7 2030 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2031 MIPS_SYS(sys_ni_syscall , 0)
2032 MIPS_SYS(sys_ioctl , 3)
2033 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2034 MIPS_SYS(sys_ni_syscall , 2)
2035 MIPS_SYS(sys_setpgid , 2)
2036 MIPS_SYS(sys_ni_syscall , 0)
2037 MIPS_SYS(sys_olduname , 1)
2038 MIPS_SYS(sys_umask , 1) /* 4060 */
2039 MIPS_SYS(sys_chroot , 1)
2040 MIPS_SYS(sys_ustat , 2)
2041 MIPS_SYS(sys_dup2 , 2)
2042 MIPS_SYS(sys_getppid , 0)
2043 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2044 MIPS_SYS(sys_setsid , 0)
2045 MIPS_SYS(sys_sigaction , 3)
2046 MIPS_SYS(sys_sgetmask , 0)
2047 MIPS_SYS(sys_ssetmask , 1)
2048 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2049 MIPS_SYS(sys_setregid , 2)
2050 MIPS_SYS(sys_sigsuspend , 0)
2051 MIPS_SYS(sys_sigpending , 1)
2052 MIPS_SYS(sys_sethostname , 2)
2053 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2054 MIPS_SYS(sys_getrlimit , 2)
2055 MIPS_SYS(sys_getrusage , 2)
2056 MIPS_SYS(sys_gettimeofday, 2)
2057 MIPS_SYS(sys_settimeofday, 2)
2058 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2059 MIPS_SYS(sys_setgroups , 2)
2060 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2061 MIPS_SYS(sys_symlink , 2)
2062 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2063 MIPS_SYS(sys_readlink , 3) /* 4085 */
2064 MIPS_SYS(sys_uselib , 1)
2065 MIPS_SYS(sys_swapon , 2)
2066 MIPS_SYS(sys_reboot , 3)
2067 MIPS_SYS(old_readdir , 3)
2068 MIPS_SYS(old_mmap , 6) /* 4090 */
2069 MIPS_SYS(sys_munmap , 2)
2070 MIPS_SYS(sys_truncate , 2)
2071 MIPS_SYS(sys_ftruncate , 2)
2072 MIPS_SYS(sys_fchmod , 2)
2073 MIPS_SYS(sys_fchown , 3) /* 4095 */
2074 MIPS_SYS(sys_getpriority , 2)
2075 MIPS_SYS(sys_setpriority , 3)
2076 MIPS_SYS(sys_ni_syscall , 0)
2077 MIPS_SYS(sys_statfs , 2)
2078 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2079 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2080 MIPS_SYS(sys_socketcall , 2)
2081 MIPS_SYS(sys_syslog , 3)
2082 MIPS_SYS(sys_setitimer , 3)
2083 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2084 MIPS_SYS(sys_newstat , 2)
2085 MIPS_SYS(sys_newlstat , 2)
2086 MIPS_SYS(sys_newfstat , 2)
2087 MIPS_SYS(sys_uname , 1)
2088 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2089 MIPS_SYS(sys_vhangup , 0)
2090 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2091 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2092 MIPS_SYS(sys_wait4 , 4)
2093 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2094 MIPS_SYS(sys_sysinfo , 1)
2095 MIPS_SYS(sys_ipc , 6)
2096 MIPS_SYS(sys_fsync , 1)
2097 MIPS_SYS(sys_sigreturn , 0)
18113962 2098 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2099 MIPS_SYS(sys_setdomainname, 2)
2100 MIPS_SYS(sys_newuname , 1)
2101 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2102 MIPS_SYS(sys_adjtimex , 1)
2103 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2104 MIPS_SYS(sys_sigprocmask , 3)
2105 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2106 MIPS_SYS(sys_init_module , 5)
2107 MIPS_SYS(sys_delete_module, 1)
2108 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2109 MIPS_SYS(sys_quotactl , 0)
2110 MIPS_SYS(sys_getpgid , 1)
2111 MIPS_SYS(sys_fchdir , 1)
2112 MIPS_SYS(sys_bdflush , 2)
2113 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2114 MIPS_SYS(sys_personality , 1)
2115 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2116 MIPS_SYS(sys_setfsuid , 1)
2117 MIPS_SYS(sys_setfsgid , 1)
2118 MIPS_SYS(sys_llseek , 5) /* 4140 */
2119 MIPS_SYS(sys_getdents , 3)
2120 MIPS_SYS(sys_select , 5)
2121 MIPS_SYS(sys_flock , 2)
2122 MIPS_SYS(sys_msync , 3)
2123 MIPS_SYS(sys_readv , 3) /* 4145 */
2124 MIPS_SYS(sys_writev , 3)
2125 MIPS_SYS(sys_cacheflush , 3)
2126 MIPS_SYS(sys_cachectl , 3)
2127 MIPS_SYS(sys_sysmips , 4)
2128 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2129 MIPS_SYS(sys_getsid , 1)
2130 MIPS_SYS(sys_fdatasync , 0)
2131 MIPS_SYS(sys_sysctl , 1)
2132 MIPS_SYS(sys_mlock , 2)
2133 MIPS_SYS(sys_munlock , 2) /* 4155 */
2134 MIPS_SYS(sys_mlockall , 1)
2135 MIPS_SYS(sys_munlockall , 0)
2136 MIPS_SYS(sys_sched_setparam, 2)
2137 MIPS_SYS(sys_sched_getparam, 2)
2138 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2139 MIPS_SYS(sys_sched_getscheduler, 1)
2140 MIPS_SYS(sys_sched_yield , 0)
2141 MIPS_SYS(sys_sched_get_priority_max, 1)
2142 MIPS_SYS(sys_sched_get_priority_min, 1)
2143 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2144 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2145 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2146 MIPS_SYS(sys_accept , 3)
2147 MIPS_SYS(sys_bind , 3)
2148 MIPS_SYS(sys_connect , 3) /* 4170 */
2149 MIPS_SYS(sys_getpeername , 3)
2150 MIPS_SYS(sys_getsockname , 3)
2151 MIPS_SYS(sys_getsockopt , 5)
2152 MIPS_SYS(sys_listen , 2)
2153 MIPS_SYS(sys_recv , 4) /* 4175 */
2154 MIPS_SYS(sys_recvfrom , 6)
2155 MIPS_SYS(sys_recvmsg , 3)
2156 MIPS_SYS(sys_send , 4)
2157 MIPS_SYS(sys_sendmsg , 3)
2158 MIPS_SYS(sys_sendto , 6) /* 4180 */
2159 MIPS_SYS(sys_setsockopt , 5)
2160 MIPS_SYS(sys_shutdown , 2)
2161 MIPS_SYS(sys_socket , 3)
2162 MIPS_SYS(sys_socketpair , 4)
2163 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2164 MIPS_SYS(sys_getresuid , 3)
2165 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2166 MIPS_SYS(sys_poll , 3)
2167 MIPS_SYS(sys_nfsservctl , 3)
2168 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2169 MIPS_SYS(sys_getresgid , 3)
2170 MIPS_SYS(sys_prctl , 5)
2171 MIPS_SYS(sys_rt_sigreturn, 0)
2172 MIPS_SYS(sys_rt_sigaction, 4)
2173 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2174 MIPS_SYS(sys_rt_sigpending, 2)
2175 MIPS_SYS(sys_rt_sigtimedwait, 4)
2176 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2177 MIPS_SYS(sys_rt_sigsuspend, 0)
2178 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2179 MIPS_SYS(sys_pwrite64 , 6)
2180 MIPS_SYS(sys_chown , 3)
2181 MIPS_SYS(sys_getcwd , 2)
2182 MIPS_SYS(sys_capget , 2)
2183 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2184 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2185 MIPS_SYS(sys_sendfile , 4)
2186 MIPS_SYS(sys_ni_syscall , 0)
2187 MIPS_SYS(sys_ni_syscall , 0)
2188 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2189 MIPS_SYS(sys_truncate64 , 4)
2190 MIPS_SYS(sys_ftruncate64 , 4)
2191 MIPS_SYS(sys_stat64 , 2)
2192 MIPS_SYS(sys_lstat64 , 2)
2193 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2194 MIPS_SYS(sys_pivot_root , 2)
2195 MIPS_SYS(sys_mincore , 3)
2196 MIPS_SYS(sys_madvise , 3)
2197 MIPS_SYS(sys_getdents64 , 3)
2198 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2199 MIPS_SYS(sys_ni_syscall , 0)
2200 MIPS_SYS(sys_gettid , 0)
2201 MIPS_SYS(sys_readahead , 5)
2202 MIPS_SYS(sys_setxattr , 5)
2203 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2204 MIPS_SYS(sys_fsetxattr , 5)
2205 MIPS_SYS(sys_getxattr , 4)
2206 MIPS_SYS(sys_lgetxattr , 4)
2207 MIPS_SYS(sys_fgetxattr , 4)
2208 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2209 MIPS_SYS(sys_llistxattr , 3)
2210 MIPS_SYS(sys_flistxattr , 3)
2211 MIPS_SYS(sys_removexattr , 2)
2212 MIPS_SYS(sys_lremovexattr, 2)
2213 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2214 MIPS_SYS(sys_tkill , 2)
2215 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2216 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2217 MIPS_SYS(sys_sched_setaffinity, 3)
2218 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2219 MIPS_SYS(sys_io_setup , 2)
2220 MIPS_SYS(sys_io_destroy , 1)
2221 MIPS_SYS(sys_io_getevents, 5)
2222 MIPS_SYS(sys_io_submit , 3)
2223 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2224 MIPS_SYS(sys_exit_group , 1)
2225 MIPS_SYS(sys_lookup_dcookie, 3)
2226 MIPS_SYS(sys_epoll_create, 1)
2227 MIPS_SYS(sys_epoll_ctl , 4)
2228 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2229 MIPS_SYS(sys_remap_file_pages, 5)
2230 MIPS_SYS(sys_set_tid_address, 1)
2231 MIPS_SYS(sys_restart_syscall, 0)
2232 MIPS_SYS(sys_fadvise64_64, 7)
2233 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2234 MIPS_SYS(sys_fstatfs64 , 2)
2235 MIPS_SYS(sys_timer_create, 3)
2236 MIPS_SYS(sys_timer_settime, 4)
2237 MIPS_SYS(sys_timer_gettime, 2)
2238 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2239 MIPS_SYS(sys_timer_delete, 1)
2240 MIPS_SYS(sys_clock_settime, 2)
2241 MIPS_SYS(sys_clock_gettime, 2)
2242 MIPS_SYS(sys_clock_getres, 2)
2243 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2244 MIPS_SYS(sys_tgkill , 3)
2245 MIPS_SYS(sys_utimes , 2)
2246 MIPS_SYS(sys_mbind , 4)
2247 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2248 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2249 MIPS_SYS(sys_mq_open , 4)
2250 MIPS_SYS(sys_mq_unlink , 1)
2251 MIPS_SYS(sys_mq_timedsend, 5)
2252 MIPS_SYS(sys_mq_timedreceive, 5)
2253 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2254 MIPS_SYS(sys_mq_getsetattr, 3)
2255 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2256 MIPS_SYS(sys_waitid , 4)
2257 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2258 MIPS_SYS(sys_add_key , 5)
388bb21a 2259 MIPS_SYS(sys_request_key, 4)
048f6b4d 2260 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2261 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2262 MIPS_SYS(sys_inotify_init, 0)
2263 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2264 MIPS_SYS(sys_inotify_rm_watch, 2)
2265 MIPS_SYS(sys_migrate_pages, 4)
2266 MIPS_SYS(sys_openat, 4)
2267 MIPS_SYS(sys_mkdirat, 3)
2268 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2269 MIPS_SYS(sys_fchownat, 5)
2270 MIPS_SYS(sys_futimesat, 3)
2271 MIPS_SYS(sys_fstatat64, 4)
2272 MIPS_SYS(sys_unlinkat, 3)
2273 MIPS_SYS(sys_renameat, 4) /* 4295 */
2274 MIPS_SYS(sys_linkat, 5)
2275 MIPS_SYS(sys_symlinkat, 3)
2276 MIPS_SYS(sys_readlinkat, 4)
2277 MIPS_SYS(sys_fchmodat, 3)
2278 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2279 MIPS_SYS(sys_pselect6, 6)
2280 MIPS_SYS(sys_ppoll, 5)
2281 MIPS_SYS(sys_unshare, 1)
b0932e06 2282 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2283 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2284 MIPS_SYS(sys_tee, 4)
2285 MIPS_SYS(sys_vmsplice, 4)
2286 MIPS_SYS(sys_move_pages, 6)
2287 MIPS_SYS(sys_set_robust_list, 2)
2288 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2289 MIPS_SYS(sys_kexec_load, 4)
2290 MIPS_SYS(sys_getcpu, 3)
2291 MIPS_SYS(sys_epoll_pwait, 6)
2292 MIPS_SYS(sys_ioprio_set, 3)
2293 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2294 MIPS_SYS(sys_utimensat, 4)
2295 MIPS_SYS(sys_signalfd, 3)
2296 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2297 MIPS_SYS(sys_eventfd, 1)
2298 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2299 MIPS_SYS(sys_timerfd_create, 2)
2300 MIPS_SYS(sys_timerfd_gettime, 2)
2301 MIPS_SYS(sys_timerfd_settime, 4)
2302 MIPS_SYS(sys_signalfd4, 4)
2303 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2304 MIPS_SYS(sys_epoll_create1, 1)
2305 MIPS_SYS(sys_dup3, 3)
2306 MIPS_SYS(sys_pipe2, 2)
2307 MIPS_SYS(sys_inotify_init1, 1)
2308 MIPS_SYS(sys_preadv, 6) /* 4330 */
2309 MIPS_SYS(sys_pwritev, 6)
2310 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2311 MIPS_SYS(sys_perf_event_open, 5)
2312 MIPS_SYS(sys_accept4, 4)
2313 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2314 MIPS_SYS(sys_fanotify_init, 2)
2315 MIPS_SYS(sys_fanotify_mark, 6)
2316 MIPS_SYS(sys_prlimit64, 4)
2317 MIPS_SYS(sys_name_to_handle_at, 5)
2318 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2319 MIPS_SYS(sys_clock_adjtime, 2)
2320 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2321};
ff4f7382
RH		 2322# undef MIPS_SYS
2323# endif /* O32 */
048f6b4d 2324
590bc601
PB		 2325static int do_store_exclusive(CPUMIPSState *env)
2326{
2327 target_ulong addr;
2328 target_ulong page_addr;
2329 target_ulong val;
2330 int flags;
2331 int segv = 0;
2332 int reg;
2333 int d;
2334
5499b6ff 2335 addr = env->lladdr;
590bc601
PB		 2336 page_addr = addr & TARGET_PAGE_MASK;
2337 start_exclusive();
2338 mmap_lock();
2339 flags = page_get_flags(page_addr);
2340 if ((flags & PAGE_READ) == 0) {
2341 segv = 1;
2342 } else {
2343 reg = env->llreg & 0x1f;
2344 d = (env->llreg & 0x20) != 0;
2345 if (d) {
2346 segv = get_user_s64(val, addr);
2347 } else {
2348 segv = get_user_s32(val, addr);
2349 }
2350 if (!segv) {
2351 if (val != env->llval) {
2352 env->active_tc.gpr[reg] = 0;
2353 } else {
2354 if (d) {
2355 segv = put_user_u64(env->llnewval, addr);
2356 } else {
2357 segv = put_user_u32(env->llnewval, addr);
2358 }
2359 if (!segv) {
2360 env->active_tc.gpr[reg] = 1;
2361 }
2362 }
2363 }
2364 }
5499b6ff 2365 env->lladdr = -1;
590bc601
PB		 2366 if (!segv) {
2367 env->active_tc.PC += 4;
2368 }
2369 mmap_unlock();
2370 end_exclusive();
2371 return segv;
2372}
2373
54b2f42c
MI		 2374/* Break codes */
2375enum {
2376 BRK_OVERFLOW = 6,
2377 BRK_DIVZERO = 7
2378};
2379
2380static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2381 unsigned int code)
2382{
2383 int ret = -1;
2384
2385 switch (code) {
2386 case BRK_OVERFLOW:
2387 case BRK_DIVZERO:
2388 info->si_signo = TARGET_SIGFPE;
2389 info->si_errno = 0;
2390 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2391 queue_signal(env, info->si_signo, &*info);
2392 ret = 0;
2393 break;
2394 default:
b51910ba
PJ		 2395 info->si_signo = TARGET_SIGTRAP;
2396 info->si_errno = 0;
2397 queue_signal(env, info->si_signo, &*info);
2398 ret = 0;
54b2f42c
MI		 2399 break;
2400 }
2401
2402 return ret;
2403}
2404
048f6b4d
FB		 2405void cpu_loop(CPUMIPSState *env)
2406{
0315c31c 2407 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2408 target_siginfo_t info;
ff4f7382
RH		 2409 int trapnr;
2410 abi_long ret;
2411# ifdef TARGET_ABI_MIPSO32
048f6b4d 2412 unsigned int syscall_num;
ff4f7382 2413# endif
048f6b4d
FB		 2414
2415 for(;;) {
0315c31c 2416 cpu_exec_start(cs);
048f6b4d 2417 trapnr = cpu_mips_exec(env);
0315c31c 2418 cpu_exec_end(cs);
048f6b4d
FB		 2419 switch(trapnr) {
2420 case EXCP_SYSCALL:
b5dc7732 2421 env->active_tc.PC += 4;
ff4f7382
RH		 2422# ifdef TARGET_ABI_MIPSO32
2423 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2424 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2425 ret = -TARGET_ENOSYS;
388bb21a
TS		 2426 } else {
2427 int nb_args;
992f48a0
BS		 2428 abi_ulong sp_reg;
2429 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2430
2431 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2432 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2433 switch (nb_args) {
2434 /* these arguments are taken from the stack */
94c19610
ACH		 2435 case 8:
2436 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2437 goto done_syscall;
2438 }
2439 case 7:
2440 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2441 goto done_syscall;
2442 }
2443 case 6:
2444 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 5:
2448 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2449 goto done_syscall;
2450 }
388bb21a
TS		 2451 default:
2452 break;
048f6b4d 2453 }
b5dc7732
TS		 2454 ret = do_syscall(env, env->active_tc.gpr[2],
2455 env->active_tc.gpr[4],
2456 env->active_tc.gpr[5],
2457 env->active_tc.gpr[6],
2458 env->active_tc.gpr[7],
5945cfcb 2459 arg5, arg6, arg7, arg8);
388bb21a 2460 }
94c19610 2461done_syscall:
ff4f7382
RH		 2462# else
2463 ret = do_syscall(env, env->active_tc.gpr[2],
2464 env->active_tc.gpr[4], env->active_tc.gpr[5],
2465 env->active_tc.gpr[6], env->active_tc.gpr[7],
2466 env->active_tc.gpr[8], env->active_tc.gpr[9],
2467 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2468# endif /* O32 */
0b1bcb00
PB		 2469 if (ret == -TARGET_QEMU_ESIGRETURN) {
2470 /* Returning from a successful sigreturn syscall.
2471 Avoid clobbering register state. */
2472 break;
2473 }
ff4f7382 2474 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2475 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2476 ret = -ret;
2477 } else {
b5dc7732 2478 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2479 }
b5dc7732 2480 env->active_tc.gpr[2] = ret;
048f6b4d 2481 break;
ca7c2b1b
TS		 2482 case EXCP_TLBL:
2483 case EXCP_TLBS:
e6e5bd2d
WT		 2484 case EXCP_AdEL:
2485 case EXCP_AdES:
e4474235
PB		 2486 info.si_signo = TARGET_SIGSEGV;
2487 info.si_errno = 0;
2488 /* XXX: check env->error_code */
2489 info.si_code = TARGET_SEGV_MAPERR;
2490 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2491 queue_signal(env, info.si_signo, &info);
2492 break;
6900e84b 2493 case EXCP_CpU:
048f6b4d 2494 case EXCP_RI:
bc1ad2de
FB		 2495 info.si_signo = TARGET_SIGILL;
2496 info.si_errno = 0;
2497 info.si_code = 0;
624f7979 2498 queue_signal(env, info.si_signo, &info);
048f6b4d 2499 break;
106ec879
FB		 2500 case EXCP_INTERRUPT:
2501 /* just indicate that signals should be handled asap */
2502 break;
d08b2a28
PB		 2503 case EXCP_DEBUG:
2504 {
2505 int sig;
2506
db6b81d4 2507 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2508 if (sig)
2509 {
2510 info.si_signo = sig;
2511 info.si_errno = 0;
2512 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2513 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2514 }
2515 }
2516 break;
590bc601
PB		 2517 case EXCP_SC:
2518 if (do_store_exclusive(env)) {
2519 info.si_signo = TARGET_SIGSEGV;
2520 info.si_errno = 0;
2521 info.si_code = TARGET_SEGV_MAPERR;
2522 info._sifields._sigfault._addr = env->active_tc.PC;
2523 queue_signal(env, info.si_signo, &info);
2524 }
2525 break;
853c3240
JL		 2526 case EXCP_DSPDIS:
2527 info.si_signo = TARGET_SIGILL;
2528 info.si_errno = 0;
2529 info.si_code = TARGET_ILL_ILLOPC;
2530 queue_signal(env, info.si_signo, &info);
2531 break;
54b2f42c
MI		 2532 /* The code below was inspired by the MIPS Linux kernel trap
2533 * handling code in arch/mips/kernel/traps.c.
2534 */
2535 case EXCP_BREAK:
2536 {
2537 abi_ulong trap_instr;
2538 unsigned int code;
2539
a0333817
KCY		 2540 if (env->hflags & MIPS_HFLAG_M16) {
2541 if (env->insn_flags & ASE_MICROMIPS) {
2542 /* microMIPS mode */
1308c464
KCY		 2543 ret = get_user_u16(trap_instr, env->active_tc.PC);
2544 if (ret != 0) {
2545 goto error;
2546 }
a0333817 2547
1308c464
KCY		 2548 if ((trap_instr >> 10) == 0x11) {
2549 /* 16-bit instruction */
2550 code = trap_instr & 0xf;
2551 } else {
2552 /* 32-bit instruction */
2553 abi_ulong instr_lo;
2554
2555 ret = get_user_u16(instr_lo,
2556 env->active_tc.PC + 2);
2557 if (ret != 0) {
2558 goto error;
2559 }
2560 trap_instr = (trap_instr << 16) | instr_lo;
2561 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2562 /* Unfortunately, microMIPS also suffers from
2563 the old assembler bug... */
2564 if (code >= (1 << 10)) {
2565 code >>= 10;
2566 }
2567 }
a0333817
KCY		 2568 } else {
2569 /* MIPS16e mode */
2570 ret = get_user_u16(trap_instr, env->active_tc.PC);
2571 if (ret != 0) {
2572 goto error;
2573 }
2574 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2575 }
2576 } else {
2577 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2578 if (ret != 0) {
2579 goto error;
2580 }
54b2f42c 2581
1308c464
KCY		 2582 /* As described in the original Linux kernel code, the
2583 * below checks on 'code' are to work around an old
2584 * assembly bug.
2585 */
2586 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2587 if (code >= (1 << 10)) {
2588 code >>= 10;
2589 }
54b2f42c
MI		 2590 }
2591
2592 if (do_break(env, &info, code) != 0) {
2593 goto error;
2594 }
2595 }
2596 break;
2597 case EXCP_TRAP:
2598 {
2599 abi_ulong trap_instr;
2600 unsigned int code = 0;
2601
a0333817
KCY		 2602 if (env->hflags & MIPS_HFLAG_M16) {
2603 /* microMIPS mode */
2604 abi_ulong instr[2];
2605
2606 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2607 get_user_u16(instr[1], env->active_tc.PC + 2);
2608
2609 trap_instr = (instr[0] << 16) | instr[1];
2610 } else {
2611 ret = get_user_ual(trap_instr, env->active_tc.PC);
2612 }
2613
54b2f42c
MI		 2614 if (ret != 0) {
2615 goto error;
2616 }
2617
2618 /* The immediate versions don't provide a code. */
2619 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2620 if (env->hflags & MIPS_HFLAG_M16) {
2621 /* microMIPS mode */
2622 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2623 } else {
2624 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2625 }
54b2f42c
MI		 2626 }
2627
2628 if (do_break(env, &info, code) != 0) {
2629 goto error;
2630 }
2631 }
2632 break;
048f6b4d 2633 default:
54b2f42c 2634error:
5fafdf24 2635 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2636 trapnr);
878096ee 2637 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2638 abort();
2639 }
2640 process_pending_signals(env);
2641 }
2642}
2643#endif
2644
d962783e
JL		 2645#ifdef TARGET_OPENRISC
2646
2647void cpu_loop(CPUOpenRISCState *env)
2648{
878096ee 2649 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2650 int trapnr, gdbsig;
2651
2652 for (;;) {
2653 trapnr = cpu_exec(env);
2654 gdbsig = 0;
2655
2656 switch (trapnr) {
2657 case EXCP_RESET:
2658 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2659 exit(1);
2660 break;
2661 case EXCP_BUSERR:
2662 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2663 gdbsig = SIGBUS;
2664 break;
2665 case EXCP_DPF:
2666 case EXCP_IPF:
878096ee 2667 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2668 gdbsig = TARGET_SIGSEGV;
2669 break;
2670 case EXCP_TICK:
2671 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2672 break;
2673 case EXCP_ALIGN:
2674 qemu_log("\nAlignment pc is %#x\n", env->pc);
2675 gdbsig = SIGBUS;
2676 break;
2677 case EXCP_ILLEGAL:
2678 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2679 gdbsig = SIGILL;
2680 break;
2681 case EXCP_INT:
2682 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2683 break;
2684 case EXCP_DTLBMISS:
2685 case EXCP_ITLBMISS:
2686 qemu_log("\nTLB miss\n");
2687 break;
2688 case EXCP_RANGE:
2689 qemu_log("\nRange\n");
2690 gdbsig = SIGSEGV;
2691 break;
2692 case EXCP_SYSCALL:
2693 env->pc += 4; /* 0xc00; */
2694 env->gpr[11] = do_syscall(env,
2695 env->gpr[11], /* return value */
2696 env->gpr[3], /* r3 - r7 are params */
2697 env->gpr[4],
2698 env->gpr[5],
2699 env->gpr[6],
2700 env->gpr[7],
2701 env->gpr[8], 0, 0);
2702 break;
2703 case EXCP_FPE:
2704 qemu_log("\nFloating point error\n");
2705 break;
2706 case EXCP_TRAP:
2707 qemu_log("\nTrap\n");
2708 gdbsig = SIGTRAP;
2709 break;
2710 case EXCP_NR:
2711 qemu_log("\nNR\n");
2712 break;
2713 default:
2714 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2715 trapnr);
878096ee 2716 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2717 gdbsig = TARGET_SIGILL;
2718 break;
2719 }
2720 if (gdbsig) {
db6b81d4 2721 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2722 if (gdbsig != TARGET_SIGTRAP) {
2723 exit(1);
2724 }
2725 }
2726
2727 process_pending_signals(env);
2728 }
2729}
2730
2731#endif /* TARGET_OPENRISC */
2732
fdf9b3e8 2733#ifdef TARGET_SH4
05390248 2734void cpu_loop(CPUSH4State *env)
fdf9b3e8 2735{
878096ee 2736 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2737 int trapnr, ret;
c227f099 2738 target_siginfo_t info;
3b46e624 2739
fdf9b3e8
FB		 2740 while (1) {
2741 trapnr = cpu_sh4_exec (env);
3b46e624 2742
fdf9b3e8
FB		 2743 switch (trapnr) {
2744 case 0x160:
0b6d3ae0 2745 env->pc += 2;
5fafdf24
TS		 2746 ret = do_syscall(env,
2747 env->gregs[3],
2748 env->gregs[4],
2749 env->gregs[5],
2750 env->gregs[6],
2751 env->gregs[7],
2752 env->gregs[0],
5945cfcb
PM		 2753 env->gregs[1],
2754 0, 0);
9c2a9ea1 2755 env->gregs[0] = ret;
fdf9b3e8 2756 break;
c3b5bc8a
TS		 2757 case EXCP_INTERRUPT:
2758 /* just indicate that signals should be handled asap */
2759 break;
355fb23d
PB		 2760 case EXCP_DEBUG:
2761 {
2762 int sig;
2763
db6b81d4 2764 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2765 if (sig)
2766 {
2767 info.si_signo = sig;
2768 info.si_errno = 0;
2769 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2770 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2771 }
2772 }
2773 break;
c3b5bc8a
TS		 2774 case 0xa0:
2775 case 0xc0:
2776 info.si_signo = SIGSEGV;
2777 info.si_errno = 0;
2778 info.si_code = TARGET_SEGV_MAPERR;
2779 info._sifields._sigfault._addr = env->tea;
624f7979 2780 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2781 break;
2782
fdf9b3e8
FB		 2783 default:
2784 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2785 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2786 exit (1);
2787 }
2788 process_pending_signals (env);
2789 }
2790}
2791#endif
2792
48733d19 2793#ifdef TARGET_CRIS
05390248 2794void cpu_loop(CPUCRISState *env)
48733d19 2795{
878096ee 2796 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2797 int trapnr, ret;
c227f099 2798 target_siginfo_t info;
48733d19
TS		 2799
2800 while (1) {
2801 trapnr = cpu_cris_exec (env);
2802 switch (trapnr) {
2803 case 0xaa:
2804 {
2805 info.si_signo = SIGSEGV;
2806 info.si_errno = 0;
2807 /* XXX: check env->error_code */
2808 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2809 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2810 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2811 }
2812 break;
b6d3abda
EI		 2813 case EXCP_INTERRUPT:
2814 /* just indicate that signals should be handled asap */
2815 break;
48733d19
TS		 2816 case EXCP_BREAK:
2817 ret = do_syscall(env,
2818 env->regs[9],
2819 env->regs[10],
2820 env->regs[11],
2821 env->regs[12],
2822 env->regs[13],
2823 env->pregs[7],
5945cfcb
PM		 2824 env->pregs[11],
2825 0, 0);
48733d19 2826 env->regs[10] = ret;
48733d19
TS		 2827 break;
2828 case EXCP_DEBUG:
2829 {
2830 int sig;
2831
db6b81d4 2832 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2833 if (sig)
2834 {
2835 info.si_signo = sig;
2836 info.si_errno = 0;
2837 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2838 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2839 }
2840 }
2841 break;
2842 default:
2843 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2844 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2845 exit (1);
2846 }
2847 process_pending_signals (env);
2848 }
2849}
2850#endif
2851
b779e29e 2852#ifdef TARGET_MICROBLAZE
05390248 2853void cpu_loop(CPUMBState *env)
b779e29e 2854{
878096ee 2855 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2856 int trapnr, ret;
c227f099 2857 target_siginfo_t info;
b779e29e
EI		 2858
2859 while (1) {
2860 trapnr = cpu_mb_exec (env);
2861 switch (trapnr) {
2862 case 0xaa:
2863 {
2864 info.si_signo = SIGSEGV;
2865 info.si_errno = 0;
2866 /* XXX: check env->error_code */
2867 info.si_code = TARGET_SEGV_MAPERR;
2868 info._sifields._sigfault._addr = 0;
2869 queue_signal(env, info.si_signo, &info);
2870 }
2871 break;
2872 case EXCP_INTERRUPT:
2873 /* just indicate that signals should be handled asap */
2874 break;
2875 case EXCP_BREAK:
2876 /* Return address is 4 bytes after the call. */
2877 env->regs[14] += 4;
d7dce494 2878 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2879 ret = do_syscall(env,
2880 env->regs[12],
2881 env->regs[5],
2882 env->regs[6],
2883 env->regs[7],
2884 env->regs[8],
2885 env->regs[9],
5945cfcb
PM		 2886 env->regs[10],
2887 0, 0);
b779e29e 2888 env->regs[3] = ret;
b779e29e 2889 break;
b76da7e3
EI		 2890 case EXCP_HW_EXCP:
2891 env->regs[17] = env->sregs[SR_PC] + 4;
2892 if (env->iflags & D_FLAG) {
2893 env->sregs[SR_ESR] |= 1 << 12;
2894 env->sregs[SR_PC] -= 4;
b4916d7b 2895 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2896 }
2897
2898 env->iflags &= ~(IMM_FLAG | D_FLAG);
2899
2900 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2901 case ESR_EC_DIVZERO:
2902 info.si_signo = SIGFPE;
2903 info.si_errno = 0;
2904 info.si_code = TARGET_FPE_FLTDIV;
2905 info._sifields._sigfault._addr = 0;
2906 queue_signal(env, info.si_signo, &info);
2907 break;
b76da7e3
EI		 2908 case ESR_EC_FPU:
2909 info.si_signo = SIGFPE;
2910 info.si_errno = 0;
2911 if (env->sregs[SR_FSR] & FSR_IO) {
2912 info.si_code = TARGET_FPE_FLTINV;
2913 }
2914 if (env->sregs[SR_FSR] & FSR_DZ) {
2915 info.si_code = TARGET_FPE_FLTDIV;
2916 }
2917 info._sifields._sigfault._addr = 0;
2918 queue_signal(env, info.si_signo, &info);
2919 break;
2920 default:
2921 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2922 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2923 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2924 exit (1);
2925 break;
2926 }
2927 break;
b779e29e
EI		 2928 case EXCP_DEBUG:
2929 {
2930 int sig;
2931
db6b81d4 2932 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2933 if (sig)
2934 {
2935 info.si_signo = sig;
2936 info.si_errno = 0;
2937 info.si_code = TARGET_TRAP_BRKPT;
2938 queue_signal(env, info.si_signo, &info);
2939 }
2940 }
2941 break;
2942 default:
2943 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2944 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2945 exit (1);
2946 }
2947 process_pending_signals (env);
2948 }
2949}
2950#endif
2951
e6e5906b
PB		 2952#ifdef TARGET_M68K
2953
2954void cpu_loop(CPUM68KState *env)
2955{
878096ee 2956 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2957 int trapnr;
2958 unsigned int n;
c227f099 2959 target_siginfo_t info;
0429a971 2960 TaskState *ts = cs->opaque;
3b46e624 2961
e6e5906b
PB		 2962 for(;;) {
2963 trapnr = cpu_m68k_exec(env);
2964 switch(trapnr) {
2965 case EXCP_ILLEGAL:
2966 {
2967 if (ts->sim_syscalls) {
2968 uint16_t nr;
2969 nr = lduw(env->pc + 2);
2970 env->pc += 4;
2971 do_m68k_simcall(env, nr);
2972 } else {
2973 goto do_sigill;
2974 }
2975 }
2976 break;
a87295e8 2977 case EXCP_HALT_INSN:
e6e5906b 2978 /* Semihosing syscall. */
a87295e8 2979 env->pc += 4;
e6e5906b
PB		 2980 do_m68k_semihosting(env, env->dregs[0]);
2981 break;
2982 case EXCP_LINEA:
2983 case EXCP_LINEF:
2984 case EXCP_UNSUPPORTED:
2985 do_sigill:
2986 info.si_signo = SIGILL;
2987 info.si_errno = 0;
2988 info.si_code = TARGET_ILL_ILLOPN;
2989 info._sifields._sigfault._addr = env->pc;
624f7979 2990 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2991 break;
2992 case EXCP_TRAP0:
2993 {
2994 ts->sim_syscalls = 0;
2995 n = env->dregs[0];
2996 env->pc += 2;
5fafdf24
TS		 2997 env->dregs[0] = do_syscall(env,
2998 n,
e6e5906b
PB		 2999 env->dregs[1],
3000 env->dregs[2],
3001 env->dregs[3],
3002 env->dregs[4],
3003 env->dregs[5],
5945cfcb
PM		 3004 env->aregs[0],
3005 0, 0);
e6e5906b
PB		 3006 }
3007 break;
3008 case EXCP_INTERRUPT:
3009 /* just indicate that signals should be handled asap */
3010 break;
3011 case EXCP_ACCESS:
3012 {
3013 info.si_signo = SIGSEGV;
3014 info.si_errno = 0;
3015 /* XXX: check env->error_code */
3016 info.si_code = TARGET_SEGV_MAPERR;
3017 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3018 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3019 }
3020 break;
3021 case EXCP_DEBUG:
3022 {
3023 int sig;
3024
db6b81d4 3025 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3026 if (sig)
3027 {
3028 info.si_signo = sig;
3029 info.si_errno = 0;
3030 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3031 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3032 }
3033 }
3034 break;
3035 default:
5fafdf24 3036 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3037 trapnr);
878096ee 3038 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3039 abort();
3040 }
3041 process_pending_signals(env);
3042 }
3043}
3044#endif /* TARGET_M68K */
3045
7a3148a9 3046#ifdef TARGET_ALPHA
6910b8f6
RH		 3047static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3048{
3049 target_ulong addr, val, tmp;
3050 target_siginfo_t info;
3051 int ret = 0;
3052
3053 addr = env->lock_addr;
3054 tmp = env->lock_st_addr;
3055 env->lock_addr = -1;
3056 env->lock_st_addr = 0;
3057
3058 start_exclusive();
3059 mmap_lock();
3060
3061 if (addr == tmp) {
3062 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3063 goto do_sigsegv;
3064 }
3065
3066 if (val == env->lock_value) {
3067 tmp = env->ir[reg];
3068 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3069 goto do_sigsegv;
3070 }
3071 ret = 1;
3072 }
3073 }
3074 env->ir[reg] = ret;
3075 env->pc += 4;
3076
3077 mmap_unlock();
3078 end_exclusive();
3079 return;
3080
3081 do_sigsegv:
3082 mmap_unlock();
3083 end_exclusive();
3084
3085 info.si_signo = TARGET_SIGSEGV;
3086 info.si_errno = 0;
3087 info.si_code = TARGET_SEGV_MAPERR;
3088 info._sifields._sigfault._addr = addr;
3089 queue_signal(env, TARGET_SIGSEGV, &info);
3090}
3091
05390248 3092void cpu_loop(CPUAlphaState *env)
7a3148a9 3093{
878096ee 3094 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3095 int trapnr;
c227f099 3096 target_siginfo_t info;
6049f4f8 3097 abi_long sysret;
3b46e624 3098
7a3148a9
JM		 3099 while (1) {
3100 trapnr = cpu_alpha_exec (env);
3b46e624 3101
ac316ca4
RH		 3102 /* All of the traps imply a transition through PALcode, which
3103 implies an REI instruction has been executed. Which means
3104 that the intr_flag should be cleared. */
3105 env->intr_flag = 0;
3106
7a3148a9
JM		 3107 switch (trapnr) {
3108 case EXCP_RESET:
3109 fprintf(stderr, "Reset requested. Exit\n");
3110 exit(1);
3111 break;
3112 case EXCP_MCHK:
3113 fprintf(stderr, "Machine check exception. Exit\n");
3114 exit(1);
3115 break;
07b6c13b
RH		 3116 case EXCP_SMP_INTERRUPT:
3117 case EXCP_CLK_INTERRUPT:
3118 case EXCP_DEV_INTERRUPT:
5fafdf24 3119 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3120 exit(1);
3121 break;
07b6c13b 3122 case EXCP_MMFAULT:
6910b8f6 3123 env->lock_addr = -1;
6049f4f8
RH		 3124 info.si_signo = TARGET_SIGSEGV;
3125 info.si_errno = 0;
129d8aa5 3126 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3127 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3128 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3129 queue_signal(env, info.si_signo, &info);
7a3148a9 3130 break;
7a3148a9 3131 case EXCP_UNALIGN:
6910b8f6 3132 env->lock_addr = -1;
6049f4f8
RH		 3133 info.si_signo = TARGET_SIGBUS;
3134 info.si_errno = 0;
3135 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3136 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3137 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3138 break;
3139 case EXCP_OPCDEC:
6049f4f8 3140 do_sigill:
6910b8f6 3141 env->lock_addr = -1;
6049f4f8
RH		 3142 info.si_signo = TARGET_SIGILL;
3143 info.si_errno = 0;
3144 info.si_code = TARGET_ILL_ILLOPC;
3145 info._sifields._sigfault._addr = env->pc;
3146 queue_signal(env, info.si_signo, &info);
7a3148a9 3147 break;
07b6c13b
RH		 3148 case EXCP_ARITH:
3149 env->lock_addr = -1;
3150 info.si_signo = TARGET_SIGFPE;
3151 info.si_errno = 0;
3152 info.si_code = TARGET_FPE_FLTINV;
3153 info._sifields._sigfault._addr = env->pc;
3154 queue_signal(env, info.si_signo, &info);
3155 break;
7a3148a9 3156 case EXCP_FEN:
6049f4f8 3157 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3158 break;
07b6c13b 3159 case EXCP_CALL_PAL:
6910b8f6 3160 env->lock_addr = -1;
07b6c13b 3161 switch (env->error_code) {
6049f4f8
RH		 3162 case 0x80:
3163 /* BPT */
3164 info.si_signo = TARGET_SIGTRAP;
3165 info.si_errno = 0;
3166 info.si_code = TARGET_TRAP_BRKPT;
3167 info._sifields._sigfault._addr = env->pc;
3168 queue_signal(env, info.si_signo, &info);
3169 break;
3170 case 0x81:
3171 /* BUGCHK */
3172 info.si_signo = TARGET_SIGTRAP;
3173 info.si_errno = 0;
3174 info.si_code = 0;
3175 info._sifields._sigfault._addr = env->pc;
3176 queue_signal(env, info.si_signo, &info);
3177 break;
3178 case 0x83:
3179 /* CALLSYS */
3180 trapnr = env->ir[IR_V0];
3181 sysret = do_syscall(env, trapnr,
3182 env->ir[IR_A0], env->ir[IR_A1],
3183 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3184 env->ir[IR_A4], env->ir[IR_A5],
3185 0, 0);
a5b3b13b
RH		 3186 if (trapnr == TARGET_NR_sigreturn
3187 || trapnr == TARGET_NR_rt_sigreturn) {
3188 break;
3189 }
3190 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3191 to how this is handled internal to Linux kernel.
3192 (Ab)use trapnr temporarily as boolean indicating error. */
3193 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3194 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3195 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3196 break;
3197 case 0x86:
3198 /* IMB */
3199 /* ??? We can probably elide the code using page_unprotect
3200 that is checking for self-modifying code. Instead we
3201 could simply call tb_flush here. Until we work out the
3202 changes required to turn off the extra write protection,
3203 this can be a no-op. */
3204 break;
3205 case 0x9E:
3206 /* RDUNIQUE */
3207 /* Handled in the translator for usermode. */
3208 abort();
3209 case 0x9F:
3210 /* WRUNIQUE */
3211 /* Handled in the translator for usermode. */
3212 abort();
3213 case 0xAA:
3214 /* GENTRAP */
3215 info.si_signo = TARGET_SIGFPE;
3216 switch (env->ir[IR_A0]) {
3217 case TARGET_GEN_INTOVF:
3218 info.si_code = TARGET_FPE_INTOVF;
3219 break;
3220 case TARGET_GEN_INTDIV:
3221 info.si_code = TARGET_FPE_INTDIV;
3222 break;
3223 case TARGET_GEN_FLTOVF:
3224 info.si_code = TARGET_FPE_FLTOVF;
3225 break;
3226 case TARGET_GEN_FLTUND:
3227 info.si_code = TARGET_FPE_FLTUND;
3228 break;
3229 case TARGET_GEN_FLTINV:
3230 info.si_code = TARGET_FPE_FLTINV;
3231 break;
3232 case TARGET_GEN_FLTINE:
3233 info.si_code = TARGET_FPE_FLTRES;
3234 break;
3235 case TARGET_GEN_ROPRAND:
3236 info.si_code = 0;
3237 break;
3238 default:
3239 info.si_signo = TARGET_SIGTRAP;
3240 info.si_code = 0;
3241 break;
3242 }
3243 info.si_errno = 0;
3244 info._sifields._sigfault._addr = env->pc;
3245 queue_signal(env, info.si_signo, &info);
3246 break;
3247 default:
3248 goto do_sigill;
3249 }
7a3148a9 3250 break;
7a3148a9 3251 case EXCP_DEBUG:
db6b81d4 3252 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3253 if (info.si_signo) {
6910b8f6 3254 env->lock_addr = -1;
6049f4f8
RH		 3255 info.si_errno = 0;
3256 info.si_code = TARGET_TRAP_BRKPT;
3257 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3258 }
3259 break;
6910b8f6
RH		 3260 case EXCP_STL_C:
3261 case EXCP_STQ_C:
3262 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3263 break;
d0f20495
RH		 3264 case EXCP_INTERRUPT:
3265 /* Just indicate that signals should be handled asap. */
3266 break;
7a3148a9
JM		 3267 default:
3268 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3269 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3270 exit (1);
3271 }
3272 process_pending_signals (env);
3273 }
3274}
3275#endif /* TARGET_ALPHA */
3276
a4c075f1
UH		 3277#ifdef TARGET_S390X
3278void cpu_loop(CPUS390XState *env)
3279{
878096ee 3280 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3281 int trapnr, n, sig;
a4c075f1 3282 target_siginfo_t info;
d5a103cd 3283 target_ulong addr;
a4c075f1
UH		 3284
3285 while (1) {
d5a103cd 3286 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3287 switch (trapnr) {
3288 case EXCP_INTERRUPT:
d5a103cd 3289 /* Just indicate that signals should be handled asap. */
a4c075f1 3290 break;
a4c075f1 3291
d5a103cd
RH		 3292 case EXCP_SVC:
3293 n = env->int_svc_code;
3294 if (!n) {
3295 /* syscalls > 255 */
3296 n = env->regs[1];
a4c075f1 3297 }
d5a103cd
RH		 3298 env->psw.addr += env->int_svc_ilen;
3299 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3300 env->regs[4], env->regs[5],
3301 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3302 break;
d5a103cd
RH		 3303
3304 case EXCP_DEBUG:
db6b81d4 3305 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3306 if (sig) {
3307 n = TARGET_TRAP_BRKPT;
3308 goto do_signal_pc;
a4c075f1
UH		 3309 }
3310 break;
d5a103cd
RH		 3311 case EXCP_PGM:
3312 n = env->int_pgm_code;
3313 switch (n) {
3314 case PGM_OPERATION:
3315 case PGM_PRIVILEGED:
3316 sig = SIGILL;
3317 n = TARGET_ILL_ILLOPC;
3318 goto do_signal_pc;
3319 case PGM_PROTECTION:
3320 case PGM_ADDRESSING:
3321 sig = SIGSEGV;
a4c075f1 3322 /* XXX: check env->error_code */
d5a103cd
RH		 3323 n = TARGET_SEGV_MAPERR;
3324 addr = env->__excp_addr;
3325 goto do_signal;
3326 case PGM_EXECUTE:
3327 case PGM_SPECIFICATION:
3328 case PGM_SPECIAL_OP:
3329 case PGM_OPERAND:
3330 do_sigill_opn:
3331 sig = SIGILL;
3332 n = TARGET_ILL_ILLOPN;
3333 goto do_signal_pc;
3334
3335 case PGM_FIXPT_OVERFLOW:
3336 sig = SIGFPE;
3337 n = TARGET_FPE_INTOVF;
3338 goto do_signal_pc;
3339 case PGM_FIXPT_DIVIDE:
3340 sig = SIGFPE;
3341 n = TARGET_FPE_INTDIV;
3342 goto do_signal_pc;
3343
3344 case PGM_DATA:
3345 n = (env->fpc >> 8) & 0xff;
3346 if (n == 0xff) {
3347 /* compare-and-trap */
3348 goto do_sigill_opn;
3349 } else {
3350 /* An IEEE exception, simulated or otherwise. */
3351 if (n & 0x80) {
3352 n = TARGET_FPE_FLTINV;
3353 } else if (n & 0x40) {
3354 n = TARGET_FPE_FLTDIV;
3355 } else if (n & 0x20) {
3356 n = TARGET_FPE_FLTOVF;
3357 } else if (n & 0x10) {
3358 n = TARGET_FPE_FLTUND;
3359 } else if (n & 0x08) {
3360 n = TARGET_FPE_FLTRES;
3361 } else {
3362 /* ??? Quantum exception; BFP, DFP error. */
3363 goto do_sigill_opn;
3364 }
3365 sig = SIGFPE;
3366 goto do_signal_pc;
3367 }
3368
3369 default:
3370 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3371 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3372 exit(1);
a4c075f1
UH		 3373 }
3374 break;
d5a103cd
RH		 3375
3376 do_signal_pc:
3377 addr = env->psw.addr;
3378 do_signal:
3379 info.si_signo = sig;
3380 info.si_errno = 0;
3381 info.si_code = n;
3382 info._sifields._sigfault._addr = addr;
3383 queue_signal(env, info.si_signo, &info);
a4c075f1 3384 break;
d5a103cd 3385
a4c075f1 3386 default:
d5a103cd 3387 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3388 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3389 exit(1);
a4c075f1
UH		 3390 }
3391 process_pending_signals (env);
3392 }
3393}
3394
3395#endif /* TARGET_S390X */
3396
a2247f8e 3397THREAD CPUState *thread_cpu;
59faf6d6 3398
edf8e2af
MW		 3399void task_settid(TaskState *ts)
3400{
3401 if (ts->ts_tid == 0) {
edf8e2af 3402 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3403 }
3404}
3405
3406void stop_all_tasks(void)
3407{
3408 /*
3409 * We trust that when using NPTL, start_exclusive()
3410 * handles thread stopping correctly.
3411 */
3412 start_exclusive();
3413}
3414
c3a92833 3415/* Assumes contents are already zeroed. */
624f7979
PB		 3416void init_task_state(TaskState *ts)
3417{
3418 int i;
3419
624f7979
PB		 3420 ts->used = 1;
3421 ts->first_free = ts->sigqueue_table;
3422 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3423 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3424 }
3425 ts->sigqueue_table[i].next = NULL;
3426}
fc9c5412 3427
30ba0ee5
AF		 3428CPUArchState *cpu_copy(CPUArchState *env)
3429{
ff4700b0 3430 CPUState *cpu = ENV_GET_CPU(env);
51fb256a 3431 CPUArchState *new_env = cpu_init(cpu_model);
75a34036 3432 CPUState *new_cpu = ENV_GET_CPU(new_env);
30ba0ee5
AF		 3433#if defined(TARGET_HAS_ICE)
3434 CPUBreakpoint *bp;
3435 CPUWatchpoint *wp;
3436#endif
3437
3438 /* Reset non arch specific state */
75a34036 3439 cpu_reset(new_cpu);
30ba0ee5
AF		 3440
3441 memcpy(new_env, env, sizeof(CPUArchState));
3442
3443 /* Clone all break/watchpoints.
3444 Note: Once we support ptrace with hw-debug register access, make sure
3445 BP_CPU break/watchpoints are handled correctly on clone. */
f0c3c505 3446 QTAILQ_INIT(&cpu->breakpoints);
ff4700b0 3447 QTAILQ_INIT(&cpu->watchpoints);
30ba0ee5 3448#if defined(TARGET_HAS_ICE)
f0c3c505 3449 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3450 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3451 }
ff4700b0 3452 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
75a34036 3453 cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1,
30ba0ee5
AF		 3454 wp->flags, NULL);
3455 }
3456#endif
3457
3458 return new_env;
3459}
3460
fc9c5412
JS		 3461static void handle_arg_help(const char *arg)
3462{
3463 usage();
3464}
3465
3466static void handle_arg_log(const char *arg)
3467{
3468 int mask;
fc9c5412 3469
4fde1eba 3470 mask = qemu_str_to_log_mask(arg);
fc9c5412 3471 if (!mask) {
59a6fa6e 3472 qemu_print_log_usage(stdout);
fc9c5412
JS		 3473 exit(1);
3474 }
24537a01 3475 qemu_set_log(mask);
fc9c5412
JS		 3476}
3477
50171d42
CWR		 3478static void handle_arg_log_filename(const char *arg)
3479{
9a7e5424 3480 qemu_set_log_filename(arg);
50171d42
CWR		 3481}
3482
fc9c5412
JS		 3483static void handle_arg_set_env(const char *arg)
3484{
3485 char *r, *p, *token;
3486 r = p = strdup(arg);
3487 while ((token = strsep(&p, ",")) != NULL) {
3488 if (envlist_setenv(envlist, token) != 0) {
3489 usage();
3490 }
3491 }
3492 free(r);
3493}
3494
3495static void handle_arg_unset_env(const char *arg)
3496{
3497 char *r, *p, *token;
3498 r = p = strdup(arg);
3499 while ((token = strsep(&p, ",")) != NULL) {
3500 if (envlist_unsetenv(envlist, token) != 0) {
3501 usage();
3502 }
3503 }
3504 free(r);
3505}
3506
3507static void handle_arg_argv0(const char *arg)
3508{
3509 argv0 = strdup(arg);
3510}
3511
3512static void handle_arg_stack_size(const char *arg)
3513{
3514 char *p;
3515 guest_stack_size = strtoul(arg, &p, 0);
3516 if (guest_stack_size == 0) {
3517 usage();
3518 }
3519
3520 if (*p == 'M') {
3521 guest_stack_size *= 1024 * 1024;
3522 } else if (*p == 'k' || *p == 'K') {
3523 guest_stack_size *= 1024;
3524 }
3525}
3526
3527static void handle_arg_ld_prefix(const char *arg)
3528{
3529 interp_prefix = strdup(arg);
3530}
3531
3532static void handle_arg_pagesize(const char *arg)
3533{
3534 qemu_host_page_size = atoi(arg);
3535 if (qemu_host_page_size == 0 ||
3536 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3537 fprintf(stderr, "page size must be a power of two\n");
3538 exit(1);
3539 }
3540}
3541
3542static void handle_arg_gdb(const char *arg)
3543{
3544 gdbstub_port = atoi(arg);
3545}
3546
3547static void handle_arg_uname(const char *arg)
3548{
3549 qemu_uname_release = strdup(arg);
3550}
3551
3552static void handle_arg_cpu(const char *arg)
3553{
3554 cpu_model = strdup(arg);
c8057f95 3555 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3556 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3557#if defined(cpu_list)
3558 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3559#endif
3560 exit(1);
3561 }
3562}
3563
3564#if defined(CONFIG_USE_GUEST_BASE)
3565static void handle_arg_guest_base(const char *arg)
3566{
3567 guest_base = strtol(arg, NULL, 0);
3568 have_guest_base = 1;
3569}
3570
3571static void handle_arg_reserved_va(const char *arg)
3572{
3573 char *p;
3574 int shift = 0;
3575 reserved_va = strtoul(arg, &p, 0);
3576 switch (*p) {
3577 case 'k':
3578 case 'K':
3579 shift = 10;
3580 break;
3581 case 'M':
3582 shift = 20;
3583 break;
3584 case 'G':
3585 shift = 30;
3586 break;
3587 }
3588 if (shift) {
3589 unsigned long unshifted = reserved_va;
3590 p++;
3591 reserved_va <<= shift;
3592 if (((reserved_va >> shift) != unshifted)
3593#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3594 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3595#endif
3596 ) {
3597 fprintf(stderr, "Reserved virtual address too big\n");
3598 exit(1);
3599 }
3600 }
3601 if (*p) {
3602 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3603 exit(1);
3604 }
3605}
3606#endif
3607
3608static void handle_arg_singlestep(const char *arg)
3609{
3610 singlestep = 1;
3611}
3612
3613static void handle_arg_strace(const char *arg)
3614{
3615 do_strace = 1;
3616}
3617
3618static void handle_arg_version(const char *arg)
3619{
2e59915d 3620 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3621 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3622 exit(0);
fc9c5412
JS		 3623}
3624
3625struct qemu_argument {
3626 const char *argv;
3627 const char *env;
3628 bool has_arg;
3629 void (*handle_opt)(const char *arg);
3630 const char *example;
3631 const char *help;
3632};
3633
42644cee 3634static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3635 {"h", "", false, handle_arg_help,
3636 "", "print this help"},
3637 {"g", "QEMU_GDB", true, handle_arg_gdb,
3638 "port", "wait gdb connection to 'port'"},
3639 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3640 "path", "set the elf interpreter prefix to 'path'"},
3641 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3642 "size", "set the stack size to 'size' bytes"},
3643 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3644 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3645 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3646 "var=value", "sets targets environment variable (see below)"},
3647 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3648 "var", "unsets targets environment variable (see below)"},
3649 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3650 "argv0", "forces target process argv[0] to be 'argv0'"},
3651 {"r", "QEMU_UNAME", true, handle_arg_uname,
3652 "uname", "set qemu uname release string to 'uname'"},
3653#if defined(CONFIG_USE_GUEST_BASE)
3654 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3655 "address", "set guest_base address to 'address'"},
3656 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3657 "size", "reserve 'size' bytes for guest virtual address space"},
3658#endif
3659 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3660 "item[,...]", "enable logging of specified items "
3661 "(use '-d help' for a list of items)"},
50171d42 3662 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3663 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3664 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3665 "pagesize", "set the host page size to 'pagesize'"},
3666 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3667 "", "run in singlestep mode"},
3668 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3669 "", "log system calls"},
3670 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3671 "", "display version information and exit"},
fc9c5412
JS		 3672 {NULL, NULL, false, NULL, NULL, NULL}
3673};
3674
3675static void usage(void)
3676{
42644cee 3677 const struct qemu_argument *arginfo;
fc9c5412
JS		 3678 int maxarglen;
3679 int maxenvlen;
3680
2e59915d
PB		 3681 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3682 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3683 "\n"
3684 "Options and associated environment variables:\n"
3685 "\n");
3686
63ec54d7
PM		 3687 /* Calculate column widths. We must always have at least enough space
3688 * for the column header.
3689 */
3690 maxarglen = strlen("Argument");
3691 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3692
3693 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3694 int arglen = strlen(arginfo->argv);
3695 if (arginfo->has_arg) {
3696 arglen += strlen(arginfo->example) + 1;
3697 }
fc9c5412
JS		 3698 if (strlen(arginfo->env) > maxenvlen) {
3699 maxenvlen = strlen(arginfo->env);
3700 }
63ec54d7
PM		 3701 if (arglen > maxarglen) {
3702 maxarglen = arglen;
fc9c5412
JS		 3703 }
3704 }
3705
63ec54d7
PM		 3706 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3707 maxenvlen, "Env-variable");
fc9c5412
JS		 3708
3709 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3710 if (arginfo->has_arg) {
3711 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3712 (int)(maxarglen - strlen(arginfo->argv) - 1),
3713 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3714 } else {
63ec54d7 3715 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3716 maxenvlen, arginfo->env,
3717 arginfo->help);
3718 }
3719 }
3720
3721 printf("\n"
3722 "Defaults:\n"
3723 "QEMU_LD_PREFIX = %s\n"
989b697d 3724 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3725 interp_prefix,
989b697d 3726 guest_stack_size);
fc9c5412
JS		 3727
3728 printf("\n"
3729 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3730 "QEMU_UNSET_ENV environment variables to set and unset\n"
3731 "environment variables for the target process.\n"
3732 "It is possible to provide several variables by separating them\n"
3733 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3734 "provide the -E and -U options multiple times.\n"
3735 "The following lines are equivalent:\n"
3736 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3737 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3738 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3739 "Note that if you provide several changes to a single variable\n"
3740 "the last change will stay in effect.\n");
3741
3742 exit(1);
3743}
3744
3745static int parse_args(int argc, char **argv)
3746{
3747 const char *r;
3748 int optind;
42644cee 3749 const struct qemu_argument *arginfo;
fc9c5412
JS		 3750
3751 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3752 if (arginfo->env == NULL) {
3753 continue;
3754 }
3755
3756 r = getenv(arginfo->env);
3757 if (r != NULL) {
3758 arginfo->handle_opt(r);
3759 }
3760 }
3761
3762 optind = 1;
3763 for (;;) {
3764 if (optind >= argc) {
3765 break;
3766 }
3767 r = argv[optind];
3768 if (r[0] != '-') {
3769 break;
3770 }
3771 optind++;
3772 r++;
3773 if (!strcmp(r, "-")) {
3774 break;
3775 }
3776
3777 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3778 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3779 if (arginfo->has_arg) {
1386d4c0
PM		 3780 if (optind >= argc) {
3781 usage();
3782 }
3783 arginfo->handle_opt(argv[optind]);
fc9c5412 3784 optind++;
1386d4c0
PM		 3785 } else {
3786 arginfo->handle_opt(NULL);
fc9c5412 3787 }
fc9c5412
JS		 3788 break;
3789 }
3790 }
3791
3792 /* no option matched the current argv */
3793 if (arginfo->handle_opt == NULL) {
3794 usage();
3795 }
3796 }
3797
3798 if (optind >= argc) {
3799 usage();
3800 }
3801
3802 filename = argv[optind];
3803 exec_path = argv[optind];
3804
3805 return optind;
3806}
3807
902b3d5c 3808int main(int argc, char **argv, char **envp)
31e31b8a 3809{
01ffc75b 3810 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3811 struct image_info info1, *info = &info1;
edf8e2af 3812 struct linux_binprm bprm;
48e15fc2 3813 TaskState *ts;
9349b4f9 3814 CPUArchState *env;
db6b81d4 3815 CPUState *cpu;
586314f2 3816 int optind;
04a6dfeb 3817 char **target_environ, **wrk;
7d8cec95
AJ		 3818 char **target_argv;
3819 int target_argc;
7d8cec95 3820 int i;
fd4d81dd 3821 int ret;
03cfd8fa 3822 int execfd;
b12b6a18 3823
ce008c1f
AF		 3824 module_call_init(MODULE_INIT_QOM);
3825
b6a3e690 3826 qemu_init_auxval(envp);
664d2c44 3827 qemu_cache_utils_init();
902b3d5c 3828
04a6dfeb
AJ		 3829 if ((envlist = envlist_create()) == NULL) {
3830 (void) fprintf(stderr, "Unable to allocate envlist\n");
3831 exit(1);
3832 }
3833
3834 /* add current environment into the list */
3835 for (wrk = environ; *wrk != NULL; wrk++) {
3836 (void) envlist_setenv(envlist, *wrk);
3837 }
3838
703e0e89
RH		 3839 /* Read the stack limit from the kernel. If it's "unlimited",
3840 then we can do little else besides use the default. */
3841 {
3842 struct rlimit lim;
3843 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3844 && lim.rlim_cur != RLIM_INFINITY
3845 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3846 guest_stack_size = lim.rlim_cur;
3847 }
3848 }
3849
b1f9be31 3850 cpu_model = NULL;
b5ec5ce0 3851#if defined(cpudef_setup)
3852 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3853#endif
3854
fc9c5412 3855 optind = parse_args(argc, argv);
586314f2 3856
31e31b8a 3857 /* Zero out regs */
01ffc75b 3858 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3859
3860 /* Zero out image_info */
3861 memset(info, 0, sizeof(struct image_info));
3862
edf8e2af
MW		 3863 memset(&bprm, 0, sizeof (bprm));
3864
74cd30b8
FB		 3865 /* Scan interp_prefix dir for replacement files. */
3866 init_paths(interp_prefix);
3867
4a24a758
PM		 3868 init_qemu_uname_release();
3869
46027c07 3870 if (cpu_model == NULL) {
aaed909a 3871#if defined(TARGET_I386)
46027c07
FB		 3872#ifdef TARGET_X86_64
3873 cpu_model = "qemu64";
3874#else
3875 cpu_model = "qemu32";
3876#endif
aaed909a 3877#elif defined(TARGET_ARM)
088ab16c 3878 cpu_model = "any";
d2fbca94
GX		 3879#elif defined(TARGET_UNICORE32)
3880 cpu_model = "any";
aaed909a
FB		 3881#elif defined(TARGET_M68K)
3882 cpu_model = "any";
3883#elif defined(TARGET_SPARC)
3884#ifdef TARGET_SPARC64
3885 cpu_model = "TI UltraSparc II";
3886#else
3887 cpu_model = "Fujitsu MB86904";
46027c07 3888#endif
aaed909a
FB		 3889#elif defined(TARGET_MIPS)
3890#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3891 cpu_model = "20Kc";
3892#else
3893 cpu_model = "24Kf";
3894#endif
d962783e
JL		 3895#elif defined TARGET_OPENRISC
3896 cpu_model = "or1200";
aaed909a 3897#elif defined(TARGET_PPC)
7ded4f52 3898#ifdef TARGET_PPC64
f7177937 3899 cpu_model = "970fx";
7ded4f52 3900#else
aaed909a 3901 cpu_model = "750";
7ded4f52 3902#endif
aaed909a
FB		 3903#else
3904 cpu_model = "any";
3905#endif
3906 }
d5ab9713
JK		 3907 tcg_exec_init(0);
3908 cpu_exec_init_all();
83fb7adf
FB		 3909 /* NOTE: we need to init the CPU at this stage to get
3910 qemu_host_page_size */
aaed909a
FB		 3911 env = cpu_init(cpu_model);
3912 if (!env) {
3913 fprintf(stderr, "Unable to find CPU definition\n");
3914 exit(1);
3915 }
db6b81d4 3916 cpu = ENV_GET_CPU(env);
0ac46af3 3917 cpu_reset(cpu);
b55a37c9 3918
db6b81d4 3919 thread_cpu = cpu;
3b46e624 3920
b6741956
FB		 3921 if (getenv("QEMU_STRACE")) {
3922 do_strace = 1;
b92c47c1
TS		 3923 }
3924
04a6dfeb
AJ		 3925 target_environ = envlist_to_environ(envlist, NULL);
3926 envlist_free(envlist);
b12b6a18 3927
379f6698
PB		 3928#if defined(CONFIG_USE_GUEST_BASE)
3929 /*
3930 * Now that page sizes are configured in cpu_init() we can do
3931 * proper page alignment for guest_base.
3932 */
3933 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3934
806d1021
MI		 3935 if (reserved_va || have_guest_base) {
3936 guest_base = init_guest_space(guest_base, reserved_va, 0,
3937 have_guest_base);
3938 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3939 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3940 "space for use as guest address space (check your virtual "
3941 "memory ulimit setting or reserve less using -R option)\n",
3942 reserved_va);
68a1c816
PB		 3943 exit(1);
3944 }
97cc7560 3945
806d1021
MI		 3946 if (reserved_va) {
3947 mmap_next_start = reserved_va;
97cc7560
DDAG		 3948 }
3949 }
14f24e14 3950#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3951
3952 /*
3953 * Read in mmap_min_addr kernel parameter. This value is used
3954 * When loading the ELF image to determine whether guest_base
14f24e14 3955 * is needed. It is also used in mmap_find_vma.
379f6698 3956 */
14f24e14 3957 {
379f6698
PB		 3958 FILE *fp;
3959
3960 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3961 unsigned long tmp;
3962 if (fscanf(fp, "%lu", &tmp) == 1) {
3963 mmap_min_addr = tmp;
3964 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3965 }
3966 fclose(fp);
3967 }
3968 }
379f6698 3969
7d8cec95
AJ		 3970 /*
3971 * Prepare copy of argv vector for target.
3972 */
3973 target_argc = argc - optind;
3974 target_argv = calloc(target_argc + 1, sizeof (char *));
3975 if (target_argv == NULL) {
3976 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3977 exit(1);
3978 }
3979
3980 /*
3981 * If argv0 is specified (using '-0' switch) we replace
3982 * argv[0] pointer with the given one.
3983 */
3984 i = 0;
3985 if (argv0 != NULL) {
3986 target_argv[i++] = strdup(argv0);
3987 }
3988 for (; i < target_argc; i++) {
3989 target_argv[i] = strdup(argv[optind + i]);
3990 }
3991 target_argv[target_argc] = NULL;
3992
7267c094 3993 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3994 init_task_state(ts);
3995 /* build Task State */
3996 ts->info = info;
3997 ts->bprm = &bprm;
0429a971 3998 cpu->opaque = ts;
edf8e2af
MW		 3999 task_settid(ts);
4000
0b959cf5
RH		 4001 execfd = qemu_getauxval(AT_EXECFD);
4002 if (execfd == 0) {
03cfd8fa 4003 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4004 if (execfd < 0) {
4005 printf("Error while loading %s: %s\n", filename, strerror(errno));
4006 _exit(1);
4007 }
03cfd8fa
LV		 4008 }
4009
4010 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4011 info, &bprm);
4012 if (ret != 0) {
885c1d10 4013 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4014 _exit(1);
4015 }
4016
4017 for (wrk = target_environ; *wrk; wrk++) {
4018 free(*wrk);
31e31b8a 4019 }
3b46e624 4020
b12b6a18
TS		 4021 free(target_environ);
4022
2e77eac6 4023 if (qemu_log_enabled()) {
379f6698
PB		 4024#if defined(CONFIG_USE_GUEST_BASE)
4025 qemu_log("guest_base 0x%lx\n", guest_base);
4026#endif
2e77eac6
BS		 4027 log_page_dump();
4028
4029 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4030 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4031 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4032 info->start_code);
4033 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4034 info->start_data);
4035 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4036 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4037 info->start_stack);
4038 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4039 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4040 }
31e31b8a 4041
53a5960a 4042 target_set_brk(info->brk);
31e31b8a 4043 syscall_init();
66fb9763 4044 signal_init();
31e31b8a 4045
9002ec79
RH		 4046#if defined(CONFIG_USE_GUEST_BASE)
4047 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4048 generating the prologue until now so that the prologue can take
4049 the real value of GUEST_BASE into account. */
4050 tcg_prologue_init(&tcg_ctx);
4051#endif
4052
b346ff46 4053#if defined(TARGET_I386)
3802ce26 4054 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4055 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4056 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4057 env->cr[4] |= CR4_OSFXSR_MASK;
4058 env->hflags |= HF_OSFXSR_MASK;
4059 }
d2fd1af7 4060#ifndef TARGET_ABI32
4dbc422b 4061 /* enable 64 bit mode if possible */
0514ef2f 4062 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4063 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4064 exit(1);
4065 }
d2fd1af7 4066 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4067 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4068 env->hflags |= HF_LMA_MASK;
4069#endif
1bde465e 4070
415e561f
FB		 4071 /* flags setup : we activate the IRQs by default as in user mode */
4072 env->eflags |= IF_MASK;
3b46e624 4073
6dbad63e 4074 /* linux register setup */
d2fd1af7 4075#ifndef TARGET_ABI32
84409ddb
JM		 4076 env->regs[R_EAX] = regs->rax;
4077 env->regs[R_EBX] = regs->rbx;
4078 env->regs[R_ECX] = regs->rcx;
4079 env->regs[R_EDX] = regs->rdx;
4080 env->regs[R_ESI] = regs->rsi;
4081 env->regs[R_EDI] = regs->rdi;
4082 env->regs[R_EBP] = regs->rbp;
4083 env->regs[R_ESP] = regs->rsp;
4084 env->eip = regs->rip;
4085#else
0ecfa993
FB		 4086 env->regs[R_EAX] = regs->eax;
4087 env->regs[R_EBX] = regs->ebx;
4088 env->regs[R_ECX] = regs->ecx;
4089 env->regs[R_EDX] = regs->edx;
4090 env->regs[R_ESI] = regs->esi;
4091 env->regs[R_EDI] = regs->edi;
4092 env->regs[R_EBP] = regs->ebp;
4093 env->regs[R_ESP] = regs->esp;
dab2ed99 4094 env->eip = regs->eip;
84409ddb 4095#endif
31e31b8a 4096
f4beb510 4097 /* linux interrupt setup */
e441570f
AZ		 4098#ifndef TARGET_ABI32
4099 env->idt.limit = 511;
4100#else
4101 env->idt.limit = 255;
4102#endif
4103 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4104 PROT_READ|PROT_WRITE,
4105 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4106 idt_table = g2h(env->idt.base);
f4beb510
FB		 4107 set_idt(0, 0);
4108 set_idt(1, 0);
4109 set_idt(2, 0);
4110 set_idt(3, 3);
4111 set_idt(4, 3);
ec95da6c 4112 set_idt(5, 0);
f4beb510
FB		 4113 set_idt(6, 0);
4114 set_idt(7, 0);
4115 set_idt(8, 0);
4116 set_idt(9, 0);
4117 set_idt(10, 0);
4118 set_idt(11, 0);
4119 set_idt(12, 0);
4120 set_idt(13, 0);
4121 set_idt(14, 0);
4122 set_idt(15, 0);
4123 set_idt(16, 0);
4124 set_idt(17, 0);
4125 set_idt(18, 0);
4126 set_idt(19, 0);
4127 set_idt(0x80, 3);
4128
6dbad63e 4129 /* linux segment setup */
8d18e893
FB		 4130 {
4131 uint64_t *gdt_table;
e441570f
AZ		 4132 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4133 PROT_READ|PROT_WRITE,
4134 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4135 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4136 gdt_table = g2h(env->gdt.base);
d2fd1af7 4137#ifdef TARGET_ABI32
8d18e893
FB		 4138 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4139 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4140 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4141#else
4142 /* 64 bit code segment */
4143 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4144 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4145 DESC_L_MASK |
4146 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4147#endif
8d18e893
FB		 4148 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4149 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4150 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4151 }
6dbad63e 4152 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4153 cpu_x86_load_seg(env, R_SS, __USER_DS);
4154#ifdef TARGET_ABI32
6dbad63e
FB		 4155 cpu_x86_load_seg(env, R_DS, __USER_DS);
4156 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4157 cpu_x86_load_seg(env, R_FS, __USER_DS);
4158 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4159 /* This hack makes Wine work... */
4160 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4161#else
4162 cpu_x86_load_seg(env, R_DS, 0);
4163 cpu_x86_load_seg(env, R_ES, 0);
4164 cpu_x86_load_seg(env, R_FS, 0);
4165 cpu_x86_load_seg(env, R_GS, 0);
4166#endif
99033cae
AG		 4167#elif defined(TARGET_AARCH64)
4168 {
4169 int i;
4170
4171 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4172 fprintf(stderr,
4173 "The selected ARM CPU does not support 64 bit mode\n");
4174 exit(1);
4175 }
4176
4177 for (i = 0; i < 31; i++) {
4178 env->xregs[i] = regs->regs[i];
4179 }
4180 env->pc = regs->pc;
4181 env->xregs[31] = regs->sp;
4182 }
b346ff46
FB		 4183#elif defined(TARGET_ARM)
4184 {
4185 int i;
b5ff1b31 4186 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4187 for(i = 0; i < 16; i++) {
4188 env->regs[i] = regs->uregs[i];
4189 }
d8fd2954
PB		 4190 /* Enable BE8. */
4191 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4192 && (info->elf_flags & EF_ARM_BE8)) {
4193 env->bswap_code = 1;
4194 }
b346ff46 4195 }
d2fbca94
GX		 4196#elif defined(TARGET_UNICORE32)
4197 {
4198 int i;
4199 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4200 for (i = 0; i < 32; i++) {
4201 env->regs[i] = regs->uregs[i];
4202 }
4203 }
93ac68bc 4204#elif defined(TARGET_SPARC)
060366c5
FB		 4205 {
4206 int i;
4207 env->pc = regs->pc;
4208 env->npc = regs->npc;
4209 env->y = regs->y;
4210 for(i = 0; i < 8; i++)
4211 env->gregs[i] = regs->u_regs[i];
4212 for(i = 0; i < 8; i++)
4213 env->regwptr[i] = regs->u_regs[i + 8];
4214 }
67867308
FB		 4215#elif defined(TARGET_PPC)
4216 {
4217 int i;
3fc6c082 4218
0411a972
JM		 4219#if defined(TARGET_PPC64)
4220#if defined(TARGET_ABI32)
4221 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4222#else
0411a972
JM		 4223 env->msr |= (target_ulong)1 << MSR_SF;
4224#endif
84409ddb 4225#endif
67867308
FB		 4226 env->nip = regs->nip;
4227 for(i = 0; i < 32; i++) {
4228 env->gpr[i] = regs->gpr[i];
4229 }
4230 }
e6e5906b
PB		 4231#elif defined(TARGET_M68K)
4232 {
e6e5906b
PB		 4233 env->pc = regs->pc;
4234 env->dregs[0] = regs->d0;
4235 env->dregs[1] = regs->d1;
4236 env->dregs[2] = regs->d2;
4237 env->dregs[3] = regs->d3;
4238 env->dregs[4] = regs->d4;
4239 env->dregs[5] = regs->d5;
4240 env->dregs[6] = regs->d6;
4241 env->dregs[7] = regs->d7;
4242 env->aregs[0] = regs->a0;
4243 env->aregs[1] = regs->a1;
4244 env->aregs[2] = regs->a2;
4245 env->aregs[3] = regs->a3;
4246 env->aregs[4] = regs->a4;
4247 env->aregs[5] = regs->a5;
4248 env->aregs[6] = regs->a6;
4249 env->aregs[7] = regs->usp;
4250 env->sr = regs->sr;
4251 ts->sim_syscalls = 1;
4252 }
b779e29e
EI		 4253#elif defined(TARGET_MICROBLAZE)
4254 {
4255 env->regs[0] = regs->r0;
4256 env->regs[1] = regs->r1;
4257 env->regs[2] = regs->r2;
4258 env->regs[3] = regs->r3;
4259 env->regs[4] = regs->r4;
4260 env->regs[5] = regs->r5;
4261 env->regs[6] = regs->r6;
4262 env->regs[7] = regs->r7;
4263 env->regs[8] = regs->r8;
4264 env->regs[9] = regs->r9;
4265 env->regs[10] = regs->r10;
4266 env->regs[11] = regs->r11;
4267 env->regs[12] = regs->r12;
4268 env->regs[13] = regs->r13;
4269 env->regs[14] = regs->r14;
4270 env->regs[15] = regs->r15;
4271 env->regs[16] = regs->r16;
4272 env->regs[17] = regs->r17;
4273 env->regs[18] = regs->r18;
4274 env->regs[19] = regs->r19;
4275 env->regs[20] = regs->r20;
4276 env->regs[21] = regs->r21;
4277 env->regs[22] = regs->r22;
4278 env->regs[23] = regs->r23;
4279 env->regs[24] = regs->r24;
4280 env->regs[25] = regs->r25;
4281 env->regs[26] = regs->r26;
4282 env->regs[27] = regs->r27;
4283 env->regs[28] = regs->r28;
4284 env->regs[29] = regs->r29;
4285 env->regs[30] = regs->r30;
4286 env->regs[31] = regs->r31;
4287 env->sregs[SR_PC] = regs->pc;
4288 }
048f6b4d
FB		 4289#elif defined(TARGET_MIPS)
4290 {
4291 int i;
4292
4293 for(i = 0; i < 32; i++) {
b5dc7732 4294 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4295 }
0fddbbf2
NF		 4296 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4297 if (regs->cp0_epc & 1) {
4298 env->hflags |= MIPS_HFLAG_M16;
4299 }
048f6b4d 4300 }
d962783e
JL		 4301#elif defined(TARGET_OPENRISC)
4302 {
4303 int i;
4304
4305 for (i = 0; i < 32; i++) {
4306 env->gpr[i] = regs->gpr[i];
4307 }
4308
4309 env->sr = regs->sr;
4310 env->pc = regs->pc;
4311 }
fdf9b3e8
FB		 4312#elif defined(TARGET_SH4)
4313 {
4314 int i;
4315
4316 for(i = 0; i < 16; i++) {
4317 env->gregs[i] = regs->regs[i];
4318 }
4319 env->pc = regs->pc;
4320 }
7a3148a9
JM		 4321#elif defined(TARGET_ALPHA)
4322 {
4323 int i;
4324
4325 for(i = 0; i < 28; i++) {
992f48a0 4326 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4327 }
dad081ee 4328 env->ir[IR_SP] = regs->usp;
7a3148a9 4329 env->pc = regs->pc;
7a3148a9 4330 }
48733d19
TS		 4331#elif defined(TARGET_CRIS)
4332 {
4333 env->regs[0] = regs->r0;
4334 env->regs[1] = regs->r1;
4335 env->regs[2] = regs->r2;
4336 env->regs[3] = regs->r3;
4337 env->regs[4] = regs->r4;
4338 env->regs[5] = regs->r5;
4339 env->regs[6] = regs->r6;
4340 env->regs[7] = regs->r7;
4341 env->regs[8] = regs->r8;
4342 env->regs[9] = regs->r9;
4343 env->regs[10] = regs->r10;
4344 env->regs[11] = regs->r11;
4345 env->regs[12] = regs->r12;
4346 env->regs[13] = regs->r13;
4347 env->regs[14] = info->start_stack;
4348 env->regs[15] = regs->acr;
4349 env->pc = regs->erp;
4350 }
a4c075f1
UH		 4351#elif defined(TARGET_S390X)
4352 {
4353 int i;
4354 for (i = 0; i < 16; i++) {
4355 env->regs[i] = regs->gprs[i];
4356 }
4357 env->psw.mask = regs->psw.mask;
4358 env->psw.addr = regs->psw.addr;
4359 }
b346ff46
FB		 4360#else
4361#error unsupported target CPU
4362#endif
31e31b8a 4363
d2fbca94 4364#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4365 ts->stack_base = info->start_stack;
4366 ts->heap_base = info->brk;
4367 /* This will be filled in on the first SYS_HEAPINFO call. */
4368 ts->heap_limit = 0;
4369#endif
4370
74c33bed 4371 if (gdbstub_port) {
ff7a981a
PM		 4372 if (gdbserver_start(gdbstub_port) < 0) {
4373 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4374 gdbstub_port);
4375 exit(1);
4376 }
db6b81d4 4377 gdb_handlesig(cpu, 0);
1fddef4b 4378 }
1b6b029e
FB		 4379 cpu_loop(env);
4380 /* never exits */
31e31b8a
FB		 4381 return 0;
4382}
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