[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "qemu-timer.h"
#include "sysbus.h"
#include "trace.h"

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

#define MAX_CPUS 16

typedef struct CPUTimerState {
    qemu_irq irq;
    ptimer_state *timer;
    uint32_t count, counthigh, reached;
    /* processor only */
    uint32_t running;
    uint64_t limit;
} CPUTimerState;

typedef struct SLAVIO_TIMERState {
    SysBusDevice busdev;
    uint32_t num_cpus;
    uint32_t cputimer_mode;
    CPUTimerState cputimer[MAX_CPUS + 1];
} SLAVIO_TIMERState;

typedef struct TimerContext {
    SLAVIO_TIMERState *s;
    unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
} TimerContext;

#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10

#define TIMER_LIMIT         0
#define TIMER_COUNTER       1
#define TIMER_COUNTER_NORST 2
#define TIMER_STATUS        3
#define TIMER_MODE          4

#define TIMER_COUNT_MASK32 0xfffffe00
#define TIMER_LIMIT_MASK32 0x7fffffff
#define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
#define TIMER_MAX_COUNT32  0x7ffffe00ULL
#define TIMER_REACHED      0x80000000
#define TIMER_PERIOD       500ULL // 500ns
#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)

static int slavio_timer_is_user(TimerContext *tc)
{
    SLAVIO_TIMERState *s = tc->s;
    unsigned int timer_index = tc->timer_index;

    return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
}

// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(CPUTimerState *t)
{
    uint64_t count, limit;

    if (t->limit == 0) { /* free-run system or processor counter */
        limit = TIMER_MAX_COUNT32;
    } else {
        limit = t->limit;
    }
    count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));

    trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
    t->count = count & TIMER_COUNT_MASK32;
    t->counthigh = count >> 32;
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    CPUTimerState *t = &s->cputimer[tc->timer_index];

    slavio_timer_get_out(t);
    trace_slavio_timer_irq(t->counthigh, t->count);
    /* if limit is 0 (free-run), there will be no match */
    if (t->limit != 0) {
        t->reached = TIMER_REACHED;
    }
    /* there is no interrupt if user timer or free-run */
    if (!slavio_timer_is_user(tc) && t->limit != 0) {
        qemu_irq_raise(t->irq);
    }
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr, ret;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        // read limit (system counter mode) or read most signifying
        // part of counter (user mode)
        if (slavio_timer_is_user(tc)) {
            // read user timer MSW
            slavio_timer_get_out(t);
            ret = t->counthigh | t->reached;
        } else {
            // read limit
            // clear irq
            qemu_irq_lower(t->irq);
            t->reached = 0;
            ret = t->limit & TIMER_LIMIT_MASK32;
        }
        break;
    case TIMER_COUNTER:
        // read counter and reached bit (system mode) or read lsbits
        // of counter (user mode)
        slavio_timer_get_out(t);
        if (slavio_timer_is_user(tc)) { // read user timer LSW
            ret = t->count & TIMER_MAX_COUNT64;
        } else { // read limit
            ret = (t->count & TIMER_MAX_COUNT32) |
                t->reached;
        }
        break;
    case TIMER_STATUS:
        // only available in processor counter/timer
        // read start/stop status
        if (timer_index > 0) {
            ret = t->running;
        } else {
            ret = 0;
        }
        break;
    case TIMER_MODE:
        // only available in system counter
        // read user/system mode
        ret = s->cputimer_mode;
        break;
    default:
        trace_slavio_timer_mem_readl_invalid(addr);
        ret = 0;
        break;
    }
    trace_slavio_timer_mem_readl(addr, ret);
    return ret;
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    trace_slavio_timer_mem_writel(addr, val);
    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter MSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
            t->reached = 0;
            count = ((uint64_t)t->counthigh << 32) | t->count;
            trace_slavio_timer_mem_writel_limit(timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else {
            // set limit, reset counter
            qemu_irq_lower(t->irq);
            t->limit = val & TIMER_MAX_COUNT32;
            if (t->timer) {
                if (t->limit == 0) { /* free-run */
                    ptimer_set_limit(t->timer,
                                     LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
                } else {
                    ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
                }
            }
        }
        break;
    case TIMER_COUNTER:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter LSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->count = val & TIMER_MAX_COUNT64;
            t->reached = 0;
            count = ((uint64_t)t->counthigh) << 32 | t->count;
            trace_slavio_timer_mem_writel_limit(timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else {
            trace_slavio_timer_mem_writel_counter_invalid();
        }
        break;
    case TIMER_COUNTER_NORST:
        // set limit without resetting counter
        t->limit = val & TIMER_MAX_COUNT32;
        if (t->limit == 0) { /* free-run */
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
        } else {
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
        }
        break;
    case TIMER_STATUS:
        if (slavio_timer_is_user(tc)) {
            // start/stop user counter
            if ((val & 1) && !t->running) {
                trace_slavio_timer_mem_writel_status_start(timer_index);
                ptimer_run(t->timer, 0);
                t->running = 1;
            } else if (!(val & 1) && t->running) {
                trace_slavio_timer_mem_writel_status_stop(timer_index);
                ptimer_stop(t->timer);
                t->running = 0;
            }
        }
        break;
    case TIMER_MODE:
        if (timer_index == 0) {
            unsigned int i;

            for (i = 0; i < s->num_cpus; i++) {
                unsigned int processor = 1 << i;
                CPUTimerState *curr_timer = &s->cputimer[i + 1];

                // check for a change in timer mode for this processor
                if ((val & processor) != (s->cputimer_mode & processor)) {
                    if (val & processor) { // counter -> user timer
                        qemu_irq_lower(curr_timer->irq);
                        // counters are always running
                        ptimer_stop(curr_timer->timer);
                        curr_timer->running = 0;
                        // user timer limit is always the same
                        curr_timer->limit = TIMER_MAX_COUNT64;
                        ptimer_set_limit(curr_timer->timer,
                                         LIMIT_TO_PERIODS(curr_timer->limit),
                                         1);
                        // set this processors user timer bit in config
                        // register
                        s->cputimer_mode |= processor;
                        trace_slavio_timer_mem_writel_mode_user(timer_index);
                    } else { // user timer -> counter
                        // stop the user timer if it is running
                        if (curr_timer->running) {
                            ptimer_stop(curr_timer->timer);
                        }
                        // start the counter
                        ptimer_run(curr_timer->timer, 0);
                        curr_timer->running = 1;
                        // clear this processors user timer bit in config
                        // register
                        s->cputimer_mode &= ~processor;
                        trace_slavio_timer_mem_writel_mode_counter(timer_index);
                    }
                }
            }
        } else {
            trace_slavio_timer_mem_writel_mode_invalid();
        }
        break;
    default:
        trace_slavio_timer_mem_writel_invalid(addr);
        break;
    }
}

static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
    NULL,
    NULL,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
    NULL,
    NULL,
    slavio_timer_mem_writel,
};

static const VMStateDescription vmstate_timer = {
    .name ="timer",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(limit, CPUTimerState),
        VMSTATE_UINT32(count, CPUTimerState),
        VMSTATE_UINT32(counthigh, CPUTimerState),
        VMSTATE_UINT32(reached, CPUTimerState),
        VMSTATE_UINT32(running, CPUTimerState),
        VMSTATE_PTIMER(timer, CPUTimerState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_slavio_timer = {
    .name ="slavio_timer",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
                             vmstate_timer, CPUTimerState),
        VMSTATE_END_OF_LIST()
    }
};

static void slavio_timer_reset(DeviceState *d)
{
    SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
    unsigned int i;
    CPUTimerState *curr_timer;

    for (i = 0; i <= MAX_CPUS; i++) {
        curr_timer = &s->cputimer[i];
        curr_timer->limit = 0;
        curr_timer->count = 0;
        curr_timer->reached = 0;
        if (i <= s->num_cpus) {
            ptimer_set_limit(curr_timer->timer,
                             LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
            ptimer_run(curr_timer->timer, 0);
            curr_timer->running = 1;
        }
    }
    s->cputimer_mode = 0;
}

static int slavio_timer_init1(SysBusDevice *dev)
{
    int io;
    SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
    QEMUBH *bh;
    unsigned int i;
    TimerContext *tc;

    for (i = 0; i <= MAX_CPUS; i++) {
        tc = g_malloc0(sizeof(TimerContext));
        tc->s = s;
        tc->timer_index = i;

        bh = qemu_bh_new(slavio_timer_irq, tc);
        s->cputimer[i].timer = ptimer_init(bh);
        ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);

        io = cpu_register_io_memory(slavio_timer_mem_read,
                                    slavio_timer_mem_write, tc,
                                    DEVICE_NATIVE_ENDIAN);
        if (i == 0) {
            sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
        } else {
            sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
        }

        sysbus_init_irq(dev, &s->cputimer[i].irq);
    }

    return 0;
}

static SysBusDeviceInfo slavio_timer_info = {
    .init = slavio_timer_init1,
    .qdev.name  = "slavio_timer",
    .qdev.size  = sizeof(SLAVIO_TIMERState),
    .qdev.vmsd  = &vmstate_slavio_timer,
    .qdev.reset = slavio_timer_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void slavio_timer_register_devices(void)
{
    sysbus_register_withprop(&slavio_timer_info);
}

device_init(slavio_timer_register_devices)
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
c70c59ee	24
87ecb68b PB	25	#include "sun4m.h"
87ecb68b PB	26	#include "qemu-timer.h"
c70c59ee	27	#include "sysbus.h"
97bf4851	28	#include "trace.h"
66321a11	29
e80cfcfc FB	30	/*
	31	* Registers of hardware timer in sun4m.
	32	*
	33	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	34	* produced as NCR89C105. See
	35	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24	36	*
e80cfcfc FB	37	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	38	* are zero. Bit 31 is 1 when count has been reached.
	39	*
ba3c64fb FB	40	* Per-CPU timers interrupt local CPU, system timer uses normal
	41	* interrupt routing.
	42	*
e80cfcfc FB	43	*/
e80cfcfc FB	44
81732d19 BS	45	#define MAX_CPUS 16
81732d19 BS	46
7204ff9c	47	typedef struct CPUTimerState {
d7edfd27	48	qemu_irq irq;
8d05ea8a BS	49	ptimer_state *timer;
8d05ea8a BS	50	uint32_t count, counthigh, reached;
f90074f4	51	/* processor only */
22548760	52	uint32_t running;
f90074f4	53	uint64_t limit;
7204ff9c BS	54	} CPUTimerState;
	55
	56	typedef struct SLAVIO_TIMERState {
	57	SysBusDevice busdev;
	58	uint32_t num_cpus;
7204ff9c	59	uint32_t cputimer_mode;
f90074f4	60	CPUTimerState cputimer[MAX_CPUS + 1];
e80cfcfc FB	61	} SLAVIO_TIMERState;
e80cfcfc FB	62
7204ff9c BS	63	typedef struct TimerContext {
	64	SLAVIO_TIMERState *s;
	65	unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
	66	} TimerContext;
	67
115646b6	68	#define SYS_TIMER_SIZE 0x14
81732d19	69	#define CPU_TIMER_SIZE 0x10
e80cfcfc	70
d2c38b24 BS	71	#define TIMER_LIMIT 0
	72	#define TIMER_COUNTER 1
	73	#define TIMER_COUNTER_NORST 2
	74	#define TIMER_STATUS 3
	75	#define TIMER_MODE 4
	76
	77	#define TIMER_COUNT_MASK32 0xfffffe00
	78	#define TIMER_LIMIT_MASK32 0x7fffffff
	79	#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
	80	#define TIMER_MAX_COUNT32 0x7ffffe00ULL
	81	#define TIMER_REACHED 0x80000000
	82	#define TIMER_PERIOD 500ULL // 500ns
68fb89a2 BS	83	#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
68fb89a2 BS	84	#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
d2c38b24	85
7204ff9c	86	static int slavio_timer_is_user(TimerContext *tc)
115646b6	87	{
7204ff9c BS	88	SLAVIO_TIMERState *s = tc->s;
	89	unsigned int timer_index = tc->timer_index;
	90
	91	return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
115646b6 BS	92	}
115646b6 BS	93
e80cfcfc	94	// Update count, set irq, update expire_time
8d05ea8a	95	// Convert from ptimer countdown units
7204ff9c	96	static void slavio_timer_get_out(CPUTimerState *t)
e80cfcfc	97	{
bd7e2875	98	uint64_t count, limit;
e80cfcfc	99
7204ff9c	100	if (t->limit == 0) { /* free-run system or processor counter */
bd7e2875	101	limit = TIMER_MAX_COUNT32;
7204ff9c BS	102	} else {
	103	limit = t->limit;
	104	}
9ebec28b BS	105	count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
9ebec28b BS	106
97bf4851	107	trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
7204ff9c BS	108	t->count = count & TIMER_COUNT_MASK32;
7204ff9c BS	109	t->counthigh = count >> 32;
e80cfcfc FB	110	}
	111
	112	// timer callback
	113	static void slavio_timer_irq(void *opaque)
	114	{
7204ff9c BS	115	TimerContext *tc = opaque;
	116	SLAVIO_TIMERState *s = tc->s;
	117	CPUTimerState *t = &s->cputimer[tc->timer_index];
	118
	119	slavio_timer_get_out(t);
97bf4851	120	trace_slavio_timer_irq(t->counthigh, t->count);
68fb89a2 BS	121	/* if limit is 0 (free-run), there will be no match */
	122	if (t->limit != 0) {
	123	t->reached = TIMER_REACHED;
	124	}
452efba6 BS	125	/* there is no interrupt if user timer or free-run */
452efba6 BS	126	if (!slavio_timer_is_user(tc) && t->limit != 0) {
7204ff9c BS	127	qemu_irq_raise(t->irq);
7204ff9c BS	128	}
e80cfcfc FB	129	}
e80cfcfc FB	130
c227f099	131	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
e80cfcfc	132	{
7204ff9c BS	133	TimerContext *tc = opaque;
7204ff9c BS	134	SLAVIO_TIMERState *s = tc->s;
8d05ea8a	135	uint32_t saddr, ret;
7204ff9c BS	136	unsigned int timer_index = tc->timer_index;
7204ff9c BS	137	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	138
e64d7d59	139	saddr = addr >> 2;
e80cfcfc	140	switch (saddr) {
d2c38b24	141	case TIMER_LIMIT:
f930d07e BS	142	// read limit (system counter mode) or read most signifying
f930d07e BS	143	// part of counter (user mode)
7204ff9c	144	if (slavio_timer_is_user(tc)) {
115646b6	145	// read user timer MSW
7204ff9c BS	146	slavio_timer_get_out(t);
7204ff9c BS	147	ret = t->counthigh \| t->reached;
115646b6 BS	148	} else {
115646b6 BS	149	// read limit
f930d07e	150	// clear irq
7204ff9c BS	151	qemu_irq_lower(t->irq);
	152	t->reached = 0;
	153	ret = t->limit & TIMER_LIMIT_MASK32;
f930d07e	154	}
8d05ea8a	155	break;
d2c38b24	156	case TIMER_COUNTER:
f930d07e BS	157	// read counter and reached bit (system mode) or read lsbits
f930d07e BS	158	// of counter (user mode)
7204ff9c BS	159	slavio_timer_get_out(t);
	160	if (slavio_timer_is_user(tc)) { // read user timer LSW
	161	ret = t->count & TIMER_MAX_COUNT64;
	162	} else { // read limit
	163	ret = (t->count & TIMER_MAX_COUNT32) \|
	164	t->reached;
	165	}
8d05ea8a	166	break;
d2c38b24	167	case TIMER_STATUS:
115646b6	168	// only available in processor counter/timer
f930d07e	169	// read start/stop status
7204ff9c BS	170	if (timer_index > 0) {
	171	ret = t->running;
	172	} else {
	173	ret = 0;
	174	}
8d05ea8a	175	break;
d2c38b24	176	case TIMER_MODE:
115646b6	177	// only available in system counter
f930d07e	178	// read user/system mode
7204ff9c	179	ret = s->cputimer_mode;
8d05ea8a	180	break;
e80cfcfc	181	default:
97bf4851	182	trace_slavio_timer_mem_readl_invalid(addr);
8d05ea8a BS	183	ret = 0;
8d05ea8a BS	184	break;
e80cfcfc	185	}
97bf4851	186	trace_slavio_timer_mem_readl(addr, ret);
8d05ea8a	187	return ret;
e80cfcfc FB	188	}
e80cfcfc FB	189
c227f099	190	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
d2c38b24	191	uint32_t val)
e80cfcfc	192	{
7204ff9c BS	193	TimerContext *tc = opaque;
7204ff9c BS	194	SLAVIO_TIMERState *s = tc->s;
e80cfcfc	195	uint32_t saddr;
7204ff9c BS	196	unsigned int timer_index = tc->timer_index;
7204ff9c BS	197	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	198
97bf4851	199	trace_slavio_timer_mem_writel(addr, val);
e64d7d59	200	saddr = addr >> 2;
e80cfcfc	201	switch (saddr) {
d2c38b24	202	case TIMER_LIMIT:
7204ff9c	203	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	204	uint64_t count;
e1cb9502 BS	205
115646b6	206	// set user counter MSW, reset counter
7204ff9c BS	207	t->limit = TIMER_MAX_COUNT64;
	208	t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
	209	t->reached = 0;
	210	count = ((uint64_t)t->counthigh << 32) \| t->count;
97bf4851	211	trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b	212	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
115646b6 BS	213	} else {
115646b6 BS	214	// set limit, reset counter
7204ff9c BS	215	qemu_irq_lower(t->irq);
	216	t->limit = val & TIMER_MAX_COUNT32;
	217	if (t->timer) {
	218	if (t->limit == 0) { /* free-run */
	219	ptimer_set_limit(t->timer,
77f193da	220	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
7204ff9c BS	221	} else {
	222	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
	223	}
85e3023e	224	}
81732d19	225	}
115646b6	226	break;
d2c38b24	227	case TIMER_COUNTER:
7204ff9c	228	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	229	uint64_t count;
e1cb9502 BS	230
115646b6	231	// set user counter LSW, reset counter
7204ff9c BS	232	t->limit = TIMER_MAX_COUNT64;
	233	t->count = val & TIMER_MAX_COUNT64;
	234	t->reached = 0;
	235	count = ((uint64_t)t->counthigh) << 32 \| t->count;
97bf4851	236	trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b	237	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
97bf4851 BS	238	} else {
	239	trace_slavio_timer_mem_writel_counter_invalid();
	240	}
115646b6	241	break;
d2c38b24	242	case TIMER_COUNTER_NORST:
f930d07e	243	// set limit without resetting counter
7204ff9c	244	t->limit = val & TIMER_MAX_COUNT32;
9ebec28b BS	245	if (t->limit == 0) { /* free-run */
	246	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
	247	} else {
	248	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
85e3023e	249	}
f930d07e	250	break;
d2c38b24	251	case TIMER_STATUS:
7204ff9c	252	if (slavio_timer_is_user(tc)) {
115646b6	253	// start/stop user counter
7204ff9c	254	if ((val & 1) && !t->running) {
97bf4851	255	trace_slavio_timer_mem_writel_status_start(timer_index);
9ebec28b	256	ptimer_run(t->timer, 0);
7204ff9c BS	257	t->running = 1;
7204ff9c BS	258	} else if (!(val & 1) && t->running) {
97bf4851	259	trace_slavio_timer_mem_writel_status_stop(timer_index);
9ebec28b	260	ptimer_stop(t->timer);
7204ff9c	261	t->running = 0;
f930d07e BS	262	}
	263	}
	264	break;
d2c38b24	265	case TIMER_MODE:
7204ff9c	266	if (timer_index == 0) {
81732d19 BS	267	unsigned int i;
81732d19 BS	268
7204ff9c	269	for (i = 0; i < s->num_cpus; i++) {
67e42751	270	unsigned int processor = 1 << i;
7204ff9c	271	CPUTimerState *curr_timer = &s->cputimer[i + 1];
67e42751 BS	272
67e42751 BS	273	// check for a change in timer mode for this processor
7204ff9c	274	if ((val & processor) != (s->cputimer_mode & processor)) {
67e42751	275	if (val & processor) { // counter -> user timer
7204ff9c	276	qemu_irq_lower(curr_timer->irq);
67e42751	277	// counters are always running
7204ff9c BS	278	ptimer_stop(curr_timer->timer);
7204ff9c BS	279	curr_timer->running = 0;
67e42751	280	// user timer limit is always the same
7204ff9c BS	281	curr_timer->limit = TIMER_MAX_COUNT64;
	282	ptimer_set_limit(curr_timer->timer,
	283	LIMIT_TO_PERIODS(curr_timer->limit),
77f193da	284	1);
67e42751 BS	285	// set this processors user timer bit in config
67e42751 BS	286	// register
7204ff9c	287	s->cputimer_mode \|= processor;
97bf4851	288	trace_slavio_timer_mem_writel_mode_user(timer_index);
67e42751 BS	289	} else { // user timer -> counter
67e42751 BS	290	// stop the user timer if it is running
7204ff9c BS	291	if (curr_timer->running) {
	292	ptimer_stop(curr_timer->timer);
	293	}
67e42751	294	// start the counter
7204ff9c BS	295	ptimer_run(curr_timer->timer, 0);
7204ff9c BS	296	curr_timer->running = 1;
67e42751 BS	297	// clear this processors user timer bit in config
67e42751 BS	298	// register
7204ff9c	299	s->cputimer_mode &= ~processor;
97bf4851	300	trace_slavio_timer_mem_writel_mode_counter(timer_index);
67e42751	301	}
115646b6	302	}
81732d19	303	}
7204ff9c	304	} else {
97bf4851	305	trace_slavio_timer_mem_writel_mode_invalid();
7204ff9c	306	}
f930d07e	307	break;
e80cfcfc	308	default:
97bf4851	309	trace_slavio_timer_mem_writel_invalid(addr);
f930d07e	310	break;
e80cfcfc FB	311	}
	312	}
	313
d60efc6b	314	static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
7c560456 BS	315	NULL,
7c560456 BS	316	NULL,
e80cfcfc FB	317	slavio_timer_mem_readl,
	318	};
	319
d60efc6b	320	static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
7c560456 BS	321	NULL,
7c560456 BS	322	NULL,
e80cfcfc FB	323	slavio_timer_mem_writel,
	324	};
	325
f4b19cd0 BS	326	static const VMStateDescription vmstate_timer = {
	327	.name ="timer",
	328	.version_id = 3,
	329	.minimum_version_id = 3,
	330	.minimum_version_id_old = 3,
	331	.fields = (VMStateField []) {
	332	VMSTATE_UINT64(limit, CPUTimerState),
	333	VMSTATE_UINT32(count, CPUTimerState),
	334	VMSTATE_UINT32(counthigh, CPUTimerState),
	335	VMSTATE_UINT32(reached, CPUTimerState),
	336	VMSTATE_UINT32(running, CPUTimerState),
	337	VMSTATE_PTIMER(timer, CPUTimerState),
	338	VMSTATE_END_OF_LIST()
7204ff9c	339	}
f4b19cd0	340	};
e80cfcfc	341
f4b19cd0 BS	342	static const VMStateDescription vmstate_slavio_timer = {
	343	.name ="slavio_timer",
	344	.version_id = 3,
	345	.minimum_version_id = 3,
	346	.minimum_version_id_old = 3,
	347	.fields = (VMStateField []) {
	348	VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
	349	vmstate_timer, CPUTimerState),
	350	VMSTATE_END_OF_LIST()
7204ff9c	351	}
f4b19cd0	352	};
e80cfcfc	353
0e0bfeea	354	static void slavio_timer_reset(DeviceState *d)
e80cfcfc	355	{
0e0bfeea	356	SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
7204ff9c BS	357	unsigned int i;
	358	CPUTimerState *curr_timer;
	359
	360	for (i = 0; i <= MAX_CPUS; i++) {
	361	curr_timer = &s->cputimer[i];
	362	curr_timer->limit = 0;
	363	curr_timer->count = 0;
	364	curr_timer->reached = 0;
5933e8a9	365	if (i <= s->num_cpus) {
7204ff9c BS	366	ptimer_set_limit(curr_timer->timer,
	367	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
	368	ptimer_run(curr_timer->timer, 0);
5933e8a9	369	curr_timer->running = 1;
7204ff9c	370	}
85e3023e	371	}
7204ff9c	372	s->cputimer_mode = 0;
e80cfcfc FB	373	}
e80cfcfc FB	374
81a322d4	375	static int slavio_timer_init1(SysBusDevice *dev)
c70c59ee BS	376	{
	377	int io;
	378	SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
8d05ea8a	379	QEMUBH *bh;
7204ff9c BS	380	unsigned int i;
7204ff9c BS	381	TimerContext *tc;
e80cfcfc	382
7204ff9c	383	for (i = 0; i <= MAX_CPUS; i++) {
7267c094	384	tc = g_malloc0(sizeof(TimerContext));
7204ff9c BS	385	tc->s = s;
7204ff9c BS	386	tc->timer_index = i;
c70c59ee	387
7204ff9c BS	388	bh = qemu_bh_new(slavio_timer_irq, tc);
	389	s->cputimer[i].timer = ptimer_init(bh);
	390	ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
e80cfcfc	391
7204ff9c	392	io = cpu_register_io_memory(slavio_timer_mem_read,
2507c12a AG	393	slavio_timer_mem_write, tc,
2507c12a AG	394	DEVICE_NATIVE_ENDIAN);
7204ff9c BS	395	if (i == 0) {
	396	sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
	397	} else {
	398	sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
	399	}
	400
	401	sysbus_init_irq(dev, &s->cputimer[i].irq);
c70c59ee BS	402	}
c70c59ee BS	403
81a322d4	404	return 0;
81732d19 BS	405	}
81732d19 BS	406
c70c59ee BS	407	static SysBusDeviceInfo slavio_timer_info = {
	408	.init = slavio_timer_init1,
	409	.qdev.name = "slavio_timer",
	410	.qdev.size = sizeof(SLAVIO_TIMERState),
0e0bfeea BS	411	.qdev.vmsd = &vmstate_slavio_timer,
0e0bfeea BS	412	.qdev.reset = slavio_timer_reset,
ee6847d1	413	.qdev.props = (Property[]) {
18c637dc GH	414	DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
18c637dc GH	415	DEFINE_PROP_END_OF_LIST(),
c70c59ee BS	416	}
	417	};
	418
	419	static void slavio_timer_register_devices(void)
	420	{
	421	sysbus_register_withprop(&slavio_timer_info);
	422	}
	423
	424	device_init(slavio_timer_register_devices)