[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "qemu-timer.h"
#include "sysbus.h"

//#define DEBUG_TIMER

#ifdef DEBUG_TIMER
#define DPRINTF(fmt, ...)                                       \
    do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

#define MAX_CPUS 16

typedef struct CPUTimerState {
    qemu_irq irq;
    ptimer_state *timer;
    uint32_t count, counthigh, reached;
    uint64_t limit;
    // processor only
    uint32_t running;
} CPUTimerState;

typedef struct SLAVIO_TIMERState {
    SysBusDevice busdev;
    uint32_t num_cpus;
    CPUTimerState cputimer[MAX_CPUS + 1];
    uint32_t cputimer_mode;
} SLAVIO_TIMERState;

typedef struct TimerContext {
    SLAVIO_TIMERState *s;
    unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
} TimerContext;

#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10

#define TIMER_LIMIT         0
#define TIMER_COUNTER       1
#define TIMER_COUNTER_NORST 2
#define TIMER_STATUS        3
#define TIMER_MODE          4

#define TIMER_COUNT_MASK32 0xfffffe00
#define TIMER_LIMIT_MASK32 0x7fffffff
#define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
#define TIMER_MAX_COUNT32  0x7ffffe00ULL
#define TIMER_REACHED      0x80000000
#define TIMER_PERIOD       500ULL // 500ns
#define LIMIT_TO_PERIODS(l) ((l) >> 9)
#define PERIODS_TO_LIMIT(l) ((l) << 9)

static int slavio_timer_is_user(TimerContext *tc)
{
    SLAVIO_TIMERState *s = tc->s;
    unsigned int timer_index = tc->timer_index;

    return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
}

// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(CPUTimerState *t)
{
    uint64_t count, limit;

    if (t->limit == 0) { /* free-run system or processor counter */
        limit = TIMER_MAX_COUNT32;
    } else {
        limit = t->limit;
    }
    count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));

    DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
            t->count);
    t->count = count & TIMER_COUNT_MASK32;
    t->counthigh = count >> 32;
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    CPUTimerState *t = &s->cputimer[tc->timer_index];

    slavio_timer_get_out(t);
    DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
    t->reached = TIMER_REACHED;
    if (!slavio_timer_is_user(tc)) {
        qemu_irq_raise(t->irq);
    }
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr, ret;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        // read limit (system counter mode) or read most signifying
        // part of counter (user mode)
        if (slavio_timer_is_user(tc)) {
            // read user timer MSW
            slavio_timer_get_out(t);
            ret = t->counthigh | t->reached;
        } else {
            // read limit
            // clear irq
            qemu_irq_lower(t->irq);
            t->reached = 0;
            ret = t->limit & TIMER_LIMIT_MASK32;
        }
        break;
    case TIMER_COUNTER:
        // read counter and reached bit (system mode) or read lsbits
        // of counter (user mode)
        slavio_timer_get_out(t);
        if (slavio_timer_is_user(tc)) { // read user timer LSW
            ret = t->count & TIMER_MAX_COUNT64;
        } else { // read limit
            ret = (t->count & TIMER_MAX_COUNT32) |
                t->reached;
        }
        break;
    case TIMER_STATUS:
        // only available in processor counter/timer
        // read start/stop status
        if (timer_index > 0) {
            ret = t->running;
        } else {
            ret = 0;
        }
        break;
    case TIMER_MODE:
        // only available in system counter
        // read user/system mode
        ret = s->cputimer_mode;
        break;
    default:
        DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
        ret = 0;
        break;
    }
    DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);

    return ret;
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter MSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
            t->reached = 0;
            count = ((uint64_t)t->counthigh << 32) | t->count;
            DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
                    timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else {
            // set limit, reset counter
            qemu_irq_lower(t->irq);
            t->limit = val & TIMER_MAX_COUNT32;
            if (t->timer) {
                if (t->limit == 0) { /* free-run */
                    ptimer_set_limit(t->timer,
                                     LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
                } else {
                    ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
                }
            }
        }
        break;
    case TIMER_COUNTER:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter LSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->count = val & TIMER_MAX_COUNT64;
            t->reached = 0;
            count = ((uint64_t)t->counthigh) << 32 | t->count;
            DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
                    timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else
            DPRINTF("not user timer\n");
        break;
    case TIMER_COUNTER_NORST:
        // set limit without resetting counter
        t->limit = val & TIMER_MAX_COUNT32;
        if (t->limit == 0) { /* free-run */
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
        } else {
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
        }
        break;
    case TIMER_STATUS:
        if (slavio_timer_is_user(tc)) {
            // start/stop user counter
            if ((val & 1) && !t->running) {
                DPRINTF("processor %d user timer started\n",
                        timer_index);
                ptimer_run(t->timer, 0);
                t->running = 1;
            } else if (!(val & 1) && t->running) {
                DPRINTF("processor %d user timer stopped\n",
                        timer_index);
                ptimer_stop(t->timer);
                t->running = 0;
            }
        }
        break;
    case TIMER_MODE:
        if (timer_index == 0) {
            unsigned int i;

            for (i = 0; i < s->num_cpus; i++) {
                unsigned int processor = 1 << i;
                CPUTimerState *curr_timer = &s->cputimer[i + 1];

                // check for a change in timer mode for this processor
                if ((val & processor) != (s->cputimer_mode & processor)) {
                    if (val & processor) { // counter -> user timer
                        qemu_irq_lower(curr_timer->irq);
                        // counters are always running
                        ptimer_stop(curr_timer->timer);
                        curr_timer->running = 0;
                        // user timer limit is always the same
                        curr_timer->limit = TIMER_MAX_COUNT64;
                        ptimer_set_limit(curr_timer->timer,
                                         LIMIT_TO_PERIODS(curr_timer->limit),
                                         1);
                        // set this processors user timer bit in config
                        // register
                        s->cputimer_mode |= processor;
                        DPRINTF("processor %d changed from counter to user "
                                "timer\n", timer_index);
                    } else { // user timer -> counter
                        // stop the user timer if it is running
                        if (curr_timer->running) {
                            ptimer_stop(curr_timer->timer);
                        }
                        // start the counter
                        ptimer_run(curr_timer->timer, 0);
                        curr_timer->running = 1;
                        // clear this processors user timer bit in config
                        // register
                        s->cputimer_mode &= ~processor;
                        DPRINTF("processor %d changed from user timer to "
                                "counter\n", timer_index);
                    }
                }
            }
        } else {
            DPRINTF("not system timer\n");
        }
        break;
    default:
        DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
        break;
    }
}

static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
    NULL,
    NULL,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
    NULL,
    NULL,
    slavio_timer_mem_writel,
};

static void slavio_timer_save(QEMUFile *f, void *opaque)
{
    SLAVIO_TIMERState *s = opaque;
    unsigned int i;
    CPUTimerState *curr_timer;

    for (i = 0; i <= MAX_CPUS; i++) {
        curr_timer = &s->cputimer[i];
        qemu_put_be64s(f, &curr_timer->limit);
        qemu_put_be32s(f, &curr_timer->count);
        qemu_put_be32s(f, &curr_timer->counthigh);
        qemu_put_be32s(f, &curr_timer->reached);
        qemu_put_be32s(f, &curr_timer->running);
        qemu_put_ptimer(f, curr_timer->timer);
    }
}

static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_TIMERState *s = opaque;
    unsigned int i;
    CPUTimerState *curr_timer;

    if (version_id != 3)
        return -EINVAL;

    for (i = 0; i <= MAX_CPUS; i++) {
        curr_timer = &s->cputimer[i];
        qemu_get_be64s(f, &curr_timer->limit);
        qemu_get_be32s(f, &curr_timer->count);
        qemu_get_be32s(f, &curr_timer->counthigh);
        qemu_get_be32s(f, &curr_timer->reached);
        qemu_get_be32s(f, &curr_timer->running);
        qemu_get_ptimer(f, curr_timer->timer);
    }

    return 0;
}

static void slavio_timer_reset(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;
    unsigned int i;
    CPUTimerState *curr_timer;

    for (i = 0; i <= MAX_CPUS; i++) {
        curr_timer = &s->cputimer[i];
        curr_timer->limit = 0;
        curr_timer->count = 0;
        curr_timer->reached = 0;
        if (i < s->num_cpus) {
            ptimer_set_limit(curr_timer->timer,
                             LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
            ptimer_run(curr_timer->timer, 0);
        }
        curr_timer->running = 1;
    }
    s->cputimer_mode = 0;
}

static int slavio_timer_init1(SysBusDevice *dev)
{
    int io;
    SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
    QEMUBH *bh;
    unsigned int i;
    TimerContext *tc;

    for (i = 0; i <= MAX_CPUS; i++) {
        tc = qemu_mallocz(sizeof(TimerContext));
        tc->s = s;
        tc->timer_index = i;

        bh = qemu_bh_new(slavio_timer_irq, tc);
        s->cputimer[i].timer = ptimer_init(bh);
        ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);

        io = cpu_register_io_memory(slavio_timer_mem_read,
                                    slavio_timer_mem_write, tc);
        if (i == 0) {
            sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
        } else {
            sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
        }

        sysbus_init_irq(dev, &s->cputimer[i].irq);
    }

    register_savevm("slavio_timer", -1, 3, slavio_timer_save,
                    slavio_timer_load, s);
    qemu_register_reset(slavio_timer_reset, s);
    slavio_timer_reset(s);
    return 0;
}

static SysBusDeviceInfo slavio_timer_info = {
    .init = slavio_timer_init1,
    .qdev.name  = "slavio_timer",
    .qdev.size  = sizeof(SLAVIO_TIMERState),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void slavio_timer_register_devices(void)
{
    sysbus_register_withprop(&slavio_timer_info);
}

device_init(slavio_timer_register_devices)
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
c70c59ee	24
87ecb68b PB	25	#include "sun4m.h"
87ecb68b PB	26	#include "qemu-timer.h"
c70c59ee	27	#include "sysbus.h"
e80cfcfc FB	28
	29	//#define DEBUG_TIMER
	30
66321a11	31	#ifdef DEBUG_TIMER
001faf32 BS	32	#define DPRINTF(fmt, ...) \
001faf32 BS	33	do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
66321a11	34	#else
001faf32	35	#define DPRINTF(fmt, ...) do {} while (0)
66321a11 FB	36	#endif
66321a11 FB	37
e80cfcfc FB	38	/*
	39	* Registers of hardware timer in sun4m.
	40	*
	41	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	42	* produced as NCR89C105. See
	43	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24	44	*
e80cfcfc FB	45	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	46	* are zero. Bit 31 is 1 when count has been reached.
	47	*
ba3c64fb FB	48	* Per-CPU timers interrupt local CPU, system timer uses normal
	49	* interrupt routing.
	50	*
e80cfcfc FB	51	*/
e80cfcfc FB	52
81732d19 BS	53	#define MAX_CPUS 16
81732d19 BS	54
7204ff9c	55	typedef struct CPUTimerState {
d7edfd27	56	qemu_irq irq;
8d05ea8a BS	57	ptimer_state *timer;
	58	uint32_t count, counthigh, reached;
	59	uint64_t limit;
115646b6	60	// processor only
22548760	61	uint32_t running;
7204ff9c BS	62	} CPUTimerState;
	63
	64	typedef struct SLAVIO_TIMERState {
	65	SysBusDevice busdev;
	66	uint32_t num_cpus;
	67	CPUTimerState cputimer[MAX_CPUS + 1];
	68	uint32_t cputimer_mode;
e80cfcfc FB	69	} SLAVIO_TIMERState;
e80cfcfc FB	70
7204ff9c BS	71	typedef struct TimerContext {
	72	SLAVIO_TIMERState *s;
	73	unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
	74	} TimerContext;
	75
115646b6	76	#define SYS_TIMER_SIZE 0x14
81732d19	77	#define CPU_TIMER_SIZE 0x10
e80cfcfc	78
d2c38b24 BS	79	#define TIMER_LIMIT 0
	80	#define TIMER_COUNTER 1
	81	#define TIMER_COUNTER_NORST 2
	82	#define TIMER_STATUS 3
	83	#define TIMER_MODE 4
	84
	85	#define TIMER_COUNT_MASK32 0xfffffe00
	86	#define TIMER_LIMIT_MASK32 0x7fffffff
	87	#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
	88	#define TIMER_MAX_COUNT32 0x7ffffe00ULL
	89	#define TIMER_REACHED 0x80000000
	90	#define TIMER_PERIOD 500ULL // 500ns
	91	#define LIMIT_TO_PERIODS(l) ((l) >> 9)
	92	#define PERIODS_TO_LIMIT(l) ((l) << 9)
	93
7204ff9c	94	static int slavio_timer_is_user(TimerContext *tc)
115646b6	95	{
7204ff9c BS	96	SLAVIO_TIMERState *s = tc->s;
	97	unsigned int timer_index = tc->timer_index;
	98
	99	return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
115646b6 BS	100	}
115646b6 BS	101
e80cfcfc	102	// Update count, set irq, update expire_time
8d05ea8a	103	// Convert from ptimer countdown units
7204ff9c	104	static void slavio_timer_get_out(CPUTimerState *t)
e80cfcfc	105	{
bd7e2875	106	uint64_t count, limit;
e80cfcfc	107
7204ff9c	108	if (t->limit == 0) { /* free-run system or processor counter */
bd7e2875	109	limit = TIMER_MAX_COUNT32;
7204ff9c BS	110	} else {
	111	limit = t->limit;
	112	}
9ebec28b BS	113	count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
9ebec28b BS	114
7204ff9c BS	115	DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
	116	t->count);
	117	t->count = count & TIMER_COUNT_MASK32;
	118	t->counthigh = count >> 32;
e80cfcfc FB	119	}
	120
	121	// timer callback
	122	static void slavio_timer_irq(void *opaque)
	123	{
7204ff9c BS	124	TimerContext *tc = opaque;
	125	SLAVIO_TIMERState *s = tc->s;
	126	CPUTimerState *t = &s->cputimer[tc->timer_index];
	127
	128	slavio_timer_get_out(t);
	129	DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
	130	t->reached = TIMER_REACHED;
	131	if (!slavio_timer_is_user(tc)) {
	132	qemu_irq_raise(t->irq);
	133	}
e80cfcfc FB	134	}
	135
	136	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
	137	{
7204ff9c BS	138	TimerContext *tc = opaque;
7204ff9c BS	139	SLAVIO_TIMERState *s = tc->s;
8d05ea8a	140	uint32_t saddr, ret;
7204ff9c BS	141	unsigned int timer_index = tc->timer_index;
7204ff9c BS	142	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	143
e64d7d59	144	saddr = addr >> 2;
e80cfcfc	145	switch (saddr) {
d2c38b24	146	case TIMER_LIMIT:
f930d07e BS	147	// read limit (system counter mode) or read most signifying
f930d07e BS	148	// part of counter (user mode)
7204ff9c	149	if (slavio_timer_is_user(tc)) {
115646b6	150	// read user timer MSW
7204ff9c BS	151	slavio_timer_get_out(t);
7204ff9c BS	152	ret = t->counthigh \| t->reached;
115646b6 BS	153	} else {
115646b6 BS	154	// read limit
f930d07e	155	// clear irq
7204ff9c BS	156	qemu_irq_lower(t->irq);
	157	t->reached = 0;
	158	ret = t->limit & TIMER_LIMIT_MASK32;
f930d07e	159	}
8d05ea8a	160	break;
d2c38b24	161	case TIMER_COUNTER:
f930d07e BS	162	// read counter and reached bit (system mode) or read lsbits
f930d07e BS	163	// of counter (user mode)
7204ff9c BS	164	slavio_timer_get_out(t);
	165	if (slavio_timer_is_user(tc)) { // read user timer LSW
	166	ret = t->count & TIMER_MAX_COUNT64;
	167	} else { // read limit
	168	ret = (t->count & TIMER_MAX_COUNT32) \|
	169	t->reached;
	170	}
8d05ea8a	171	break;
d2c38b24	172	case TIMER_STATUS:
115646b6	173	// only available in processor counter/timer
f930d07e	174	// read start/stop status
7204ff9c BS	175	if (timer_index > 0) {
	176	ret = t->running;
	177	} else {
	178	ret = 0;
	179	}
8d05ea8a	180	break;
d2c38b24	181	case TIMER_MODE:
115646b6	182	// only available in system counter
f930d07e	183	// read user/system mode
7204ff9c	184	ret = s->cputimer_mode;
8d05ea8a	185	break;
e80cfcfc	186	default:
115646b6	187	DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
8d05ea8a BS	188	ret = 0;
8d05ea8a BS	189	break;
e80cfcfc	190	}
8d05ea8a BS	191	DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
	192
	193	return ret;
e80cfcfc FB	194	}
e80cfcfc FB	195
d2c38b24 BS	196	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
d2c38b24 BS	197	uint32_t val)
e80cfcfc	198	{
7204ff9c BS	199	TimerContext *tc = opaque;
7204ff9c BS	200	SLAVIO_TIMERState *s = tc->s;
e80cfcfc	201	uint32_t saddr;
7204ff9c BS	202	unsigned int timer_index = tc->timer_index;
7204ff9c BS	203	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	204
8d05ea8a	205	DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
e64d7d59	206	saddr = addr >> 2;
e80cfcfc	207	switch (saddr) {
d2c38b24	208	case TIMER_LIMIT:
7204ff9c	209	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	210	uint64_t count;
e1cb9502 BS	211
115646b6	212	// set user counter MSW, reset counter
7204ff9c BS	213	t->limit = TIMER_MAX_COUNT64;
	214	t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
	215	t->reached = 0;
	216	count = ((uint64_t)t->counthigh << 32) \| t->count;
0bf9e31a	217	DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
7204ff9c	218	timer_index, count);
9ebec28b	219	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
115646b6 BS	220	} else {
115646b6 BS	221	// set limit, reset counter
7204ff9c BS	222	qemu_irq_lower(t->irq);
	223	t->limit = val & TIMER_MAX_COUNT32;
	224	if (t->timer) {
	225	if (t->limit == 0) { /* free-run */
	226	ptimer_set_limit(t->timer,
77f193da	227	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
7204ff9c BS	228	} else {
	229	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
	230	}
85e3023e	231	}
81732d19	232	}
115646b6	233	break;
d2c38b24	234	case TIMER_COUNTER:
7204ff9c	235	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	236	uint64_t count;
e1cb9502 BS	237
115646b6	238	// set user counter LSW, reset counter
7204ff9c BS	239	t->limit = TIMER_MAX_COUNT64;
	240	t->count = val & TIMER_MAX_COUNT64;
	241	t->reached = 0;
	242	count = ((uint64_t)t->counthigh) << 32 \| t->count;
0bf9e31a	243	DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
7204ff9c	244	timer_index, count);
9ebec28b	245	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
115646b6 BS	246	} else
	247	DPRINTF("not user timer\n");
	248	break;
d2c38b24	249	case TIMER_COUNTER_NORST:
f930d07e	250	// set limit without resetting counter
7204ff9c	251	t->limit = val & TIMER_MAX_COUNT32;
9ebec28b BS	252	if (t->limit == 0) { /* free-run */
	253	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
	254	} else {
	255	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
85e3023e	256	}
f930d07e	257	break;
d2c38b24	258	case TIMER_STATUS:
7204ff9c	259	if (slavio_timer_is_user(tc)) {
115646b6	260	// start/stop user counter
7204ff9c BS	261	if ((val & 1) && !t->running) {
	262	DPRINTF("processor %d user timer started\n",
	263	timer_index);
9ebec28b	264	ptimer_run(t->timer, 0);
7204ff9c BS	265	t->running = 1;
	266	} else if (!(val & 1) && t->running) {
	267	DPRINTF("processor %d user timer stopped\n",
	268	timer_index);
9ebec28b	269	ptimer_stop(t->timer);
7204ff9c	270	t->running = 0;
f930d07e BS	271	}
	272	}
	273	break;
d2c38b24	274	case TIMER_MODE:
7204ff9c	275	if (timer_index == 0) {
81732d19 BS	276	unsigned int i;
81732d19 BS	277
7204ff9c	278	for (i = 0; i < s->num_cpus; i++) {
67e42751	279	unsigned int processor = 1 << i;
7204ff9c	280	CPUTimerState *curr_timer = &s->cputimer[i + 1];
67e42751 BS	281
67e42751 BS	282	// check for a change in timer mode for this processor
7204ff9c	283	if ((val & processor) != (s->cputimer_mode & processor)) {
67e42751	284	if (val & processor) { // counter -> user timer
7204ff9c	285	qemu_irq_lower(curr_timer->irq);
67e42751	286	// counters are always running
7204ff9c BS	287	ptimer_stop(curr_timer->timer);
7204ff9c BS	288	curr_timer->running = 0;
67e42751	289	// user timer limit is always the same
7204ff9c BS	290	curr_timer->limit = TIMER_MAX_COUNT64;
	291	ptimer_set_limit(curr_timer->timer,
	292	LIMIT_TO_PERIODS(curr_timer->limit),
77f193da	293	1);
67e42751 BS	294	// set this processors user timer bit in config
67e42751 BS	295	// register
7204ff9c	296	s->cputimer_mode \|= processor;
67e42751	297	DPRINTF("processor %d changed from counter to user "
7204ff9c	298	"timer\n", timer_index);
67e42751 BS	299	} else { // user timer -> counter
67e42751 BS	300	// stop the user timer if it is running
7204ff9c BS	301	if (curr_timer->running) {
	302	ptimer_stop(curr_timer->timer);
	303	}
67e42751	304	// start the counter
7204ff9c BS	305	ptimer_run(curr_timer->timer, 0);
7204ff9c BS	306	curr_timer->running = 1;
67e42751 BS	307	// clear this processors user timer bit in config
67e42751 BS	308	// register
7204ff9c	309	s->cputimer_mode &= ~processor;
67e42751	310	DPRINTF("processor %d changed from user timer to "
7204ff9c	311	"counter\n", timer_index);
67e42751	312	}
115646b6	313	}
81732d19	314	}
7204ff9c	315	} else {
115646b6	316	DPRINTF("not system timer\n");
7204ff9c	317	}
f930d07e	318	break;
e80cfcfc	319	default:
115646b6	320	DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
f930d07e	321	break;
e80cfcfc FB	322	}
	323	}
	324
d60efc6b	325	static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
7c560456 BS	326	NULL,
7c560456 BS	327	NULL,
e80cfcfc FB	328	slavio_timer_mem_readl,
	329	};
	330
d60efc6b	331	static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
7c560456 BS	332	NULL,
7c560456 BS	333	NULL,
e80cfcfc FB	334	slavio_timer_mem_writel,
	335	};
	336
	337	static void slavio_timer_save(QEMUFile f, void opaque)
	338	{
	339	SLAVIO_TIMERState *s = opaque;
7204ff9c BS	340	unsigned int i;
	341	CPUTimerState *curr_timer;
	342
	343	for (i = 0; i <= MAX_CPUS; i++) {
	344	curr_timer = &s->cputimer[i];
	345	qemu_put_be64s(f, &curr_timer->limit);
	346	qemu_put_be32s(f, &curr_timer->count);
	347	qemu_put_be32s(f, &curr_timer->counthigh);
	348	qemu_put_be32s(f, &curr_timer->reached);
	349	qemu_put_be32s(f, &curr_timer->running);
9ebec28b	350	qemu_put_ptimer(f, curr_timer->timer);
7204ff9c	351	}
e80cfcfc FB	352	}
	353
	354	static int slavio_timer_load(QEMUFile f, void opaque, int version_id)
	355	{
	356	SLAVIO_TIMERState *s = opaque;
7204ff9c BS	357	unsigned int i;
7204ff9c BS	358	CPUTimerState *curr_timer;
3b46e624	359
85e3023e	360	if (version_id != 3)
e80cfcfc FB	361	return -EINVAL;
e80cfcfc FB	362
7204ff9c BS	363	for (i = 0; i <= MAX_CPUS; i++) {
	364	curr_timer = &s->cputimer[i];
	365	qemu_get_be64s(f, &curr_timer->limit);
	366	qemu_get_be32s(f, &curr_timer->count);
	367	qemu_get_be32s(f, &curr_timer->counthigh);
	368	qemu_get_be32s(f, &curr_timer->reached);
	369	qemu_get_be32s(f, &curr_timer->running);
9ebec28b	370	qemu_get_ptimer(f, curr_timer->timer);
7204ff9c	371	}
8d05ea8a	372
e80cfcfc FB	373	return 0;
	374	}
	375
	376	static void slavio_timer_reset(void *opaque)
	377	{
	378	SLAVIO_TIMERState *s = opaque;
7204ff9c BS	379	unsigned int i;
	380	CPUTimerState *curr_timer;
	381
	382	for (i = 0; i <= MAX_CPUS; i++) {
	383	curr_timer = &s->cputimer[i];
	384	curr_timer->limit = 0;
	385	curr_timer->count = 0;
	386	curr_timer->reached = 0;
	387	if (i < s->num_cpus) {
	388	ptimer_set_limit(curr_timer->timer,
	389	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
	390	ptimer_run(curr_timer->timer, 0);
	391	}
	392	curr_timer->running = 1;
85e3023e	393	}
7204ff9c	394	s->cputimer_mode = 0;
e80cfcfc FB	395	}
e80cfcfc FB	396
81a322d4	397	static int slavio_timer_init1(SysBusDevice *dev)
c70c59ee BS	398	{
	399	int io;
	400	SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
8d05ea8a	401	QEMUBH *bh;
7204ff9c BS	402	unsigned int i;
7204ff9c BS	403	TimerContext *tc;
e80cfcfc	404
7204ff9c BS	405	for (i = 0; i <= MAX_CPUS; i++) {
	406	tc = qemu_mallocz(sizeof(TimerContext));
	407	tc->s = s;
	408	tc->timer_index = i;
c70c59ee	409
7204ff9c BS	410	bh = qemu_bh_new(slavio_timer_irq, tc);
	411	s->cputimer[i].timer = ptimer_init(bh);
	412	ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
e80cfcfc	413
7204ff9c BS	414	io = cpu_register_io_memory(slavio_timer_mem_read,
	415	slavio_timer_mem_write, tc);
	416	if (i == 0) {
	417	sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
	418	} else {
	419	sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
	420	}
	421
	422	sysbus_init_irq(dev, &s->cputimer[i].irq);
c70c59ee BS	423	}
	424
	425	register_savevm("slavio_timer", -1, 3, slavio_timer_save,
d2c38b24	426	slavio_timer_load, s);
a08d4367	427	qemu_register_reset(slavio_timer_reset, s);
e80cfcfc	428	slavio_timer_reset(s);
81a322d4	429	return 0;
81732d19 BS	430	}
81732d19 BS	431
c70c59ee BS	432	static SysBusDeviceInfo slavio_timer_info = {
	433	.init = slavio_timer_init1,
	434	.qdev.name = "slavio_timer",
	435	.qdev.size = sizeof(SLAVIO_TIMERState),
ee6847d1	436	.qdev.props = (Property[]) {
18c637dc GH	437	DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
18c637dc GH	438	DEFINE_PROP_END_OF_LIST(),
c70c59ee BS	439	}
	440	};
	441
	442	static void slavio_timer_register_devices(void)
	443	{
	444	sysbus_register_withprop(&slavio_timer_info);
	445	}
	446
	447	device_init(slavio_timer_register_devices)