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ae0f5e9e AF |
1 | /* |
2 | * QEMU UniCore32 CPU | |
3 | * | |
d48813dd | 4 | * Copyright (c) 2010-2012 Guan Xuetao |
ae0f5e9e AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Contributions from 2012-04-01 on are considered under GPL version 2, | |
12 | * or (at your option) any later version. | |
13 | */ | |
14 | ||
5af98cc5 | 15 | #include "qemu/osdep.h" |
da34e65c | 16 | #include "qapi/error.h" |
3993c6bd | 17 | #include "cpu.h" |
ae0f5e9e | 18 | #include "qemu-common.h" |
88e28512 | 19 | #include "migration/vmstate.h" |
63c91552 | 20 | #include "exec/exec-all.h" |
24f91e81 | 21 | #include "fpu/softfloat.h" |
ae0f5e9e | 22 | |
b42eab27 AF |
23 | static void uc32_cpu_set_pc(CPUState *cs, vaddr value) |
24 | { | |
25 | UniCore32CPU *cpu = UNICORE32_CPU(cs); | |
26 | ||
27 | cpu->env.regs[31] = value; | |
28 | } | |
29 | ||
8c2e1b00 AF |
30 | static bool uc32_cpu_has_work(CPUState *cs) |
31 | { | |
32 | return cs->interrupt_request & | |
33 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
34 | } | |
35 | ||
8df9082d AF |
36 | static inline void set_feature(CPUUniCore32State *env, int feature) |
37 | { | |
38 | env->features |= feature; | |
39 | } | |
40 | ||
ae0f5e9e AF |
41 | /* CPU models */ |
42 | ||
d89e1218 AF |
43 | static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model) |
44 | { | |
45 | ObjectClass *oc; | |
eeb266de | 46 | char *typename; |
d89e1218 | 47 | |
6a826866 | 48 | typename = g_strdup_printf(UNICORE32_CPU_TYPE_NAME("%s"), cpu_model); |
eeb266de AF |
49 | oc = object_class_by_name(typename); |
50 | g_free(typename); | |
4933908a AF |
51 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) || |
52 | object_class_is_abstract(oc))) { | |
d89e1218 AF |
53 | oc = NULL; |
54 | } | |
55 | return oc; | |
56 | } | |
57 | ||
ae0f5e9e AF |
58 | static void unicore_ii_cpu_initfn(Object *obj) |
59 | { | |
60 | UniCore32CPU *cpu = UNICORE32_CPU(obj); | |
61 | CPUUniCore32State *env = &cpu->env; | |
62 | ||
d48813dd GX |
63 | env->cp0.c0_cpuid = 0x4d000863; |
64 | env->cp0.c0_cachetype = 0x0d152152; | |
65 | env->cp0.c1_sys = 0x2000; | |
66 | env->cp0.c2_base = 0x0; | |
67 | env->cp0.c3_faultstatus = 0x0; | |
68 | env->cp0.c4_faultaddr = 0x0; | |
69 | env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; | |
8df9082d AF |
70 | |
71 | set_feature(env, UC32_HWCAP_CMOV); | |
72 | set_feature(env, UC32_HWCAP_UCF64); | |
af39bc8c | 73 | set_snan_bit_is_one(1, &env->ucf64.fp_status); |
ae0f5e9e AF |
74 | } |
75 | ||
76 | static void uc32_any_cpu_initfn(Object *obj) | |
77 | { | |
78 | UniCore32CPU *cpu = UNICORE32_CPU(obj); | |
79 | CPUUniCore32State *env = &cpu->env; | |
80 | ||
81 | env->cp0.c0_cpuid = 0xffffffff; | |
d48813dd | 82 | env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; |
8df9082d AF |
83 | |
84 | set_feature(env, UC32_HWCAP_CMOV); | |
85 | set_feature(env, UC32_HWCAP_UCF64); | |
af39bc8c | 86 | set_snan_bit_is_one(1, &env->ucf64.fp_status); |
ae0f5e9e AF |
87 | } |
88 | ||
088383e3 AF |
89 | static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) |
90 | { | |
ce5b1bbf | 91 | CPUState *cs = CPU(dev); |
088383e3 | 92 | UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev); |
ce5b1bbf | 93 | Error *local_err = NULL; |
088383e3 | 94 | |
ce5b1bbf LV |
95 | cpu_exec_realizefn(cs, &local_err); |
96 | if (local_err != NULL) { | |
97 | error_propagate(errp, local_err); | |
98 | return; | |
99 | } | |
100 | ||
101 | qemu_init_vcpu(cs); | |
14a10fc3 | 102 | |
088383e3 AF |
103 | ucc->parent_realize(dev, errp); |
104 | } | |
105 | ||
ae0f5e9e AF |
106 | static void uc32_cpu_initfn(Object *obj) |
107 | { | |
c05efcb1 | 108 | CPUState *cs = CPU(obj); |
ae0f5e9e AF |
109 | UniCore32CPU *cpu = UNICORE32_CPU(obj); |
110 | CPUUniCore32State *env = &cpu->env; | |
111 | ||
c05efcb1 | 112 | cs->env_ptr = env; |
ae0f5e9e | 113 | |
d48813dd | 114 | #ifdef CONFIG_USER_ONLY |
ae0f5e9e AF |
115 | env->uncached_asr = ASR_MODE_USER; |
116 | env->regs[31] = 0; | |
d48813dd GX |
117 | #else |
118 | env->uncached_asr = ASR_MODE_PRIV; | |
119 | env->regs[31] = 0x03000000; | |
120 | #endif | |
ae0f5e9e | 121 | |
d10eb08f | 122 | tlb_flush(cs); |
ae0f5e9e AF |
123 | } |
124 | ||
88e28512 AF |
125 | static const VMStateDescription vmstate_uc32_cpu = { |
126 | .name = "cpu", | |
127 | .unmigratable = 1, | |
128 | }; | |
129 | ||
d89e1218 AF |
130 | static void uc32_cpu_class_init(ObjectClass *oc, void *data) |
131 | { | |
88e28512 | 132 | DeviceClass *dc = DEVICE_CLASS(oc); |
d89e1218 | 133 | CPUClass *cc = CPU_CLASS(oc); |
088383e3 AF |
134 | UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc); |
135 | ||
bf853881 PMD |
136 | device_class_set_parent_realize(dc, uc32_cpu_realizefn, |
137 | &ucc->parent_realize); | |
d89e1218 AF |
138 | |
139 | cc->class_by_name = uc32_cpu_class_by_name; | |
8c2e1b00 | 140 | cc->has_work = uc32_cpu_has_work; |
97a8ea5a | 141 | cc->do_interrupt = uc32_cpu_do_interrupt; |
d8bb9159 | 142 | cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; |
878096ee | 143 | cc->dump_state = uc32_cpu_dump_state; |
b42eab27 | 144 | cc->set_pc = uc32_cpu_set_pc; |
7510454e AF |
145 | #ifdef CONFIG_USER_ONLY |
146 | cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; | |
147 | #else | |
00b941e5 AF |
148 | cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; |
149 | #endif | |
55c3ceef | 150 | cc->tcg_initialize = uc32_translate_init; |
88e28512 | 151 | dc->vmsd = &vmstate_uc32_cpu; |
d89e1218 AF |
152 | } |
153 | ||
6a826866 IM |
154 | #define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \ |
155 | { \ | |
156 | .parent = TYPE_UNICORE32_CPU, \ | |
157 | .instance_init = initfn, \ | |
158 | .name = UNICORE32_CPU_TYPE_NAME(cpu_model), \ | |
159 | } | |
ae0f5e9e | 160 | |
6a826866 IM |
161 | static const TypeInfo uc32_cpu_type_infos[] = { |
162 | { | |
163 | .name = TYPE_UNICORE32_CPU, | |
164 | .parent = TYPE_CPU, | |
165 | .instance_size = sizeof(UniCore32CPU), | |
166 | .instance_init = uc32_cpu_initfn, | |
167 | .abstract = true, | |
168 | .class_size = sizeof(UniCore32CPUClass), | |
169 | .class_init = uc32_cpu_class_init, | |
170 | }, | |
171 | DEFINE_UNICORE32_CPU_TYPE("UniCore-II", unicore_ii_cpu_initfn), | |
172 | DEFINE_UNICORE32_CPU_TYPE("any", uc32_any_cpu_initfn), | |
ae0f5e9e AF |
173 | }; |
174 | ||
6a826866 | 175 | DEFINE_TYPES(uc32_cpu_type_infos) |