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tcg/s390: Fix setcond expansion
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
c896fe29 25#include "tcg.h"
944eea96 26#include "exec/helper-proto.h"
c017230d
RH		 27#include "exec/helper-gen.h"
28
951c6300 29/* Basic output routines. Not for general consumption. */
c896fe29 30
951c6300
RH		 31void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
32void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
33void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
34void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
36 TCGArg, TCGArg);
37void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
38 TCGArg, TCGArg, TCGArg);
212c328d 39
951c6300
RH		 40
41static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 42{
951c6300 43 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1));
a7812ae4
PB		 44}
45
951c6300 46static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 47{
951c6300 48 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1));
c896fe29
FB		 49}
50
951c6300 51static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 52{
951c6300 53 tcg_gen_op1(&tcg_ctx, opc, a1);
c896fe29
FB		 54}
55
951c6300 56static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 57{
951c6300 58 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
a7812ae4
PB		 59}
60
951c6300 61static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 62{
951c6300 63 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
a7812ae4
PB		 64}
65
951c6300 66static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 67{
951c6300 68 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2);
c896fe29
FB		 69}
70
951c6300 71static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 72{
951c6300 73 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2);
ac56dd48
PB		 74}
75
951c6300 76static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 77{
951c6300 78 tcg_gen_op2(&tcg_ctx, opc, a1, a2);
bcb0126f
PB		 79}
80
951c6300
RH		 81static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
82 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 83{
951c6300
RH		 84 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1),
85 GET_TCGV_I32(a2), GET_TCGV_I32(a3));
a7812ae4
PB		 86}
87
951c6300
RH		 88static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 90{
951c6300
RH		 91 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1),
92 GET_TCGV_I64(a2), GET_TCGV_I64(a3));
a7812ae4
PB		 93}
94
951c6300
RH		 95static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
96 TCGv_i32 a2, TCGArg a3)
ac56dd48 97{
951c6300 98 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
ac56dd48
PB		 99}
100
951c6300
RH		 101static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
102 TCGv_i64 a2, TCGArg a3)
ac56dd48 103{
951c6300 104 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
ac56dd48
PB		 105}
106
a9751609
RH		 107static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
108 TCGv_ptr base, TCGArg offset)
a7812ae4 109{
951c6300 110 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
a7812ae4
PB		 111}
112
a9751609
RH		 113static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
114 TCGv_ptr base, TCGArg offset)
a7812ae4 115{
951c6300 116 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
a7812ae4
PB		 117}
118
951c6300
RH		 119static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
120 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 121{
951c6300
RH		 122 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
123 GET_TCGV_I32(a3), GET_TCGV_I32(a4));
a7812ae4
PB		 124}
125
951c6300
RH		 126static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
127 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 128{
951c6300
RH		 129 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
130 GET_TCGV_I64(a3), GET_TCGV_I64(a4));
a7812ae4
PB		 131}
132
951c6300
RH		 133static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
134 TCGv_i32 a3, TCGArg a4)
a7812ae4 135{
951c6300
RH		 136 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
137 GET_TCGV_I32(a3), a4);
a7812ae4
PB		 138}
139
951c6300
RH		 140static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
141 TCGv_i64 a3, TCGArg a4)
ac56dd48 142{
951c6300
RH		 143 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
144 GET_TCGV_I64(a3), a4);
ac56dd48
PB		 145}
146
951c6300
RH		 147static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
148 TCGArg a3, TCGArg a4)
ac56dd48 149{
951c6300 150 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
c896fe29
FB		 151}
152
951c6300
RH		 153static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
154 TCGArg a3, TCGArg a4)
c896fe29 155{
951c6300 156 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
ac56dd48
PB		 157}
158
951c6300
RH		 159static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
160 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 161{
951c6300
RH		 162 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
163 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
a7812ae4
PB		 164}
165
951c6300
RH		 166static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
167 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 168{
951c6300
RH		 169 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
170 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
a7812ae4
PB		 171}
172
951c6300
RH		 173static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
174 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 175{
951c6300
RH		 176 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
177 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
ac56dd48
PB		 178}
179
951c6300
RH		 180static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
181 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 182{
951c6300
RH		 183 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
184 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
c896fe29
FB		 185}
186
951c6300
RH		 187static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
188 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 189{
951c6300
RH		 190 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
191 GET_TCGV_I32(a3), a4, a5);
b7767f0f
RH		 192}
193
951c6300
RH		 194static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
195 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 196{
951c6300
RH		 197 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
198 GET_TCGV_I64(a3), a4, a5);
b7767f0f
RH		 199}
200
951c6300
RH		 201static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
202 TCGv_i32 a3, TCGv_i32 a4,
203 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 204{
951c6300
RH		 205 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
206 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
207 GET_TCGV_I32(a6));
a7812ae4
PB		 208}
209
951c6300
RH		 210static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
211 TCGv_i64 a3, TCGv_i64 a4,
212 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 213{
951c6300
RH		 214 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
215 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
216 GET_TCGV_I64(a6));
ac56dd48
PB		 217}
218
951c6300
RH		 219static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
220 TCGv_i32 a3, TCGv_i32 a4,
221 TCGv_i32 a5, TCGArg a6)
be210acb 222{
951c6300
RH		 223 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
224 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
be210acb
RH		 225}
226
951c6300
RH		 227static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
228 TCGv_i64 a3, TCGv_i64 a4,
229 TCGv_i64 a5, TCGArg a6)
be210acb 230{
951c6300
RH		 231 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
232 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
be210acb
RH		 233}
234
951c6300
RH		 235static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
236 TCGv_i32 a3, TCGv_i32 a4,
237 TCGArg a5, TCGArg a6)
ac56dd48 238{
951c6300
RH		 239 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
240 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
a7812ae4
PB		 241}
242
951c6300
RH		 243static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
244 TCGv_i64 a3, TCGv_i64 a4,
245 TCGArg a5, TCGArg a6)
a7812ae4 246{
951c6300
RH		 247 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
248 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
c896fe29
FB		 249}
250
f713d6ad 251
951c6300
RH		 252/* Generic ops. */
253
42a268c2 254static inline void gen_set_label(TCGLabel *l)
c896fe29 255{
42a268c2 256 tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
c896fe29
FB		 257}
258
42a268c2 259static inline void tcg_gen_br(TCGLabel *l)
fb50d413 260{
42a268c2 261 tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
951c6300
RH		 262}
263
f65e19bc
PK		 264void tcg_gen_mb(TCGBar);
265
951c6300
RH		 266/* Helper calls. */
267
268/* 32 bit ops */
269
270void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
271void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
272void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
273void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
274void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
277void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
278void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
279void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
291void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
292void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
293void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
294 unsigned int ofs, unsigned int len);
42a268c2
RH		 295void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
296void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 297void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
298 TCGv_i32 arg1, TCGv_i32 arg2);
299void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
300 TCGv_i32 arg1, int32_t arg2);
301void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
302 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
303void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
304 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
305void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
306 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
307void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
308void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 309void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 310void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
311void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
312void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
313void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
314void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
315void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
316
317static inline void tcg_gen_discard_i32(TCGv_i32 arg)
318{
319 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 320}
321
a7812ae4 322static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 323{
951c6300 324 if (!TCGV_EQUAL_I32(ret, arg)) {
a7812ae4 325 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 326 }
c896fe29
FB		 327}
328
a7812ae4 329static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 330{
a7812ae4 331 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 332}
333
951c6300
RH		 334static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
335 tcg_target_long offset)
c896fe29 336{
a7812ae4 337 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 338}
339
951c6300
RH		 340static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
341 tcg_target_long offset)
c896fe29 342{
a7812ae4 343 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 344}
345
951c6300
RH		 346static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
347 tcg_target_long offset)
c896fe29 348{
a7812ae4 349 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 350}
351
951c6300
RH		 352static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
353 tcg_target_long offset)
c896fe29 354{
a7812ae4 355 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 356}
357
951c6300
RH		 358static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
359 tcg_target_long offset)
c896fe29 360{
a7812ae4 361 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 362}
363
951c6300
RH		 364static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
365 tcg_target_long offset)
c896fe29 366{
a7812ae4 367 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 368}
369
951c6300
RH		 370static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
371 tcg_target_long offset)
c896fe29 372{
a7812ae4 373 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 374}
375
951c6300
RH		 376static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
377 tcg_target_long offset)
c896fe29 378{
a7812ae4 379 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 380}
381
a7812ae4 382static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 383{
a7812ae4 384 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 385}
386
a7812ae4 387static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 388{
a7812ae4 389 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 390}
391
a7812ae4 392static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 393{
951c6300 394 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 395}
396
a7812ae4 397static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 398{
951c6300 399 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 400}
401
a7812ae4 402static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 403{
951c6300 404 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 405}
406
a7812ae4 407static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 408{
a7812ae4 409 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 410}
411
a7812ae4 412static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 413{
a7812ae4 414 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 415}
416
a7812ae4 417static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 418{
a7812ae4 419 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 420}
421
a7812ae4 422static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 423{
a7812ae4 424 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 425}
426
951c6300 427static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 428{
951c6300
RH		 429 if (TCG_TARGET_HAS_neg_i32) {
430 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 431 } else {
951c6300 432 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 433 }
31d66551
AJ		 434}
435
951c6300 436static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 437{
951c6300
RH		 438 if (TCG_TARGET_HAS_not_i32) {
439 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 440 } else {
951c6300 441 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 442 }
31d66551
AJ		 443}
444
951c6300
RH		 445/* 64 bit ops */
446
447void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
448void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
449void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
450void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
451void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
452void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
453void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
454void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
455void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
456void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
457void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
458void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
459void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
460void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
461void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
462void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
463void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
464void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
465void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
466void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
467void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
468void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
469void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
470void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
471 unsigned int ofs, unsigned int len);
42a268c2
RH		 472void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
473void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 474void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
475 TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
477 TCGv_i64 arg1, int64_t arg2);
478void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
479 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
480void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
481 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
482void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
483 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
484void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
485void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 486void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 487void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
488void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
489void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
490void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
491void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
492void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
493void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
494void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
495void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
496void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
c896fe29 497
951c6300
RH		 498#if TCG_TARGET_REG_BITS == 64
499static inline void tcg_gen_discard_i64(TCGv_i64 arg)
500{
501 tcg_gen_op1_i64(INDEX_op_discard, arg);
502}
c896fe29 503
a7812ae4 504static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 505{
fe75bcf7 506 if (!TCGV_EQUAL_I64(ret, arg)) {
951c6300 507 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 508 }
c896fe29
FB		 509}
510
a7812ae4 511static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 512{
951c6300 513 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 514}
515
a7812ae4
PB		 516static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
517 tcg_target_long offset)
c896fe29 518{
951c6300 519 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 520}
521
a7812ae4
PB		 522static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
523 tcg_target_long offset)
c896fe29 524{
951c6300 525 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 526}
527
a7812ae4
PB		 528static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
529 tcg_target_long offset)
c896fe29 530{
951c6300 531 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 532}
533
a7812ae4
PB		 534static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
535 tcg_target_long offset)
c896fe29 536{
951c6300 537 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 538}
539
a7812ae4
PB		 540static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
541 tcg_target_long offset)
c896fe29 542{
951c6300 543 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 544}
545
a7812ae4
PB		 546static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
547 tcg_target_long offset)
c896fe29 548{
951c6300 549 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 550}
551
a7812ae4
PB		 552static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
553 tcg_target_long offset)
c896fe29 554{
951c6300 555 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 556}
557
a7812ae4
PB		 558static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
559 tcg_target_long offset)
c896fe29 560{
951c6300 561 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 562}
563
a7812ae4
PB		 564static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
565 tcg_target_long offset)
c896fe29 566{
951c6300 567 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 568}
569
a7812ae4
PB		 570static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
571 tcg_target_long offset)
c896fe29 572{
951c6300 573 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 574}
575
a7812ae4
PB		 576static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
577 tcg_target_long offset)
c896fe29 578{
951c6300 579 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 580}
581
a7812ae4 582static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 583{
951c6300 584 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 585}
586
a7812ae4 587static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 588{
951c6300 589 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 590}
591
a7812ae4 592static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 593{
951c6300 594 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 595}
596
a7812ae4 597static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 598{
951c6300 599 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 600}
601
a7812ae4 602static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 603{
951c6300 604 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 605}
606
a7812ae4 607static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 608{
951c6300 609 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 610}
611
a7812ae4 612static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 613{
951c6300 614 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 615}
616
a7812ae4 617static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 618{
951c6300 619 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 620}
621
a7812ae4 622static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 623{
951c6300 624 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 625}
951c6300
RH		 626#else /* TCG_TARGET_REG_BITS == 32 */
627static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
628 tcg_target_long offset)
c896fe29 629{
951c6300 630 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 631}
632
951c6300
RH		 633static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
634 tcg_target_long offset)
c896fe29 635{
951c6300 636 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 637}
638
951c6300
RH		 639static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
640 tcg_target_long offset)
c896fe29 641{
951c6300 642 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 643}
644
951c6300 645static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 646{
951c6300
RH		 647 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
648 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 649}
650
951c6300 651static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 652{
951c6300
RH		 653 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
654 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
655}
656
657void tcg_gen_discard_i64(TCGv_i64 arg);
658void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
659void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
660void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
661void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
662void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
663void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
664void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
665void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
666void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
667void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
668void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
669void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
670void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
671void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
672void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
673void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
674void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
675#endif /* TCG_TARGET_REG_BITS */
c896fe29 676
951c6300 677static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 678{
951c6300
RH		 679 if (TCG_TARGET_HAS_neg_i64) {
680 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
681 } else {
682 tcg_gen_subfi_i64(ret, 0, arg);
683 }
c896fe29
FB		 684}
685
951c6300 686/* Size changing operations. */
c896fe29 687
951c6300
RH		 688void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
689void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
690void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 691void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
692void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 693void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
694void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 695
951c6300 696static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 697{
951c6300 698 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 699}
700
951c6300 701/* QEMU specific operations. */
c896fe29 702
951c6300
RH		 703#ifndef TARGET_LONG_BITS
704#error must include QEMU headers
705#endif
c896fe29 706
9aef40ed
RH		 707#if TARGET_INSN_START_WORDS == 1
708# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
709static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 710{
9aef40ed
RH		 711 tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc);
712}
713# else
714static inline void tcg_gen_insn_start(target_ulong pc)
715{
716 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start,
717 (uint32_t)pc, (uint32_t)(pc >> 32));
718}
719# endif
720#elif TARGET_INSN_START_WORDS == 2
721# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
722static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
723{
724 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1);
725}
726# else
727static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
728{
729 tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start,
730 (uint32_t)pc, (uint32_t)(pc >> 32),
731 (uint32_t)a1, (uint32_t)(a1 >> 32));
732}
733# endif
734#elif TARGET_INSN_START_WORDS == 3
735# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
736static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
737 target_ulong a2)
738{
739 tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
740}
741# else
742static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
743 target_ulong a2)
744{
745 tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start,
746 (uint32_t)pc, (uint32_t)(pc >> 32),
747 (uint32_t)a1, (uint32_t)(a1 >> 32),
748 (uint32_t)a2, (uint32_t)(a2 >> 32));
749}
750# endif
951c6300 751#else
9aef40ed 752# error "Unhandled number of operands to insn_start"
951c6300 753#endif
c896fe29 754
951c6300 755static inline void tcg_gen_exit_tb(uintptr_t val)
c896fe29 756{
951c6300 757 tcg_gen_op1i(INDEX_op_exit_tb, val);
c896fe29
FB		 758}
759
5b053a4a
SF		 760/**
761 * tcg_gen_goto_tb() - output goto_tb TCG operation
762 * @idx: Direct jump slot index (0 or 1)
763 *
764 * See tcg/README for more info about this TCG operation.
765 *
90aa39a1
SF		 766 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
767 * the pages this TB resides in because we don't take care of direct jumps when
768 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
769 * static address translation, so the destination address is always valid, TBs
770 * are always invalidated properly, and direct jumps are reset when mapping
771 * changes.
5b053a4a 772 */
951c6300 773void tcg_gen_goto_tb(unsigned idx);
c896fe29 774
a7812ae4 775#if TARGET_LONG_BITS == 32
a7812ae4
PB		 776#define tcg_temp_new() tcg_temp_new_i32()
777#define tcg_global_reg_new tcg_global_reg_new_i32
778#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 779#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 780#define tcg_temp_free tcg_temp_free_i32
a7812ae4 781#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
afcb92be 782#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
fe75bcf7 783#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
f713d6ad
RH		 784#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
785#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 786#else
a7812ae4
PB		 787#define tcg_temp_new() tcg_temp_new_i64()
788#define tcg_global_reg_new tcg_global_reg_new_i64
789#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 790#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 791#define tcg_temp_free tcg_temp_free_i64
a7812ae4 792#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
afcb92be 793#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
fe75bcf7 794#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
f713d6ad
RH		 795#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
796#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 797#endif
798
f713d6ad
RH		 799void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
800void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
801void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
802void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 803
ac56dd48 804static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 805{
f713d6ad 806 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 807}
808
ac56dd48 809static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 810{
f713d6ad 811 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 812}
813
ac56dd48 814static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 815{
f713d6ad 816 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 817}
818
ac56dd48 819static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 820{
f713d6ad 821 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 822}
823
ac56dd48 824static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 825{
f713d6ad 826 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 827}
828
ac56dd48 829static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 830{
f713d6ad 831 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 832}
833
a7812ae4 834static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 835{
f713d6ad 836 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 837}
838
ac56dd48 839static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 840{
f713d6ad 841 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 842}
843
ac56dd48 844static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 845{
f713d6ad 846 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 847}
848
ac56dd48 849static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 850{
f713d6ad 851 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 852}
853
a7812ae4 854static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 855{
f713d6ad 856 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 857}
858
c482cb11
RH		 859void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
860 TCGArg, TCGMemOp);
861void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
862 TCGArg, TCGMemOp);
863
864void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
865void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
866void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
867void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
868void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
869void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
870void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
871void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
872void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
873void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
874void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
875void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
876void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
877void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
878void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
879void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
880void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
881void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
882
f8422f52 883#if TARGET_LONG_BITS == 64
f8422f52
BS		 884#define tcg_gen_movi_tl tcg_gen_movi_i64
885#define tcg_gen_mov_tl tcg_gen_mov_i64
886#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
887#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
888#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
889#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
890#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
891#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
892#define tcg_gen_ld_tl tcg_gen_ld_i64
893#define tcg_gen_st8_tl tcg_gen_st8_i64
894#define tcg_gen_st16_tl tcg_gen_st16_i64
895#define tcg_gen_st32_tl tcg_gen_st32_i64
896#define tcg_gen_st_tl tcg_gen_st_i64
897#define tcg_gen_add_tl tcg_gen_add_i64
898#define tcg_gen_addi_tl tcg_gen_addi_i64
899#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 900#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 901#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 902#define tcg_gen_subi_tl tcg_gen_subi_i64
903#define tcg_gen_and_tl tcg_gen_and_i64
904#define tcg_gen_andi_tl tcg_gen_andi_i64
905#define tcg_gen_or_tl tcg_gen_or_i64
906#define tcg_gen_ori_tl tcg_gen_ori_i64
907#define tcg_gen_xor_tl tcg_gen_xor_i64
908#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 909#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 910#define tcg_gen_shl_tl tcg_gen_shl_i64
911#define tcg_gen_shli_tl tcg_gen_shli_i64
912#define tcg_gen_shr_tl tcg_gen_shr_i64
913#define tcg_gen_shri_tl tcg_gen_shri_i64
914#define tcg_gen_sar_tl tcg_gen_sar_i64
915#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 916#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 917#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 918#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 919#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 920#define tcg_gen_mul_tl tcg_gen_mul_i64
921#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 922#define tcg_gen_div_tl tcg_gen_div_i64
923#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 924#define tcg_gen_divu_tl tcg_gen_divu_i64
925#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 926#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 927#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 928#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
929#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
930#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
931#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
932#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 933#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
934#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
935#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
936#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
937#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
938#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 939#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
940#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
941#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 942#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 943#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 944#define tcg_gen_andc_tl tcg_gen_andc_i64
945#define tcg_gen_eqv_tl tcg_gen_eqv_i64
946#define tcg_gen_nand_tl tcg_gen_nand_i64
947#define tcg_gen_nor_tl tcg_gen_nor_i64
948#define tcg_gen_orc_tl tcg_gen_orc_i64
15824571
AJ		 949#define tcg_gen_rotl_tl tcg_gen_rotl_i64
950#define tcg_gen_rotli_tl tcg_gen_rotli_i64
951#define tcg_gen_rotr_tl tcg_gen_rotr_i64
952#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 953#define tcg_gen_deposit_tl tcg_gen_deposit_i64
a98824ac 954#define tcg_const_tl tcg_const_i64
bdffd4a9 955#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 956#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 957#define tcg_gen_add2_tl tcg_gen_add2_i64
958#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 959#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
960#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 961#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
c482cb11
RH		 962#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
963#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
964#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
965#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
966#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
967#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
968#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
969#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
970#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
971#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
f8422f52 972#else
f8422f52
BS		 973#define tcg_gen_movi_tl tcg_gen_movi_i32
974#define tcg_gen_mov_tl tcg_gen_mov_i32
975#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
976#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
977#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
978#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
979#define tcg_gen_ld32u_tl tcg_gen_ld_i32
980#define tcg_gen_ld32s_tl tcg_gen_ld_i32
981#define tcg_gen_ld_tl tcg_gen_ld_i32
982#define tcg_gen_st8_tl tcg_gen_st8_i32
983#define tcg_gen_st16_tl tcg_gen_st16_i32
984#define tcg_gen_st32_tl tcg_gen_st_i32
985#define tcg_gen_st_tl tcg_gen_st_i32
986#define tcg_gen_add_tl tcg_gen_add_i32
987#define tcg_gen_addi_tl tcg_gen_addi_i32
988#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 989#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 990#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 991#define tcg_gen_subi_tl tcg_gen_subi_i32
992#define tcg_gen_and_tl tcg_gen_and_i32
993#define tcg_gen_andi_tl tcg_gen_andi_i32
994#define tcg_gen_or_tl tcg_gen_or_i32
995#define tcg_gen_ori_tl tcg_gen_ori_i32
996#define tcg_gen_xor_tl tcg_gen_xor_i32
997#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 998#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 999#define tcg_gen_shl_tl tcg_gen_shl_i32
1000#define tcg_gen_shli_tl tcg_gen_shli_i32
1001#define tcg_gen_shr_tl tcg_gen_shr_i32
1002#define tcg_gen_shri_tl tcg_gen_shri_i32
1003#define tcg_gen_sar_tl tcg_gen_sar_i32
1004#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1005#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1006#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1007#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1008#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1009#define tcg_gen_mul_tl tcg_gen_mul_i32
1010#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1011#define tcg_gen_div_tl tcg_gen_div_i32
1012#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1013#define tcg_gen_divu_tl tcg_gen_divu_i32
1014#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1015#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1016#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1017#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1018#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1019#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1020#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1021#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1022#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1023#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1024#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1025#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1026#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1027#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1028#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1029#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1030#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1031#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1032#define tcg_gen_andc_tl tcg_gen_andc_i32
1033#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1034#define tcg_gen_nand_tl tcg_gen_nand_i32
1035#define tcg_gen_nor_tl tcg_gen_nor_i32
1036#define tcg_gen_orc_tl tcg_gen_orc_i32
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AJ		 1037#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1038#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1039#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1040#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1041#define tcg_gen_deposit_tl tcg_gen_deposit_i32
a98824ac 1042#define tcg_const_tl tcg_const_i32
bdffd4a9 1043#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1044#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1045#define tcg_gen_add2_tl tcg_gen_add2_i32
1046#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1047#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1048#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1049#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
c482cb11
RH		 1050#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1051#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1052#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1053#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1054#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1055#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1056#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1057#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1058#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1059#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
f8422f52 1060#endif
6ddbc6e4 1061
71b92699 1062#if UINTPTR_MAX == UINT32_MAX
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RH		 1063# define tcg_gen_ld_ptr(R, A, O) \
1064 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
1065# define tcg_gen_discard_ptr(A) \
1066 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
1067# define tcg_gen_add_ptr(R, A, B) \
1068 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1069# define tcg_gen_addi_ptr(R, A, B) \
1070 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1071# define tcg_gen_ext_i32_ptr(R, A) \
1072 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
1073#else
1074# define tcg_gen_ld_ptr(R, A, O) \
1075 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
1076# define tcg_gen_discard_ptr(A) \
1077 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
1078# define tcg_gen_add_ptr(R, A, B) \
1079 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1080# define tcg_gen_addi_ptr(R, A, B) \
1081 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1082# define tcg_gen_ext_i32_ptr(R, A) \
1083 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
71b92699 1084#endif /* UINTPTR_MAX == UINT32_MAX */
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