[qemu.git] / hw / i2c / omap_i2c.c

/*
 * TI OMAP on-chip I2C controller.  Only "new I2C" mode supported.
 *
 * Copyright (C) 2007 Andrzej Zaborowski  <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"

#define TYPE_OMAP_I2C "omap_i2c"
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)

typedef struct OMAPI2CState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq drq[2];
    I2CBus *bus;

    uint8_t revision;
    void *iclk;
    void *fclk;

    uint8_t mask;
    uint16_t stat;
    uint16_t dma;
    uint16_t count;
    int count_cur;
    uint32_t fifo;
    int rxlen;
    int txlen;
    uint16_t control;
    uint16_t addr[2];
    uint8_t divider;
    uint8_t times[2];
    uint16_t test;
} OMAPI2CState;

#define OMAP2_INTR_REV	0x34
#define OMAP2_GC_REV	0x34

static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
    qemu_set_irq(s->irq, s->stat & s->mask);
    if ((s->dma >> 15) & 1)					/* RDMA_EN */
        qemu_set_irq(s->drq[0], (s->stat >> 3) & 1);		/* RRDY */
    if ((s->dma >> 7) & 1)					/* XDMA_EN */
        qemu_set_irq(s->drq[1], (s->stat >> 4) & 1);		/* XRDY */
}

static void omap_i2c_fifo_run(OMAPI2CState *s)
{
    int ack = 1;

    if (!i2c_bus_busy(s->bus))
        return;

    if ((s->control >> 2) & 1) {				/* RM */
        if ((s->control >> 1) & 1) {				/* STP */
            i2c_end_transfer(s->bus);
            s->control &= ~(1 << 1);				/* STP */
            s->count_cur = s->count;
            s->txlen = 0;
        } else if ((s->control >> 9) & 1) {			/* TRX */
            while (ack && s->txlen)
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
            s->stat |= 1 << 4;					/* XRDY */
        } else {
            while (s->rxlen < 4)
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
            s->stat |= 1 << 3;					/* RRDY */
        }
    } else {
        if ((s->control >> 9) & 1) {				/* TRX */
            while (ack && s->count_cur && s->txlen) {
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
                s->count_cur --;
            }
            if (ack && s->count_cur)
                s->stat |= 1 << 4;				/* XRDY */
            else
                s->stat &= ~(1 << 4);				/* XRDY */
            if (!s->count_cur) {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        } else {
            while (s->count_cur && s->rxlen < 4) {
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
                s->count_cur --;
            }
            if (s->rxlen)
                s->stat |= 1 << 3;				/* RRDY */
            else
                s->stat &= ~(1 << 3);				/* RRDY */
        }
        if (!s->count_cur) {
            if ((s->control >> 1) & 1) {			/* STP */
                i2c_end_transfer(s->bus);
                s->control &= ~(1 << 1);			/* STP */
                s->count_cur = s->count;
                s->txlen = 0;
            } else {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
    }

    s->stat |= (!ack) << 1;					/* NACK */
    if (!ack)
        s->control &= ~(1 << 1);				/* STP */
}

static void omap_i2c_reset(DeviceState *dev)
{
    OMAPI2CState *s = OMAP_I2C(dev);

    s->mask = 0;
    s->stat = 0;
    s->dma = 0;
    s->count = 0;
    s->count_cur = 0;
    s->fifo = 0;
    s->rxlen = 0;
    s->txlen = 0;
    s->control = 0;
    s->addr[0] = 0;
    s->addr[1] = 0;
    s->divider = 0;
    s->times[0] = 0;
    s->times[1] = 0;
    s->test = 0;
}

static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    uint16_t ret;

    switch (offset) {
    case 0x00:	/* I2C_REV */
        return s->revision;					/* REV */

    case 0x04:	/* I2C_IE */
        return s->mask;

    case 0x08:	/* I2C_STAT */
        return s->stat | (i2c_bus_busy(s->bus) << 12);

    case 0x0c:	/* I2C_IV */
        if (s->revision >= OMAP2_INTR_REV)
            break;
        ret = ctz32(s->stat & s->mask);
        if (ret != 32) {
            s->stat ^= 1 << ret;
            ret++;
        } else {
            ret = 0;
        }
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x10:	/* I2C_SYSS */
        return (s->control >> 15) & 1;				/* I2C_EN */

    case 0x14:	/* I2C_BUF */
        return s->dma;

    case 0x18:	/* I2C_CNT */
        return s->count_cur;					/* DCOUNT */

    case 0x1c:	/* I2C_DATA */
        ret = 0;
        if (s->control & (1 << 14)) {				/* BE */
            ret |= ((s->fifo >> 0) & 0xff) << 8;
            ret |= ((s->fifo >> 8) & 0xff) << 0;
        } else {
            ret |= ((s->fifo >> 8) & 0xff) << 8;
            ret |= ((s->fifo >> 0) & 0xff) << 0;
        }
        if (s->rxlen == 1) {
            s->stat |= 1 << 15;					/* SBD */
            s->rxlen = 0;
        } else if (s->rxlen > 1) {
            if (s->rxlen > 2)
                s->fifo >>= 16;
            s->rxlen -= 2;
        } else {
            /* XXX: remote access (qualifier) error - what's that?  */
        }
        if (!s->rxlen) {
            s->stat &= ~(1 << 3);				/* RRDY */
            if (((s->control >> 10) & 1) &&			/* MST */
                            ((~s->control >> 9) & 1)) {		/* TRX */
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
        s->stat &= ~(1 << 11);					/* ROVR */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x20:	/* I2C_SYSC */
        return 0;

    case 0x24:	/* I2C_CON */
        return s->control;

    case 0x28:	/* I2C_OA */
        return s->addr[0];

    case 0x2c:	/* I2C_SA */
        return s->addr[1];

    case 0x30:	/* I2C_PSC */
        return s->divider;

    case 0x34:	/* I2C_SCLL */
        return s->times[0];

    case 0x38:	/* I2C_SCLH */
        return s->times[1];

    case 0x3c:	/* I2C_SYSTEST */
        if (s->test & (1 << 15)) {				/* ST_EN */
            s->test ^= 0xa;
            return s->test;
        } else
            return s->test & ~0x300f;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_i2c_write(void *opaque, hwaddr addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    int nack;

    switch (offset) {
    case 0x00:	/* I2C_REV */
    case 0x0c:	/* I2C_IV */
    case 0x10:	/* I2C_SYSS */
        OMAP_RO_REG(addr);
        return;

    case 0x04:	/* I2C_IE */
        s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
        break;

    case 0x08:	/* I2C_STAT */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_RO_REG(addr);
            return;
        }

        /* RRDY and XRDY are reset by hardware. (in all versions???) */
        s->stat &= ~(value & 0x27);
        omap_i2c_interrupts_update(s);
        break;

    case 0x14:	/* I2C_BUF */
        s->dma = value & 0x8080;
        if (value & (1 << 15))					/* RDMA_EN */
            s->mask &= ~(1 << 3);				/* RRDY_IE */
        if (value & (1 << 7))					/* XDMA_EN */
            s->mask &= ~(1 << 4);				/* XRDY_IE */
        break;

    case 0x18:	/* I2C_CNT */
        s->count = value;					/* DCOUNT */
        break;

    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 16;
        s->txlen += 2;
        if (s->control & (1 << 14)) {				/* BE */
            s->fifo |= ((value >> 8) & 0xff) << 8;
            s->fifo |= ((value >> 0) & 0xff) << 0;
        } else {
            s->fifo |= ((value >> 0) & 0xff) << 8;
            s->fifo |= ((value >> 8) & 0xff) << 0;
        }
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    case 0x20:	/* I2C_SYSC */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_BAD_REG(addr);
            return;
        }

        if (value & 2) {
            omap_i2c_reset(DEVICE(s));
        }
        break;

    case 0x24:	/* I2C_CON */
        s->control = value & 0xcf87;
        if (~value & (1 << 15)) {				/* I2C_EN */
            if (s->revision < OMAP2_INTR_REV) {
                omap_i2c_reset(DEVICE(s));
            }
            break;
        }
        if ((value & (1 << 15)) && !(value & (1 << 10))) {    /* MST */
            qemu_log_mask(LOG_UNIMP, "%s: I^2C slave mode not supported\n",
                          __func__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 8)) {        /* XA */
            qemu_log_mask(LOG_UNIMP,
                          "%s: 10-bit addressing mode not supported\n",
                          __func__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 0)) {		/* STT */
            nack = !!i2c_start_transfer(s->bus, s->addr[1],	/* SA */
                            (~value >> 9) & 1);			/* TRX */
            s->stat |= nack << 1;				/* NACK */
            s->control &= ~(1 << 0);				/* STT */
            s->fifo = 0;
            if (nack)
                s->control &= ~(1 << 1);			/* STP */
            else {
                s->count_cur = s->count;
                omap_i2c_fifo_run(s);
            }
            omap_i2c_interrupts_update(s);
        }
        break;

    case 0x28:	/* I2C_OA */
        s->addr[0] = value & 0x3ff;
        break;

    case 0x2c:	/* I2C_SA */
        s->addr[1] = value & 0x3ff;
        break;

    case 0x30:	/* I2C_PSC */
        s->divider = value;
        break;

    case 0x34:	/* I2C_SCLL */
        s->times[0] = value;
        break;

    case 0x38:	/* I2C_SCLH */
        s->times[1] = value;
        break;

    case 0x3c:	/* I2C_SYSTEST */
        s->test = value & 0xf80f;
        if (value & (1 << 11))					/* SBB */
            if (s->revision >= OMAP2_INTR_REV) {
                s->stat |= 0x3f;
                omap_i2c_interrupts_update(s);
            }
        if (value & (1 << 15)) {                    /* ST_EN */
            qemu_log_mask(LOG_UNIMP,
                          "%s: System Test not supported\n", __func__);
        }
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static void omap_i2c_writeb(void *opaque, hwaddr addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;

    switch (offset) {
    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 8;
        s->txlen += 1;
        s->fifo |= value & 0xff;
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
                                unsigned size)
{
    switch (size) {
    case 2:
        return omap_i2c_read(opaque, addr);
    default:
        return omap_badwidth_read16(opaque, addr);
    }
}

static void omap_i2c_writefn(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    switch (size) {
    case 1:
        /* Only the last fifo write can be 8 bit. */
        omap_i2c_writeb(opaque, addr, value);
        break;
    case 2:
        omap_i2c_write(opaque, addr, value);
        break;
    default:
        omap_badwidth_write16(opaque, addr, value);
        break;
    }
}

static const MemoryRegionOps omap_i2c_ops = {
    .read = omap_i2c_readfn,
    .write = omap_i2c_writefn,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void omap_i2c_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    OMAPI2CState *s = OMAP_I2C(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->drq[0]);
    sysbus_init_irq(sbd, &s->drq[1]);
    sysbus_init_mmio(sbd, &s->iomem);
    s->bus = i2c_init_bus(dev, NULL);
}

static void omap_i2c_realize(DeviceState *dev, Error **errp)
{
    OMAPI2CState *s = OMAP_I2C(dev);

    memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c",
                          (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);

    if (!s->fclk) {
        error_setg(errp, "omap_i2c: fclk not connected");
        return;
    }
    if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
        /* Note that OMAP1 doesn't have a separate interface clock */
        error_setg(errp, "omap_i2c: iclk not connected");
        return;
    }
}

static Property omap_i2c_properties[] = {
    DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
    DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
    DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->props = omap_i2c_properties;
    dc->reset = omap_i2c_reset;
    /* Reason: pointer properties "iclk", "fclk" */
    dc->user_creatable = false;
    dc->realize = omap_i2c_realize;
}

static const TypeInfo omap_i2c_info = {
    .name = TYPE_OMAP_I2C,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(OMAPI2CState),
    .instance_init = omap_i2c_init,
    .class_init = omap_i2c_class_init,
};

static void omap_i2c_register_types(void)
{
    type_register_static(&omap_i2c_info);
}

I2CBus *omap_i2c_bus(DeviceState *omap_i2c)
{
    OMAPI2CState *s = OMAP_I2C(omap_i2c);
    return s->bus;
}

type_init(omap_i2c_register_types)
Commit	Line	Data
02645926 AZ	1	/*
	2	* TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
	3	*
	4	* Copyright (C) 2007 Andrzej Zaborowski <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
02645926	18	*/
0b8fa32f	19
17b7f2db	20	#include "qemu/osdep.h"
8d2774f0	21	#include "qemu/log.h"
0b8fa32f	22	#include "qemu/module.h"
83c9f4ca	23	#include "hw/hw.h"
0d09e41a	24	#include "hw/i2c/i2c.h"
64552b6b	25	#include "hw/irq.h"
0d09e41a	26	#include "hw/arm/omap.h"
83c9f4ca	27	#include "hw/sysbus.h"
84a3a53c	28	#include "qemu/error-report.h"
758aba7d	29	#include "qapi/error.h"
02645926	30
60ecfcb3 AF	31	#define TYPE_OMAP_I2C "omap_i2c"
60ecfcb3 AF	32	#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
54e17933 JR	33
54e17933 JR	34	typedef struct OMAPI2CState {
60ecfcb3 AF	35	SysBusDevice parent_obj;
60ecfcb3 AF	36
74878139	37	MemoryRegion iomem;
02645926 AZ	38	qemu_irq irq;
02645926 AZ	39	qemu_irq drq[2];
a5c82852	40	I2CBus *bus;
02645926	41
29885477	42	uint8_t revision;
54e17933 JR	43	void *iclk;
	44	void *fclk;
	45
02645926 AZ	46	uint8_t mask;
	47	uint16_t stat;
	48	uint16_t dma;
	49	uint16_t count;
	50	int count_cur;
	51	uint32_t fifo;
	52	int rxlen;
	53	int txlen;
	54	uint16_t control;
	55	uint16_t addr[2];
	56	uint8_t divider;
	57	uint8_t times[2];
	58	uint16_t test;
54e17933	59	} OMAPI2CState;
02645926	60
29885477 AZ	61	#define OMAP2_INTR_REV 0x34
	62	#define OMAP2_GC_REV 0x34
	63
54e17933	64	static void omap_i2c_interrupts_update(OMAPI2CState *s)
02645926 AZ	65	{
	66	qemu_set_irq(s->irq, s->stat & s->mask);
	67	if ((s->dma >> 15) & 1) /* RDMA_EN */
	68	qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
	69	if ((s->dma >> 7) & 1) /* XDMA_EN */
	70	qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
	71	}
	72
54e17933	73	static void omap_i2c_fifo_run(OMAPI2CState *s)
02645926 AZ	74	{
	75	int ack = 1;
	76
	77	if (!i2c_bus_busy(s->bus))
	78	return;
	79
	80	if ((s->control >> 2) & 1) { /* RM */
	81	if ((s->control >> 1) & 1) { /* STP */
	82	i2c_end_transfer(s->bus);
	83	s->control &= ~(1 << 1); /* STP */
	84	s->count_cur = s->count;
29885477	85	s->txlen = 0;
02645926 AZ	86	} else if ((s->control >> 9) & 1) { /* TRX */
	87	while (ack && s->txlen)
	88	ack = (i2c_send(s->bus,
	89	(s->fifo >> ((-- s->txlen) << 3)) &
	90	0xff) >= 0);
	91	s->stat \|= 1 << 4; /* XRDY */
	92	} else {
	93	while (s->rxlen < 4)
	94	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	95	s->stat \|= 1 << 3; /* RRDY */
	96	}
	97	} else {
	98	if ((s->control >> 9) & 1) { /* TRX */
	99	while (ack && s->count_cur && s->txlen) {
	100	ack = (i2c_send(s->bus,
	101	(s->fifo >> ((-- s->txlen) << 3)) &
	102	0xff) >= 0);
	103	s->count_cur --;
	104	}
	105	if (ack && s->count_cur)
	106	s->stat \|= 1 << 4; /* XRDY */
827df9f3 AZ	107	else
827df9f3 AZ	108	s->stat &= ~(1 << 4); /* XRDY */
02645926 AZ	109	if (!s->count_cur) {
	110	s->stat \|= 1 << 2; /* ARDY */
	111	s->control &= ~(1 << 10); /* MST */
	112	}
	113	} else {
	114	while (s->count_cur && s->rxlen < 4) {
	115	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	116	s->count_cur --;
	117	}
	118	if (s->rxlen)
	119	s->stat \|= 1 << 3; /* RRDY */
827df9f3 AZ	120	else
827df9f3 AZ	121	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	122	}
	123	if (!s->count_cur) {
	124	if ((s->control >> 1) & 1) { /* STP */
	125	i2c_end_transfer(s->bus);
	126	s->control &= ~(1 << 1); /* STP */
	127	s->count_cur = s->count;
29885477	128	s->txlen = 0;
02645926 AZ	129	} else {
	130	s->stat \|= 1 << 2; /* ARDY */
	131	s->control &= ~(1 << 10); /* MST */
	132	}
	133	}
	134	}
	135
	136	s->stat \|= (!ack) << 1; /* NACK */
	137	if (!ack)
	138	s->control &= ~(1 << 1); /* STP */
	139	}
	140
54e17933	141	static void omap_i2c_reset(DeviceState *dev)
02645926	142	{
60ecfcb3 AF	143	OMAPI2CState *s = OMAP_I2C(dev);
60ecfcb3 AF	144
02645926 AZ	145	s->mask = 0;
	146	s->stat = 0;
	147	s->dma = 0;
	148	s->count = 0;
	149	s->count_cur = 0;
	150	s->fifo = 0;
	151	s->rxlen = 0;
	152	s->txlen = 0;
	153	s->control = 0;
	154	s->addr[0] = 0;
	155	s->addr[1] = 0;
	156	s->divider = 0;
	157	s->times[0] = 0;
	158	s->times[1] = 0;
	159	s->test = 0;
	160	}
	161
a8170e5e	162	static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
02645926	163	{
54e17933	164	OMAPI2CState *s = opaque;
cf965d24	165	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	166	uint16_t ret;
	167
	168	switch (offset) {
	169	case 0x00: /* I2C_REV */
29885477	170	return s->revision; /* REV */
02645926 AZ	171
	172	case 0x04: /* I2C_IE */
	173	return s->mask;
	174
	175	case 0x08: /* I2C_STAT */
	176	return s->stat \| (i2c_bus_busy(s->bus) << 12);
	177
	178	case 0x0c: /* I2C_IV */
29885477 AZ	179	if (s->revision >= OMAP2_INTR_REV)
29885477 AZ	180	break;
bd2a8884 SH	181	ret = ctz32(s->stat & s->mask);
	182	if (ret != 32) {
	183	s->stat ^= 1 << ret;
	184	ret++;
	185	} else {
	186	ret = 0;
	187	}
02645926 AZ	188	omap_i2c_interrupts_update(s);
	189	return ret;
	190
29885477 AZ	191	case 0x10: /* I2C_SYSS */
	192	return (s->control >> 15) & 1; /* I2C_EN */
	193
02645926 AZ	194	case 0x14: /* I2C_BUF */
	195	return s->dma;
	196
	197	case 0x18: /* I2C_CNT */
	198	return s->count_cur; /* DCOUNT */
	199
	200	case 0x1c: /* I2C_DATA */
	201	ret = 0;
	202	if (s->control & (1 << 14)) { /* BE */
	203	ret \|= ((s->fifo >> 0) & 0xff) << 8;
	204	ret \|= ((s->fifo >> 8) & 0xff) << 0;
	205	} else {
	206	ret \|= ((s->fifo >> 8) & 0xff) << 8;
	207	ret \|= ((s->fifo >> 0) & 0xff) << 0;
	208	}
	209	if (s->rxlen == 1) {
	210	s->stat \|= 1 << 15; /* SBD */
	211	s->rxlen = 0;
	212	} else if (s->rxlen > 1) {
	213	if (s->rxlen > 2)
	214	s->fifo >>= 16;
	215	s->rxlen -= 2;
3ffd710e BS	216	} else {
	217	/* XXX: remote access (qualifier) error - what's that? */
	218	}
02645926	219	if (!s->rxlen) {
29885477	220	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	221	if (((s->control >> 10) & 1) && /* MST */
	222	((~s->control >> 9) & 1)) { /* TRX */
	223	s->stat \|= 1 << 2; /* ARDY */
	224	s->control &= ~(1 << 10); /* MST */
	225	}
	226	}
	227	s->stat &= ~(1 << 11); /* ROVR */
	228	omap_i2c_fifo_run(s);
	229	omap_i2c_interrupts_update(s);
	230	return ret;
	231
29885477 AZ	232	case 0x20: /* I2C_SYSC */
	233	return 0;
	234
02645926 AZ	235	case 0x24: /* I2C_CON */
	236	return s->control;
	237
	238	case 0x28: /* I2C_OA */
	239	return s->addr[0];
	240
	241	case 0x2c: /* I2C_SA */
	242	return s->addr[1];
	243
	244	case 0x30: /* I2C_PSC */
	245	return s->divider;
	246
	247	case 0x34: /* I2C_SCLL */
	248	return s->times[0];
	249
	250	case 0x38: /* I2C_SCLH */
	251	return s->times[1];
	252
	253	case 0x3c: /* I2C_SYSTEST */
	254	if (s->test & (1 << 15)) { /* ST_EN */
	255	s->test ^= 0xa;
	256	return s->test;
	257	} else
	258	return s->test & ~0x300f;
	259	}
	260
	261	OMAP_BAD_REG(addr);
	262	return 0;
	263	}
	264
a8170e5e	265	static void omap_i2c_write(void *opaque, hwaddr addr,
02645926 AZ	266	uint32_t value)
02645926 AZ	267	{
54e17933	268	OMAPI2CState *s = opaque;
cf965d24	269	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	270	int nack;
	271
	272	switch (offset) {
	273	case 0x00: /* I2C_REV */
02645926	274	case 0x0c: /* I2C_IV */
29885477 AZ	275	case 0x10: /* I2C_SYSS */
29885477 AZ	276	OMAP_RO_REG(addr);
02645926 AZ	277	return;
	278
	279	case 0x04: /* I2C_IE */
29885477 AZ	280	s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
	281	break;
	282
	283	case 0x08: /* I2C_STAT */
	284	if (s->revision < OMAP2_INTR_REV) {
	285	OMAP_RO_REG(addr);
	286	return;
	287	}
	288
827df9f3 AZ	289	/* RRDY and XRDY are reset by hardware. (in all versions???) */
827df9f3 AZ	290	s->stat &= ~(value & 0x27);
29885477	291	omap_i2c_interrupts_update(s);
02645926 AZ	292	break;
	293
	294	case 0x14: /* I2C_BUF */
	295	s->dma = value & 0x8080;
	296	if (value & (1 << 15)) /* RDMA_EN */
	297	s->mask &= ~(1 << 3); /* RRDY_IE */
	298	if (value & (1 << 7)) /* XDMA_EN */
	299	s->mask &= ~(1 << 4); /* XRDY_IE */
	300	break;
	301
	302	case 0x18: /* I2C_CNT */
	303	s->count = value; /* DCOUNT */
	304	break;
	305
	306	case 0x1c: /* I2C_DATA */
	307	if (s->txlen > 2) {
	308	/* XXX: remote access (qualifier) error - what's that? */
	309	break;
	310	}
	311	s->fifo <<= 16;
	312	s->txlen += 2;
	313	if (s->control & (1 << 14)) { /* BE */
	314	s->fifo \|= ((value >> 8) & 0xff) << 8;
	315	s->fifo \|= ((value >> 0) & 0xff) << 0;
	316	} else {
	317	s->fifo \|= ((value >> 0) & 0xff) << 8;
	318	s->fifo \|= ((value >> 8) & 0xff) << 0;
	319	}
	320	s->stat &= ~(1 << 10); /* XUDF */
	321	if (s->txlen > 2)
	322	s->stat &= ~(1 << 4); /* XRDY */
	323	omap_i2c_fifo_run(s);
	324	omap_i2c_interrupts_update(s);
	325	break;
	326
29885477 AZ	327	case 0x20: /* I2C_SYSC */
	328	if (s->revision < OMAP2_INTR_REV) {
	329	OMAP_BAD_REG(addr);
	330	return;
	331	}
	332
60ecfcb3 AF	333	if (value & 2) {
	334	omap_i2c_reset(DEVICE(s));
	335	}
29885477 AZ	336	break;
29885477 AZ	337
02645926	338	case 0x24: /* I2C_CON */
29885477	339	s->control = value & 0xcf87;
02645926	340	if (~value & (1 << 15)) { /* I2C_EN */
60ecfcb3 AF	341	if (s->revision < OMAP2_INTR_REV) {
	342	omap_i2c_reset(DEVICE(s));
	343	}
02645926 AZ	344	break;
02645926 AZ	345	}
8d2774f0 PMD	346	if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
	347	qemu_log_mask(LOG_UNIMP, "%s: I^2C slave mode not supported\n",
	348	__func__);
02645926 AZ	349	break;
02645926 AZ	350	}
8d2774f0 PMD	351	if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
	352	qemu_log_mask(LOG_UNIMP,
	353	"%s: 10-bit addressing mode not supported\n",
	354	__func__);
02645926 AZ	355	break;
02645926 AZ	356	}
29885477	357	if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
02645926 AZ	358	nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
	359	(~value >> 9) & 1); /* TRX */
	360	s->stat \|= nack << 1; /* NACK */
	361	s->control &= ~(1 << 0); /* STT */
51fec3cc	362	s->fifo = 0;
02645926 AZ	363	if (nack)
02645926 AZ	364	s->control &= ~(1 << 1); /* STP */
29885477 AZ	365	else {
29885477 AZ	366	s->count_cur = s->count;
02645926	367	omap_i2c_fifo_run(s);
29885477	368	}
02645926 AZ	369	omap_i2c_interrupts_update(s);
	370	}
	371	break;
	372
	373	case 0x28: /* I2C_OA */
	374	s->addr[0] = value & 0x3ff;
02645926 AZ	375	break;
	376
	377	case 0x2c: /* I2C_SA */
	378	s->addr[1] = value & 0x3ff;
	379	break;
	380
	381	case 0x30: /* I2C_PSC */
	382	s->divider = value;
	383	break;
	384
	385	case 0x34: /* I2C_SCLL */
	386	s->times[0] = value;
	387	break;
	388
	389	case 0x38: /* I2C_SCLH */
	390	s->times[1] = value;
	391	break;
	392
	393	case 0x3c: /* I2C_SYSTEST */
29885477 AZ	394	s->test = value & 0xf80f;
	395	if (value & (1 << 11)) /* SBB */
	396	if (s->revision >= OMAP2_INTR_REV) {
	397	s->stat \|= 0x3f;
	398	omap_i2c_interrupts_update(s);
	399	}
8d2774f0 PMD	400	if (value & (1 << 15)) { /* ST_EN */
	401	qemu_log_mask(LOG_UNIMP,
	402	"%s: System Test not supported\n", __func__);
	403	}
02645926 AZ	404	break;
	405
	406	default:
	407	OMAP_BAD_REG(addr);
	408	return;
	409	}
	410	}
	411
a8170e5e	412	static void omap_i2c_writeb(void *opaque, hwaddr addr,
29885477 AZ	413	uint32_t value)
29885477 AZ	414	{
54e17933	415	OMAPI2CState *s = opaque;
29885477 AZ	416	int offset = addr & OMAP_MPUI_REG_MASK;
	417
	418	switch (offset) {
	419	case 0x1c: /* I2C_DATA */
	420	if (s->txlen > 2) {
	421	/* XXX: remote access (qualifier) error - what's that? */
	422	break;
	423	}
	424	s->fifo <<= 8;
	425	s->txlen += 1;
	426	s->fifo \|= value & 0xff;
	427	s->stat &= ~(1 << 10); /* XUDF */
	428	if (s->txlen > 2)
	429	s->stat &= ~(1 << 4); /* XRDY */
	430	omap_i2c_fifo_run(s);
	431	omap_i2c_interrupts_update(s);
	432	break;
	433
	434	default:
	435	OMAP_BAD_REG(addr);
	436	return;
	437	}
	438	}
	439
28dc207f PM	440	static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
	441	unsigned size)
	442	{
	443	switch (size) {
	444	case 2:
	445	return omap_i2c_read(opaque, addr);
	446	default:
	447	return omap_badwidth_read16(opaque, addr);
	448	}
	449	}
	450
	451	static void omap_i2c_writefn(void *opaque, hwaddr addr,
	452	uint64_t value, unsigned size)
	453	{
	454	switch (size) {
	455	case 1:
	456	/* Only the last fifo write can be 8 bit. */
	457	omap_i2c_writeb(opaque, addr, value);
	458	break;
	459	case 2:
	460	omap_i2c_write(opaque, addr, value);
	461	break;
	462	default:
	463	omap_badwidth_write16(opaque, addr, value);
	464	break;
	465	}
	466	}
	467
74878139	468	static const MemoryRegionOps omap_i2c_ops = {
28dc207f PM	469	.read = omap_i2c_readfn,
	470	.write = omap_i2c_writefn,
	471	.valid.min_access_size = 1,
	472	.valid.max_access_size = 4,
74878139	473	.endianness = DEVICE_NATIVE_ENDIAN,
02645926 AZ	474	};
02645926 AZ	475
758aba7d XZ	476	static void omap_i2c_init(Object *obj)
	477	{
	478	DeviceState *dev = DEVICE(obj);
	479	OMAPI2CState *s = OMAP_I2C(obj);
	480	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	481
	482	sysbus_init_irq(sbd, &s->irq);
	483	sysbus_init_irq(sbd, &s->drq[0]);
	484	sysbus_init_irq(sbd, &s->drq[1]);
	485	sysbus_init_mmio(sbd, &s->iomem);
	486	s->bus = i2c_init_bus(dev, NULL);
	487	}
	488
	489	static void omap_i2c_realize(DeviceState dev, Error *errp)
02645926	490	{
60ecfcb3	491	OMAPI2CState *s = OMAP_I2C(dev);
02645926	492
758aba7d XZ	493	memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c",
	494	(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
	495
54e17933	496	if (!s->fclk) {
758aba7d XZ	497	error_setg(errp, "omap_i2c: fclk not connected");
758aba7d XZ	498	return;
54e17933 JR	499	}
	500	if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
	501	/* Note that OMAP1 doesn't have a separate interface clock */
758aba7d XZ	502	error_setg(errp, "omap_i2c: iclk not connected");
758aba7d XZ	503	return;
54e17933	504	}
02645926 AZ	505	}
02645926 AZ	506
54e17933 JR	507	static Property omap_i2c_properties[] = {
	508	DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
	509	DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
	510	DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
	511	DEFINE_PROP_END_OF_LIST(),
	512	};
29885477	513
54e17933 JR	514	static void omap_i2c_class_init(ObjectClass klass, void data)
	515	{
	516	DeviceClass *dc = DEVICE_CLASS(klass);
758aba7d	517
54e17933 JR	518	dc->props = omap_i2c_properties;
54e17933 JR	519	dc->reset = omap_i2c_reset;
1b111dc1	520	/* Reason: pointer properties "iclk", "fclk" */
e90f2a8c	521	dc->user_creatable = false;
758aba7d	522	dc->realize = omap_i2c_realize;
54e17933	523	}
29885477	524
8c43a6f0	525	static const TypeInfo omap_i2c_info = {
60ecfcb3	526	.name = TYPE_OMAP_I2C,
54e17933 JR	527	.parent = TYPE_SYS_BUS_DEVICE,
54e17933 JR	528	.instance_size = sizeof(OMAPI2CState),
758aba7d	529	.instance_init = omap_i2c_init,
54e17933 JR	530	.class_init = omap_i2c_class_init,
54e17933 JR	531	};
29885477	532
54e17933 JR	533	static void omap_i2c_register_types(void)
	534	{
	535	type_register_static(&omap_i2c_info);
29885477 AZ	536	}
29885477 AZ	537
a5c82852	538	I2CBus omap_i2c_bus(DeviceState omap_i2c)
02645926	539	{
60ecfcb3	540	OMAPI2CState *s = OMAP_I2C(omap_i2c);
02645926 AZ	541	return s->bus;
02645926 AZ	542	}
54e17933 JR	543
54e17933 JR	544	type_init(omap_i2c_register_types)