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2055283b PM |
1 | /* |
2 | * ARM Versatile Express emulation. | |
3 | * | |
4 | * Copyright (c) 2010 - 2011 B Labs Ltd. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
6b620ca3 PB |
19 | * |
20 | * Contributions after 2012-01-13 are licensed under the terms of the | |
21 | * GNU GPL, version 2 or (at your option) any later version. | |
2055283b PM |
22 | */ |
23 | ||
12b16722 | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
4771d756 PB |
26 | #include "qemu-common.h" |
27 | #include "cpu.h" | |
83c9f4ca | 28 | #include "hw/sysbus.h" |
bd2be150 | 29 | #include "hw/arm/arm.h" |
0d09e41a | 30 | #include "hw/arm/primecell.h" |
bd2be150 | 31 | #include "hw/devices.h" |
0b724768 | 32 | #include "hw/i2c/i2c.h" |
1422e32d | 33 | #include "net/net.h" |
9c17d615 | 34 | #include "sysemu/sysemu.h" |
83c9f4ca | 35 | #include "hw/boards.h" |
61e99241 | 36 | #include "hw/loader.h" |
022c62cb | 37 | #include "exec/address-spaces.h" |
fa1d36df | 38 | #include "sysemu/block-backend.h" |
0d09e41a | 39 | #include "hw/block/flash.h" |
c8a07b35 | 40 | #include "sysemu/device_tree.h" |
9948c38b | 41 | #include "qemu/error-report.h" |
c8a07b35 | 42 | #include <libfdt.h> |
f0d1d2c1 | 43 | #include "hw/char/pl011.h" |
c2de81e2 PMD |
44 | #include "hw/cpu/a9mpcore.h" |
45 | #include "hw/cpu/a15mpcore.h" | |
2055283b | 46 | |
2055283b | 47 | #define VEXPRESS_BOARD_ID 0x8e0 |
3dc3e7dd FL |
48 | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) |
49 | #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) | |
2055283b | 50 | |
c8a07b35 PM |
51 | /* Number of virtio transports to create (0..8; limited by |
52 | * number of available IRQ lines). | |
53 | */ | |
54 | #define NUM_VIRTIO_TRANSPORTS 4 | |
55 | ||
2558e0a6 PM |
56 | /* Address maps for peripherals: |
57 | * the Versatile Express motherboard has two possible maps, | |
58 | * the "legacy" one (used for A9) and the "Cortex-A Series" | |
59 | * map (used for newer cores). | |
60 | * Individual daughterboards can also have different maps for | |
61 | * their peripherals. | |
62 | */ | |
63 | ||
64 | enum { | |
65 | VE_SYSREGS, | |
66 | VE_SP810, | |
67 | VE_SERIALPCI, | |
68 | VE_PL041, | |
69 | VE_MMCI, | |
70 | VE_KMI0, | |
71 | VE_KMI1, | |
72 | VE_UART0, | |
73 | VE_UART1, | |
74 | VE_UART2, | |
75 | VE_UART3, | |
76 | VE_WDT, | |
77 | VE_TIMER01, | |
78 | VE_TIMER23, | |
79 | VE_SERIALDVI, | |
80 | VE_RTC, | |
81 | VE_COMPACTFLASH, | |
82 | VE_CLCD, | |
83 | VE_NORFLASH0, | |
2558e0a6 | 84 | VE_NORFLASH1, |
8941d6ce | 85 | VE_NORFLASHALIAS, |
2558e0a6 PM |
86 | VE_SRAM, |
87 | VE_VIDEORAM, | |
88 | VE_ETHERNET, | |
89 | VE_USB, | |
90 | VE_DAPROM, | |
c8a07b35 | 91 | VE_VIRTIO, |
2558e0a6 PM |
92 | }; |
93 | ||
a8170e5e | 94 | static hwaddr motherboard_legacy_map[] = { |
6ec1588e | 95 | [VE_NORFLASHALIAS] = 0, |
2558e0a6 PM |
96 | /* CS7: 0x10000000 .. 0x10020000 */ |
97 | [VE_SYSREGS] = 0x10000000, | |
98 | [VE_SP810] = 0x10001000, | |
99 | [VE_SERIALPCI] = 0x10002000, | |
100 | [VE_PL041] = 0x10004000, | |
101 | [VE_MMCI] = 0x10005000, | |
102 | [VE_KMI0] = 0x10006000, | |
103 | [VE_KMI1] = 0x10007000, | |
104 | [VE_UART0] = 0x10009000, | |
105 | [VE_UART1] = 0x1000a000, | |
106 | [VE_UART2] = 0x1000b000, | |
107 | [VE_UART3] = 0x1000c000, | |
108 | [VE_WDT] = 0x1000f000, | |
109 | [VE_TIMER01] = 0x10011000, | |
110 | [VE_TIMER23] = 0x10012000, | |
c8a07b35 | 111 | [VE_VIRTIO] = 0x10013000, |
2558e0a6 PM |
112 | [VE_SERIALDVI] = 0x10016000, |
113 | [VE_RTC] = 0x10017000, | |
114 | [VE_COMPACTFLASH] = 0x1001a000, | |
115 | [VE_CLCD] = 0x1001f000, | |
116 | /* CS0: 0x40000000 .. 0x44000000 */ | |
117 | [VE_NORFLASH0] = 0x40000000, | |
118 | /* CS1: 0x44000000 .. 0x48000000 */ | |
119 | [VE_NORFLASH1] = 0x44000000, | |
120 | /* CS2: 0x48000000 .. 0x4a000000 */ | |
121 | [VE_SRAM] = 0x48000000, | |
122 | /* CS3: 0x4c000000 .. 0x50000000 */ | |
123 | [VE_VIDEORAM] = 0x4c000000, | |
124 | [VE_ETHERNET] = 0x4e000000, | |
125 | [VE_USB] = 0x4f000000, | |
2055283b PM |
126 | }; |
127 | ||
a8170e5e | 128 | static hwaddr motherboard_aseries_map[] = { |
8941d6ce | 129 | [VE_NORFLASHALIAS] = 0, |
661bafb3 FL |
130 | /* CS0: 0x08000000 .. 0x0c000000 */ |
131 | [VE_NORFLASH0] = 0x08000000, | |
961f195e PM |
132 | /* CS4: 0x0c000000 .. 0x10000000 */ |
133 | [VE_NORFLASH1] = 0x0c000000, | |
134 | /* CS5: 0x10000000 .. 0x14000000 */ | |
135 | /* CS1: 0x14000000 .. 0x18000000 */ | |
136 | [VE_SRAM] = 0x14000000, | |
137 | /* CS2: 0x18000000 .. 0x1c000000 */ | |
138 | [VE_VIDEORAM] = 0x18000000, | |
139 | [VE_ETHERNET] = 0x1a000000, | |
140 | [VE_USB] = 0x1b000000, | |
141 | /* CS3: 0x1c000000 .. 0x20000000 */ | |
142 | [VE_DAPROM] = 0x1c000000, | |
143 | [VE_SYSREGS] = 0x1c010000, | |
144 | [VE_SP810] = 0x1c020000, | |
145 | [VE_SERIALPCI] = 0x1c030000, | |
146 | [VE_PL041] = 0x1c040000, | |
147 | [VE_MMCI] = 0x1c050000, | |
148 | [VE_KMI0] = 0x1c060000, | |
149 | [VE_KMI1] = 0x1c070000, | |
150 | [VE_UART0] = 0x1c090000, | |
151 | [VE_UART1] = 0x1c0a0000, | |
152 | [VE_UART2] = 0x1c0b0000, | |
153 | [VE_UART3] = 0x1c0c0000, | |
154 | [VE_WDT] = 0x1c0f0000, | |
155 | [VE_TIMER01] = 0x1c110000, | |
156 | [VE_TIMER23] = 0x1c120000, | |
c8a07b35 | 157 | [VE_VIRTIO] = 0x1c130000, |
961f195e PM |
158 | [VE_SERIALDVI] = 0x1c160000, |
159 | [VE_RTC] = 0x1c170000, | |
160 | [VE_COMPACTFLASH] = 0x1c1a0000, | |
161 | [VE_CLCD] = 0x1c1f0000, | |
162 | }; | |
163 | ||
4c3b29b8 PM |
164 | /* Structure defining the peculiarities of a specific daughterboard */ |
165 | ||
166 | typedef struct VEDBoardInfo VEDBoardInfo; | |
167 | ||
7eb1dc7f GB |
168 | typedef struct { |
169 | MachineClass parent; | |
170 | VEDBoardInfo *daughterboard; | |
171 | } VexpressMachineClass; | |
172 | ||
173 | typedef struct { | |
174 | MachineState parent; | |
49021924 | 175 | bool secure; |
7eb1dc7f GB |
176 | } VexpressMachineState; |
177 | ||
178 | #define TYPE_VEXPRESS_MACHINE "vexpress" | |
98cec76a EH |
179 | #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") |
180 | #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") | |
7eb1dc7f GB |
181 | #define VEXPRESS_MACHINE(obj) \ |
182 | OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) | |
183 | #define VEXPRESS_MACHINE_GET_CLASS(obj) \ | |
184 | OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) | |
185 | #define VEXPRESS_MACHINE_CLASS(klass) \ | |
186 | OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) | |
187 | ||
e364bab6 | 188 | typedef void DBoardInitFn(const VexpressMachineState *machine, |
4c3b29b8 | 189 | ram_addr_t ram_size, |
ba1ba5cc | 190 | const char *cpu_type, |
cdef10bb | 191 | qemu_irq *pic); |
4c3b29b8 PM |
192 | |
193 | struct VEDBoardInfo { | |
cef04a26 | 194 | struct arm_boot_info bootinfo; |
a8170e5e AK |
195 | const hwaddr *motherboard_map; |
196 | hwaddr loader_start; | |
197 | const hwaddr gic_cpu_if_addr; | |
cdef10bb | 198 | uint32_t proc_id; |
31410948 PM |
199 | uint32_t num_voltage_sensors; |
200 | const uint32_t *voltages; | |
9c7d4893 PM |
201 | uint32_t num_clocks; |
202 | const uint32_t *clocks; | |
4c3b29b8 PM |
203 | DBoardInitFn *init; |
204 | }; | |
205 | ||
ba1ba5cc | 206 | static void init_cpus(const char *cpu_type, const char *privdev, |
12d027f1 | 207 | hwaddr periphbase, qemu_irq *pic, bool secure) |
9948c38b | 208 | { |
9948c38b PM |
209 | DeviceState *dev; |
210 | SysBusDevice *busdev; | |
211 | int n; | |
212 | ||
9948c38b PM |
213 | /* Create the actual CPUs */ |
214 | for (n = 0; n < smp_cpus; n++) { | |
ba1ba5cc | 215 | Object *cpuobj = object_new(cpu_type); |
9948c38b | 216 | |
12d027f1 GB |
217 | if (!secure) { |
218 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
219 | } | |
220 | ||
d097696e PM |
221 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { |
222 | object_property_set_int(cpuobj, periphbase, | |
223 | "reset-cbar", &error_abort); | |
9948c38b | 224 | } |
007b0657 | 225 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
9948c38b PM |
226 | } |
227 | ||
228 | /* Create the private peripheral devices (including the GIC); | |
229 | * this must happen after the CPUs are created because a15mpcore_priv | |
230 | * wires itself up to the CPU's generic_timer gpio out lines. | |
231 | */ | |
232 | dev = qdev_create(NULL, privdev); | |
233 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
234 | qdev_init_nofail(dev); | |
235 | busdev = SYS_BUS_DEVICE(dev); | |
236 | sysbus_mmio_map(busdev, 0, periphbase); | |
237 | ||
238 | /* Interrupts [42:0] are from the motherboard; | |
239 | * [47:43] are reserved; [63:48] are daughterboard | |
240 | * peripherals. Note that some documentation numbers | |
241 | * external interrupts starting from 32 (because there | |
242 | * are internal interrupts 0..31). | |
243 | */ | |
244 | for (n = 0; n < 64; n++) { | |
245 | pic[n] = qdev_get_gpio_in(dev, n); | |
246 | } | |
247 | ||
248 | /* Connect the CPUs to the GIC */ | |
249 | for (n = 0; n < smp_cpus; n++) { | |
250 | DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); | |
251 | ||
252 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
27192e39 FA |
253 | sysbus_connect_irq(busdev, n + smp_cpus, |
254 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
9948c38b PM |
255 | } |
256 | } | |
257 | ||
e364bab6 | 258 | static void a9_daughterboard_init(const VexpressMachineState *vms, |
4c3b29b8 | 259 | ram_addr_t ram_size, |
ba1ba5cc | 260 | const char *cpu_type, |
cdef10bb | 261 | qemu_irq *pic) |
2055283b | 262 | { |
e6d17b05 AK |
263 | MemoryRegion *sysmem = get_system_memory(); |
264 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
265 | MemoryRegion *lowram = g_new(MemoryRegion, 1); | |
4c3b29b8 | 266 | ram_addr_t low_ram_size; |
2055283b | 267 | |
2055283b PM |
268 | if (ram_size > 0x40000000) { |
269 | /* 1GB is the maximum the address space permits */ | |
c0dbca36 | 270 | error_report("vexpress-a9: cannot model more than 1GB RAM"); |
2055283b PM |
271 | exit(1); |
272 | } | |
273 | ||
c8623c02 DM |
274 | memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", |
275 | ram_size); | |
2055283b PM |
276 | low_ram_size = ram_size; |
277 | if (low_ram_size > 0x4000000) { | |
278 | low_ram_size = 0x4000000; | |
279 | } | |
280 | /* RAM is from 0x60000000 upwards. The bottom 64MB of the | |
281 | * address space should in theory be remappable to various | |
282 | * things including ROM or RAM; we always map the RAM there. | |
283 | */ | |
2c9b15ca | 284 | memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); |
e6d17b05 AK |
285 | memory_region_add_subregion(sysmem, 0x0, lowram); |
286 | memory_region_add_subregion(sysmem, 0x60000000, ram); | |
2055283b PM |
287 | |
288 | /* 0x1e000000 A9MPCore (SCU) private memory region */ | |
ba1ba5cc | 289 | init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); |
2055283b | 290 | |
4c3b29b8 PM |
291 | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ |
292 | ||
293 | /* 0x10020000 PL111 CLCD (daughterboard) */ | |
294 | sysbus_create_simple("pl111", 0x10020000, pic[44]); | |
295 | ||
296 | /* 0x10060000 AXI RAM */ | |
297 | /* 0x100e0000 PL341 Dynamic Memory Controller */ | |
298 | /* 0x100e1000 PL354 Static Memory Controller */ | |
299 | /* 0x100e2000 System Configuration Controller */ | |
300 | ||
301 | sysbus_create_simple("sp804", 0x100e4000, pic[48]); | |
302 | /* 0x100e5000 SP805 Watchdog module */ | |
303 | /* 0x100e6000 BP147 TrustZone Protection Controller */ | |
304 | /* 0x100e9000 PL301 'Fast' AXI matrix */ | |
305 | /* 0x100ea000 PL301 'Slow' AXI matrix */ | |
306 | /* 0x100ec000 TrustZone Address Space Controller */ | |
307 | /* 0x10200000 CoreSight debug APB */ | |
308 | /* 0x1e00a000 PL310 L2 Cache Controller */ | |
309 | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); | |
310 | } | |
311 | ||
31410948 PM |
312 | /* Voltage values for SYS_CFG_VOLT daughterboard registers; |
313 | * values are in microvolts. | |
314 | */ | |
315 | static const uint32_t a9_voltages[] = { | |
316 | 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ | |
317 | 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ | |
318 | 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ | |
319 | 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ | |
320 | 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ | |
321 | 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ | |
322 | }; | |
323 | ||
9c7d4893 PM |
324 | /* Reset values for daughterboard oscillators (in Hz) */ |
325 | static const uint32_t a9_clocks[] = { | |
326 | 45000000, /* AMBA AXI ACLK: 45MHz */ | |
327 | 23750000, /* daughterboard CLCD clock: 23.75MHz */ | |
328 | 66670000, /* Test chip reference clock: 66.67MHz */ | |
329 | }; | |
330 | ||
cef04a26 | 331 | static VEDBoardInfo a9_daughterboard = { |
4c3b29b8 PM |
332 | .motherboard_map = motherboard_legacy_map, |
333 | .loader_start = 0x60000000, | |
96eacf64 | 334 | .gic_cpu_if_addr = 0x1e000100, |
cdef10bb | 335 | .proc_id = 0x0c000191, |
31410948 PM |
336 | .num_voltage_sensors = ARRAY_SIZE(a9_voltages), |
337 | .voltages = a9_voltages, | |
9c7d4893 PM |
338 | .num_clocks = ARRAY_SIZE(a9_clocks), |
339 | .clocks = a9_clocks, | |
4c3b29b8 PM |
340 | .init = a9_daughterboard_init, |
341 | }; | |
342 | ||
e364bab6 | 343 | static void a15_daughterboard_init(const VexpressMachineState *vms, |
961f195e | 344 | ram_addr_t ram_size, |
ba1ba5cc | 345 | const char *cpu_type, |
cdef10bb | 346 | qemu_irq *pic) |
961f195e | 347 | { |
961f195e PM |
348 | MemoryRegion *sysmem = get_system_memory(); |
349 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
350 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
961f195e | 351 | |
25d71699 PM |
352 | { |
353 | /* We have to use a separate 64 bit variable here to avoid the gcc | |
354 | * "comparison is always false due to limited range of data type" | |
355 | * warning if we are on a host where ram_addr_t is 32 bits. | |
356 | */ | |
357 | uint64_t rsz = ram_size; | |
358 | if (rsz > (30ULL * 1024 * 1024 * 1024)) { | |
c0dbca36 | 359 | error_report("vexpress-a15: cannot model more than 30GB RAM"); |
25d71699 PM |
360 | exit(1); |
361 | } | |
961f195e PM |
362 | } |
363 | ||
c8623c02 DM |
364 | memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", |
365 | ram_size); | |
961f195e PM |
366 | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ |
367 | memory_region_add_subregion(sysmem, 0x80000000, ram); | |
368 | ||
369 | /* 0x2c000000 A15MPCore private memory region (GIC) */ | |
ba1ba5cc | 370 | init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); |
961f195e PM |
371 | |
372 | /* A15 daughterboard peripherals: */ | |
373 | ||
374 | /* 0x20000000: CoreSight interfaces: not modelled */ | |
375 | /* 0x2a000000: PL301 AXI interconnect: not modelled */ | |
376 | /* 0x2a420000: SCC: not modelled */ | |
377 | /* 0x2a430000: system counter: not modelled */ | |
378 | /* 0x2b000000: HDLCD controller: not modelled */ | |
379 | /* 0x2b060000: SP805 watchdog: not modelled */ | |
380 | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ | |
381 | /* 0x2e000000: system SRAM */ | |
98a99ce0 | 382 | memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, |
f8ed85ac | 383 | &error_fatal); |
961f195e PM |
384 | memory_region_add_subregion(sysmem, 0x2e000000, sram); |
385 | ||
386 | /* 0x7ffb0000: DMA330 DMA controller: not modelled */ | |
387 | /* 0x7ffd0000: PL354 static memory controller: not modelled */ | |
388 | } | |
389 | ||
31410948 PM |
390 | static const uint32_t a15_voltages[] = { |
391 | 900000, /* Vcore: 0.9V : CPU core voltage */ | |
392 | }; | |
393 | ||
9c7d4893 PM |
394 | static const uint32_t a15_clocks[] = { |
395 | 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ | |
396 | 0, /* OSCCLK1: reserved */ | |
397 | 0, /* OSCCLK2: reserved */ | |
398 | 0, /* OSCCLK3: reserved */ | |
399 | 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ | |
400 | 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ | |
401 | 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ | |
402 | 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ | |
403 | 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ | |
404 | }; | |
405 | ||
cef04a26 | 406 | static VEDBoardInfo a15_daughterboard = { |
961f195e PM |
407 | .motherboard_map = motherboard_aseries_map, |
408 | .loader_start = 0x80000000, | |
409 | .gic_cpu_if_addr = 0x2c002000, | |
cdef10bb | 410 | .proc_id = 0x14000237, |
31410948 PM |
411 | .num_voltage_sensors = ARRAY_SIZE(a15_voltages), |
412 | .voltages = a15_voltages, | |
9c7d4893 PM |
413 | .num_clocks = ARRAY_SIZE(a15_clocks), |
414 | .clocks = a15_clocks, | |
961f195e PM |
415 | .init = a15_daughterboard_init, |
416 | }; | |
417 | ||
c8a07b35 PM |
418 | static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, |
419 | hwaddr addr, hwaddr size, uint32_t intc, | |
420 | int irq) | |
421 | { | |
422 | /* Add a virtio_mmio node to the device tree blob: | |
423 | * virtio_mmio@ADDRESS { | |
424 | * compatible = "virtio,mmio"; | |
425 | * reg = <ADDRESS, SIZE>; | |
426 | * interrupt-parent = <&intc>; | |
427 | * interrupts = <0, irq, 1>; | |
428 | * } | |
429 | * (Note that the format of the interrupts property is dependent on the | |
430 | * interrupt controller that interrupt-parent points to; these are for | |
431 | * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) | |
432 | */ | |
433 | int rc; | |
434 | char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); | |
435 | ||
5a4348d1 PC |
436 | rc = qemu_fdt_add_subnode(fdt, nodename); |
437 | rc |= qemu_fdt_setprop_string(fdt, nodename, | |
438 | "compatible", "virtio,mmio"); | |
439 | rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", | |
440 | acells, addr, scells, size); | |
441 | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); | |
442 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); | |
054bb7b2 | 443 | qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); |
c8a07b35 PM |
444 | g_free(nodename); |
445 | if (rc) { | |
446 | return -1; | |
447 | } | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static uint32_t find_int_controller(void *fdt) | |
452 | { | |
453 | /* Find the FDT node corresponding to the interrupt controller | |
454 | * for virtio-mmio devices. We do this by scanning the fdt for | |
455 | * a node with the right compatibility, since we know there is | |
456 | * only one GIC on a vexpress board. | |
457 | * We return the phandle of the node, or 0 if none was found. | |
458 | */ | |
459 | const char *compat = "arm,cortex-a9-gic"; | |
460 | int offset; | |
461 | ||
462 | offset = fdt_node_offset_by_compatible(fdt, -1, compat); | |
463 | if (offset >= 0) { | |
464 | return fdt_get_phandle(fdt, offset); | |
465 | } | |
466 | return 0; | |
467 | } | |
468 | ||
469 | static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) | |
470 | { | |
471 | uint32_t acells, scells, intc; | |
472 | const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; | |
473 | ||
58e71097 EA |
474 | acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", |
475 | NULL, &error_fatal); | |
476 | scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", | |
477 | NULL, &error_fatal); | |
c8a07b35 PM |
478 | intc = find_int_controller(fdt); |
479 | if (!intc) { | |
480 | /* Not fatal, we just won't provide virtio. This will | |
481 | * happen with older device tree blobs. | |
482 | */ | |
8297be80 | 483 | warn_report("couldn't find interrupt controller in " |
b62e39b4 | 484 | "dtb; will not include virtio-mmio devices in the dtb"); |
c8a07b35 PM |
485 | } else { |
486 | int i; | |
487 | const hwaddr *map = daughterboard->motherboard_map; | |
488 | ||
489 | /* We iterate backwards here because adding nodes | |
490 | * to the dtb puts them in last-first. | |
491 | */ | |
492 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { | |
493 | add_virtio_mmio_node(fdt, acells, scells, | |
494 | map[VE_VIRTIO] + 0x200 * i, | |
495 | 0x200, intc, 40 + i); | |
496 | } | |
497 | } | |
498 | } | |
499 | ||
b8433303 RF |
500 | |
501 | /* Open code a private version of pflash registration since we | |
502 | * need to set non-default device width for VExpress platform. | |
503 | */ | |
504 | static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, | |
505 | DriveInfo *di) | |
506 | { | |
507 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
508 | ||
9b3d111a MA |
509 | if (di) { |
510 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), | |
511 | &error_abort); | |
b8433303 RF |
512 | } |
513 | ||
514 | qdev_prop_set_uint32(dev, "num-blocks", | |
515 | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); | |
516 | qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); | |
517 | qdev_prop_set_uint8(dev, "width", 4); | |
518 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 519 | qdev_prop_set_bit(dev, "big-endian", false); |
0163a2dc RF |
520 | qdev_prop_set_uint16(dev, "id0", 0x89); |
521 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
b8433303 | 522 | qdev_prop_set_uint16(dev, "id2", 0x00); |
0163a2dc | 523 | qdev_prop_set_uint16(dev, "id3", 0x00); |
b8433303 RF |
524 | qdev_prop_set_string(dev, "name", name); |
525 | qdev_init_nofail(dev); | |
526 | ||
527 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | |
528 | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); | |
529 | } | |
530 | ||
af7c9f34 | 531 | static void vexpress_common_init(MachineState *machine) |
4c3b29b8 | 532 | { |
e364bab6 | 533 | VexpressMachineState *vms = VEXPRESS_MACHINE(machine); |
af7c9f34 | 534 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); |
a8f15a27 | 535 | VEDBoardInfo *daughterboard = vmc->daughterboard; |
4c3b29b8 PM |
536 | DeviceState *dev, *sysctl, *pl041; |
537 | qemu_irq pic[64]; | |
4c3b29b8 | 538 | uint32_t sys_id; |
3dc3e7dd | 539 | DriveInfo *dinfo; |
8941d6ce | 540 | pflash_t *pflash0; |
0b724768 | 541 | I2CBus *i2c; |
4c3b29b8 PM |
542 | ram_addr_t vram_size, sram_size; |
543 | MemoryRegion *sysmem = get_system_memory(); | |
544 | MemoryRegion *vram = g_new(MemoryRegion, 1); | |
545 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
8941d6ce PM |
546 | MemoryRegion *flashalias = g_new(MemoryRegion, 1); |
547 | MemoryRegion *flash0mem; | |
a8170e5e | 548 | const hwaddr *map = daughterboard->motherboard_map; |
31410948 | 549 | int i; |
4c3b29b8 | 550 | |
ba1ba5cc | 551 | daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); |
4c3b29b8 | 552 | |
61e99241 GL |
553 | /* |
554 | * If a bios file was provided, attempt to map it into memory | |
555 | */ | |
556 | if (bios_name) { | |
6e05a12f | 557 | char *fn; |
db25a158 | 558 | int image_size; |
476e75ab PM |
559 | |
560 | if (drive_get(IF_PFLASH, 0, 0)) { | |
561 | error_report("The contents of the first flash device may be " | |
562 | "specified with -bios or with -drive if=pflash... " | |
563 | "but you cannot use both options at once"); | |
564 | exit(1); | |
565 | } | |
566 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
db25a158 SW |
567 | if (!fn) { |
568 | error_report("Could not find ROM image '%s'", bios_name); | |
569 | exit(1); | |
570 | } | |
571 | image_size = load_image_targphys(fn, map[VE_NORFLASH0], | |
572 | VEXPRESS_FLASH_SIZE); | |
573 | g_free(fn); | |
574 | if (image_size < 0) { | |
61e99241 GL |
575 | error_report("Could not load ROM image '%s'", bios_name); |
576 | exit(1); | |
577 | } | |
578 | } | |
579 | ||
2558e0a6 PM |
580 | /* Motherboard peripherals: the wiring is the same but the |
581 | * addresses vary between the legacy and A-Series memory maps. | |
582 | */ | |
583 | ||
2055283b | 584 | sys_id = 0x1190f500; |
2055283b | 585 | |
2055283b PM |
586 | sysctl = qdev_create(NULL, "realview_sysctl"); |
587 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
cdef10bb | 588 | qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); |
31410948 PM |
589 | qdev_prop_set_uint32(sysctl, "len-db-voltage", |
590 | daughterboard->num_voltage_sensors); | |
591 | for (i = 0; i < daughterboard->num_voltage_sensors; i++) { | |
592 | char *propname = g_strdup_printf("db-voltage[%d]", i); | |
593 | qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); | |
594 | g_free(propname); | |
595 | } | |
9c7d4893 PM |
596 | qdev_prop_set_uint32(sysctl, "len-db-clock", |
597 | daughterboard->num_clocks); | |
598 | for (i = 0; i < daughterboard->num_clocks; i++) { | |
599 | char *propname = g_strdup_printf("db-clock[%d]", i); | |
600 | qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); | |
601 | g_free(propname); | |
602 | } | |
7a65c8cc | 603 | qdev_init_nofail(sysctl); |
1356b98d | 604 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); |
2558e0a6 PM |
605 | |
606 | /* VE_SP810: not modelled */ | |
607 | /* VE_SERIALPCI: not modelled */ | |
2055283b | 608 | |
03a0e944 PM |
609 | pl041 = qdev_create(NULL, "pl041"); |
610 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
611 | qdev_init_nofail(pl041); | |
1356b98d AF |
612 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); |
613 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); | |
2055283b | 614 | |
2558e0a6 | 615 | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
2055283b PM |
616 | /* Wire up MMC card detect and read-only signals */ |
617 | qdev_connect_gpio_out(dev, 0, | |
618 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); | |
619 | qdev_connect_gpio_out(dev, 1, | |
620 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); | |
621 | ||
2558e0a6 PM |
622 | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
623 | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); | |
2055283b | 624 | |
9bca0edb PM |
625 | pl011_create(map[VE_UART0], pic[5], serial_hd(0)); |
626 | pl011_create(map[VE_UART1], pic[6], serial_hd(1)); | |
627 | pl011_create(map[VE_UART2], pic[7], serial_hd(2)); | |
628 | pl011_create(map[VE_UART3], pic[8], serial_hd(3)); | |
2055283b | 629 | |
2558e0a6 PM |
630 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
631 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); | |
2055283b | 632 | |
0b724768 LW |
633 | dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL); |
634 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | |
635 | i2c_create_slave(i2c, "sii9022", 0x39); | |
2055283b | 636 | |
2558e0a6 | 637 | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
2055283b | 638 | |
2558e0a6 | 639 | /* VE_COMPACTFLASH: not modelled */ |
2055283b | 640 | |
b7206878 | 641 | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
2055283b | 642 | |
3dc3e7dd | 643 | dinfo = drive_get_next(IF_PFLASH); |
b8433303 RF |
644 | pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", |
645 | dinfo); | |
8941d6ce | 646 | if (!pflash0) { |
c0dbca36 | 647 | error_report("vexpress: error registering flash 0"); |
3dc3e7dd FL |
648 | exit(1); |
649 | } | |
650 | ||
8941d6ce PM |
651 | if (map[VE_NORFLASHALIAS] != -1) { |
652 | /* Map flash 0 as an alias into low memory */ | |
653 | flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); | |
654 | memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", | |
655 | flash0mem, 0, VEXPRESS_FLASH_SIZE); | |
656 | memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); | |
657 | } | |
658 | ||
3dc3e7dd | 659 | dinfo = drive_get_next(IF_PFLASH); |
b8433303 RF |
660 | if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", |
661 | dinfo)) { | |
c0dbca36 | 662 | error_report("vexpress: error registering flash 1"); |
3dc3e7dd FL |
663 | exit(1); |
664 | } | |
2558e0a6 | 665 | |
2055283b | 666 | sram_size = 0x2000000; |
98a99ce0 | 667 | memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, |
f8ed85ac | 668 | &error_fatal); |
2558e0a6 | 669 | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
2055283b | 670 | |
2055283b | 671 | vram_size = 0x800000; |
98a99ce0 | 672 | memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, |
f8ed85ac | 673 | &error_fatal); |
2558e0a6 | 674 | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
2055283b PM |
675 | |
676 | /* 0x4e000000 LAN9118 Ethernet */ | |
a005d073 | 677 | if (nd_table[0].used) { |
2558e0a6 | 678 | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
2055283b PM |
679 | } |
680 | ||
2558e0a6 PM |
681 | /* VE_USB: not modelled */ |
682 | ||
683 | /* VE_DAPROM: not modelled */ | |
2055283b | 684 | |
c8a07b35 PM |
685 | /* Create mmio transports, so the user can create virtio backends |
686 | * (which will be automatically plugged in to the transports). If | |
687 | * no backend is created the transport will just sit harmlessly idle. | |
688 | */ | |
689 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
690 | sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, | |
691 | pic[40 + i]); | |
692 | } | |
693 | ||
3ef96221 MA |
694 | daughterboard->bootinfo.ram_size = machine->ram_size; |
695 | daughterboard->bootinfo.kernel_filename = machine->kernel_filename; | |
696 | daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
697 | daughterboard->bootinfo.initrd_filename = machine->initrd_filename; | |
cef04a26 PM |
698 | daughterboard->bootinfo.nb_cpus = smp_cpus; |
699 | daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; | |
700 | daughterboard->bootinfo.loader_start = daughterboard->loader_start; | |
701 | daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; | |
702 | daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; | |
703 | daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; | |
c8a07b35 | 704 | daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; |
12d027f1 GB |
705 | /* Indicate that when booting Linux we should be in secure state */ |
706 | daughterboard->bootinfo.secure_boot = true; | |
cef04a26 | 707 | arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); |
2055283b PM |
708 | } |
709 | ||
49021924 GB |
710 | static bool vexpress_get_secure(Object *obj, Error **errp) |
711 | { | |
712 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); | |
713 | ||
714 | return vms->secure; | |
715 | } | |
716 | ||
717 | static void vexpress_set_secure(Object *obj, bool value, Error **errp) | |
718 | { | |
719 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); | |
720 | ||
721 | vms->secure = value; | |
722 | } | |
723 | ||
724 | static void vexpress_instance_init(Object *obj) | |
725 | { | |
726 | VexpressMachineState *vms = VEXPRESS_MACHINE(obj); | |
727 | ||
728 | /* EL3 is enabled by default on vexpress */ | |
729 | vms->secure = true; | |
730 | object_property_add_bool(obj, "secure", vexpress_get_secure, | |
731 | vexpress_set_secure, NULL); | |
732 | object_property_set_description(obj, "secure", | |
733 | "Set on/off to enable/disable the ARM " | |
734 | "Security Extensions (TrustZone)", | |
735 | NULL); | |
736 | } | |
737 | ||
7eb1dc7f GB |
738 | static void vexpress_class_init(ObjectClass *oc, void *data) |
739 | { | |
740 | MachineClass *mc = MACHINE_CLASS(oc); | |
741 | ||
7eb1dc7f | 742 | mc->desc = "ARM Versatile Express"; |
af7c9f34 | 743 | mc->init = vexpress_common_init; |
7eb1dc7f | 744 | mc->max_cpus = 4; |
4672cbd7 | 745 | mc->ignore_memory_transaction_failures = true; |
7eb1dc7f GB |
746 | } |
747 | ||
9ee00ba8 GB |
748 | static void vexpress_a9_class_init(ObjectClass *oc, void *data) |
749 | { | |
750 | MachineClass *mc = MACHINE_CLASS(oc); | |
751 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); | |
752 | ||
9ee00ba8 | 753 | mc->desc = "ARM Versatile Express for Cortex-A9"; |
ba1ba5cc | 754 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
9ee00ba8 | 755 | |
a8f15a27 | 756 | vmc->daughterboard = &a9_daughterboard; |
9ee00ba8 GB |
757 | } |
758 | ||
759 | static void vexpress_a15_class_init(ObjectClass *oc, void *data) | |
760 | { | |
761 | MachineClass *mc = MACHINE_CLASS(oc); | |
762 | VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); | |
763 | ||
9ee00ba8 | 764 | mc->desc = "ARM Versatile Express for Cortex-A15"; |
ba1ba5cc | 765 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
9ee00ba8 GB |
766 | |
767 | vmc->daughterboard = &a15_daughterboard; | |
768 | } | |
769 | ||
7eb1dc7f GB |
770 | static const TypeInfo vexpress_info = { |
771 | .name = TYPE_VEXPRESS_MACHINE, | |
772 | .parent = TYPE_MACHINE, | |
773 | .abstract = true, | |
774 | .instance_size = sizeof(VexpressMachineState), | |
49021924 | 775 | .instance_init = vexpress_instance_init, |
7eb1dc7f GB |
776 | .class_size = sizeof(VexpressMachineClass), |
777 | .class_init = vexpress_class_init, | |
778 | }; | |
779 | ||
9ee00ba8 GB |
780 | static const TypeInfo vexpress_a9_info = { |
781 | .name = TYPE_VEXPRESS_A9_MACHINE, | |
782 | .parent = TYPE_VEXPRESS_MACHINE, | |
783 | .class_init = vexpress_a9_class_init, | |
2055283b PM |
784 | }; |
785 | ||
9ee00ba8 GB |
786 | static const TypeInfo vexpress_a15_info = { |
787 | .name = TYPE_VEXPRESS_A15_MACHINE, | |
788 | .parent = TYPE_VEXPRESS_MACHINE, | |
789 | .class_init = vexpress_a15_class_init, | |
961f195e PM |
790 | }; |
791 | ||
2055283b PM |
792 | static void vexpress_machine_init(void) |
793 | { | |
7eb1dc7f | 794 | type_register_static(&vexpress_info); |
9ee00ba8 GB |
795 | type_register_static(&vexpress_a9_info); |
796 | type_register_static(&vexpress_a15_info); | |
2055283b PM |
797 | } |
798 | ||
0e6aac87 | 799 | type_init(vexpress_machine_init); |