[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

struct SerialState {
    uint16_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr; /* read only */
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    qemu_irq irq;
    CharDriverState *chr;
    int last_break_enable;
    target_phys_addr_t base;
    int it_shift;
};

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static void serial_update_parameters(SerialState *s)
{
    int speed, parity, data_bits, stop_bits;
    QEMUSerialSetParams ssp;

    if (s->lcr & 0x08) {
        if (s->lcr & 0x10)
            parity = 'E';
        else
            parity = 'O';
    } else {
            parity = 'N';
    }
    if (s->lcr & 0x04)
        stop_bits = 2;
    else
        stop_bits = 1;
    data_bits = (s->lcr & 0x03) + 5;
    if (s->divider == 0)
        return;
    speed = 115200 / s->divider;
    ssp.speed = speed;
    ssp.parity = parity;
    ssp.data_bits = data_bits;
    ssp.stop_bits = stop_bits;
    qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
    printf("speed=%d parity=%c data=%d stop=%d\n",
           speed, parity, data_bits, stop_bits);
#endif
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;
   
    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
            serial_update_parameters(s);
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
            serial_update_parameters(s);
        } else {
            s->ier = val & 0x0f;
            if (s->lsr & UART_LSR_THRE) {
                s->thr_ipending = 1;
            }
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        {
            int break_enable;
            s->lcr = val;
            serial_update_parameters(s);
            break_enable = (val >> 6) & 1;
            if (break_enable != s->last_break_enable) {
                s->last_break_enable = break_enable;
                qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
                               &break_enable);
            }
        }
        break;
    case 4:
        s->mcr = val & 0x1f;
        break;
    case 5:
        break;
    case 6:
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff;
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

static void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

static void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

static void serial_event(void *opaque, int event)
{
    SerialState *s = opaque;
    if (event == CHR_EVENT_BREAK)
        serial_receive_break(s);
}

static void serial_save(QEMUFile *f, void *opaque)
{
    SerialState *s = opaque;

    qemu_put_be16s(f,&s->divider);
    qemu_put_8s(f,&s->rbr);
    qemu_put_8s(f,&s->ier);
    qemu_put_8s(f,&s->iir);
    qemu_put_8s(f,&s->lcr);
    qemu_put_8s(f,&s->mcr);
    qemu_put_8s(f,&s->lsr);
    qemu_put_8s(f,&s->msr);
    qemu_put_8s(f,&s->scr);
}

static int serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SerialState *s = opaque;

    if(version_id > 2)
        return -EINVAL;

    if (version_id >= 2)
        qemu_get_be16s(f, &s->divider);
    else
        s->divider = qemu_get_byte(f);
    qemu_get_8s(f,&s->rbr);
    qemu_get_8s(f,&s->ier);
    qemu_get_8s(f,&s->iir);
    qemu_get_8s(f,&s->lcr);
    qemu_get_8s(f,&s->mcr);
    qemu_get_8s(f,&s->lsr);
    qemu_get_8s(f,&s->msr);
    qemu_get_8s(f,&s->scr);

    return 0;
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}

/* Memory mapped interface */
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

void serial_mm_writeb (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

void serial_mm_writew (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

void serial_mm_writel (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *serial_mm_read[] = {
    &serial_mm_readb,
    &serial_mm_readw,
    &serial_mm_readl,
};

static CPUWriteMemoryFunc *serial_mm_write[] = {
    &serial_mm_writeb,
    &serial_mm_writew,
    &serial_mm_writel,
};

SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, CharDriverState *chr,
                             int ioregister)
{
    SerialState *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    s->base = base;
    s->it_shift = it_shift;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    if (ioregister) {
        s_io_memory = cpu_register_io_memory(0, serial_mm_read,
                                             serial_mm_write, s);
        cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
    }
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 16450 UART emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	//#define DEBUG_SERIAL
	27
	28	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	29
	30	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	31	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	32	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	33	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	34
	35	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	36	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	37
	38	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	39	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	40	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	41	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	42
	43	/*
	44	* These are the definitions for the Modem Control Register
	45	*/
	46	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	47	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	48	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	49	#define UART_MCR_RTS 0x02 /* RTS complement */
	50	#define UART_MCR_DTR 0x01 /* DTR complement */
	51
	52	/*
	53	* These are the definitions for the Modem Status Register
	54	*/
	55	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	56	#define UART_MSR_RI 0x40 /* Ring Indicator */
	57	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	58	#define UART_MSR_CTS 0x10 /* Clear to Send */
	59	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	60	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	61	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	62	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	63	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	64
	65	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	66	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	67	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	68	#define UART_LSR_FE 0x08 /* Frame error indicator */
	69	#define UART_LSR_PE 0x04 /* Parity error indicator */
	70	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	71	#define UART_LSR_DR 0x01 /* Receiver data ready */
	72
b41a2cd1	73	struct SerialState {
508d92d0	74	uint16_t divider;
80cabfad FB	75	uint8_t rbr; /* receive register */
	76	uint8_t ier;
	77	uint8_t iir; /* read only */
	78	uint8_t lcr;
	79	uint8_t mcr;
	80	uint8_t lsr; /* read only */
3e749fe1	81	uint8_t msr; /* read only */
80cabfad FB	82	uint8_t scr;
	83	/* NOTE: this hidden state is necessary for tx irq generation as
	84	it can be reset while reading iir */
	85	int thr_ipending;
d537cf6c	86	qemu_irq irq;
82c643ff	87	CharDriverState *chr;
f8d179e3	88	int last_break_enable;
71db710f	89	target_phys_addr_t base;
e5d13e2f	90	int it_shift;
b41a2cd1	91	};
80cabfad	92
b41a2cd1	93	static void serial_update_irq(SerialState *s)
80cabfad	94	{
80cabfad FB	95	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	96	s->iir = UART_IIR_RDI;
	97	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	98	s->iir = UART_IIR_THRI;
	99	} else {
	100	s->iir = UART_IIR_NO_INT;
	101	}
	102	if (s->iir != UART_IIR_NO_INT) {
d537cf6c	103	qemu_irq_raise(s->irq);
80cabfad	104	} else {
d537cf6c	105	qemu_irq_lower(s->irq);
80cabfad FB	106	}
	107	}
	108
f8d179e3 FB	109	static void serial_update_parameters(SerialState *s)
	110	{
	111	int speed, parity, data_bits, stop_bits;
2122c51a	112	QEMUSerialSetParams ssp;
f8d179e3 FB	113
	114	if (s->lcr & 0x08) {
	115	if (s->lcr & 0x10)
	116	parity = 'E';
	117	else
	118	parity = 'O';
	119	} else {
	120	parity = 'N';
	121	}
5fafdf24	122	if (s->lcr & 0x04)
f8d179e3 FB	123	stop_bits = 2;
	124	else
	125	stop_bits = 1;
	126	data_bits = (s->lcr & 0x03) + 5;
	127	if (s->divider == 0)
	128	return;
	129	speed = 115200 / s->divider;
2122c51a FB	130	ssp.speed = speed;
	131	ssp.parity = parity;
	132	ssp.data_bits = data_bits;
	133	ssp.stop_bits = stop_bits;
	134	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
	135	#if 0
5fafdf24	136	printf("speed=%d parity=%c data=%d stop=%d\n",
f8d179e3 FB	137	speed, parity, data_bits, stop_bits);
	138	#endif
	139	}
	140
b41a2cd1	141	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	142	{
b41a2cd1	143	SerialState *s = opaque;
80cabfad	144	unsigned char ch;
5fafdf24	145
80cabfad FB	146	addr &= 7;
	147	#ifdef DEBUG_SERIAL
	148	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	149	#endif
	150	switch(addr) {
	151	default:
	152	case 0:
	153	if (s->lcr & UART_LCR_DLAB) {
	154	s->divider = (s->divider & 0xff00) \| val;
f8d179e3	155	serial_update_parameters(s);
80cabfad FB	156	} else {
	157	s->thr_ipending = 0;
	158	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	159	serial_update_irq(s);
82c643ff FB	160	ch = val;
82c643ff FB	161	qemu_chr_write(s->chr, &ch, 1);
80cabfad FB	162	s->thr_ipending = 1;
	163	s->lsr \|= UART_LSR_THRE;
	164	s->lsr \|= UART_LSR_TEMT;
b41a2cd1	165	serial_update_irq(s);
80cabfad FB	166	}
	167	break;
	168	case 1:
	169	if (s->lcr & UART_LCR_DLAB) {
	170	s->divider = (s->divider & 0x00ff) \| (val << 8);
f8d179e3	171	serial_update_parameters(s);
80cabfad	172	} else {
60e336db FB	173	s->ier = val & 0x0f;
	174	if (s->lsr & UART_LSR_THRE) {
	175	s->thr_ipending = 1;
	176	}
b41a2cd1	177	serial_update_irq(s);
80cabfad FB	178	}
	179	break;
	180	case 2:
	181	break;
	182	case 3:
f8d179e3 FB	183	{
	184	int break_enable;
	185	s->lcr = val;
	186	serial_update_parameters(s);
	187	break_enable = (val >> 6) & 1;
	188	if (break_enable != s->last_break_enable) {
	189	s->last_break_enable = break_enable;
5fafdf24	190	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
2122c51a	191	&break_enable);
f8d179e3 FB	192	}
f8d179e3 FB	193	}
80cabfad FB	194	break;
80cabfad FB	195	case 4:
60e336db	196	s->mcr = val & 0x1f;
80cabfad FB	197	break;
	198	case 5:
	199	break;
	200	case 6:
80cabfad FB	201	break;
	202	case 7:
	203	s->scr = val;
	204	break;
	205	}
	206	}
	207
b41a2cd1	208	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	209	{
b41a2cd1	210	SerialState *s = opaque;
80cabfad FB	211	uint32_t ret;
	212
	213	addr &= 7;
	214	switch(addr) {
	215	default:
	216	case 0:
	217	if (s->lcr & UART_LCR_DLAB) {
5fafdf24	218	ret = s->divider & 0xff;
80cabfad FB	219	} else {
	220	ret = s->rbr;
	221	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	222	serial_update_irq(s);
80cabfad FB	223	}
	224	break;
	225	case 1:
	226	if (s->lcr & UART_LCR_DLAB) {
	227	ret = (s->divider >> 8) & 0xff;
	228	} else {
	229	ret = s->ier;
	230	}
	231	break;
	232	case 2:
	233	ret = s->iir;
	234	/* reset THR pending bit */
	235	if ((ret & 0x7) == UART_IIR_THRI)
	236	s->thr_ipending = 0;
b41a2cd1	237	serial_update_irq(s);
80cabfad FB	238	break;
	239	case 3:
	240	ret = s->lcr;
	241	break;
	242	case 4:
	243	ret = s->mcr;
	244	break;
	245	case 5:
	246	ret = s->lsr;
	247	break;
	248	case 6:
	249	if (s->mcr & UART_MCR_LOOP) {
	250	/* in loopback, the modem output pins are connected to the
	251	inputs */
	252	ret = (s->mcr & 0x0c) << 4;
	253	ret \|= (s->mcr & 0x02) << 3;
	254	ret \|= (s->mcr & 0x01) << 5;
	255	} else {
	256	ret = s->msr;
	257	}
	258	break;
	259	case 7:
	260	ret = s->scr;
	261	break;
	262	}
	263	#ifdef DEBUG_SERIAL
	264	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	265	#endif
	266	return ret;
	267	}
	268
82c643ff	269	static int serial_can_receive(SerialState *s)
80cabfad	270	{
80cabfad FB	271	return !(s->lsr & UART_LSR_DR);
	272	}
	273
82c643ff	274	static void serial_receive_byte(SerialState *s, int ch)
80cabfad	275	{
80cabfad FB	276	s->rbr = ch;
80cabfad FB	277	s->lsr \|= UART_LSR_DR;
b41a2cd1	278	serial_update_irq(s);
80cabfad FB	279	}
80cabfad FB	280
82c643ff	281	static void serial_receive_break(SerialState *s)
80cabfad	282	{
80cabfad FB	283	s->rbr = 0;
80cabfad FB	284	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	285	serial_update_irq(s);
80cabfad FB	286	}
80cabfad FB	287
b41a2cd1	288	static int serial_can_receive1(void *opaque)
80cabfad	289	{
b41a2cd1 FB	290	SerialState *s = opaque;
	291	return serial_can_receive(s);
	292	}
	293
	294	static void serial_receive1(void opaque, const uint8_t buf, int size)
	295	{
	296	SerialState *s = opaque;
	297	serial_receive_byte(s, buf[0]);
	298	}
80cabfad	299
82c643ff FB	300	static void serial_event(void *opaque, int event)
	301	{
	302	SerialState *s = opaque;
	303	if (event == CHR_EVENT_BREAK)
	304	serial_receive_break(s);
	305	}
	306
8738a8d0 FB	307	static void serial_save(QEMUFile f, void opaque)
	308	{
	309	SerialState *s = opaque;
	310
508d92d0	311	qemu_put_be16s(f,&s->divider);
8738a8d0 FB	312	qemu_put_8s(f,&s->rbr);
	313	qemu_put_8s(f,&s->ier);
	314	qemu_put_8s(f,&s->iir);
	315	qemu_put_8s(f,&s->lcr);
	316	qemu_put_8s(f,&s->mcr);
	317	qemu_put_8s(f,&s->lsr);
	318	qemu_put_8s(f,&s->msr);
	319	qemu_put_8s(f,&s->scr);
	320	}
	321
	322	static int serial_load(QEMUFile f, void opaque, int version_id)
	323	{
	324	SerialState *s = opaque;
	325
508d92d0	326	if(version_id > 2)
8738a8d0 FB	327	return -EINVAL;
8738a8d0 FB	328
508d92d0 FB	329	if (version_id >= 2)
	330	qemu_get_be16s(f, &s->divider);
	331	else
	332	s->divider = qemu_get_byte(f);
8738a8d0 FB	333	qemu_get_8s(f,&s->rbr);
	334	qemu_get_8s(f,&s->ier);
	335	qemu_get_8s(f,&s->iir);
	336	qemu_get_8s(f,&s->lcr);
	337	qemu_get_8s(f,&s->mcr);
	338	qemu_get_8s(f,&s->lsr);
	339	qemu_get_8s(f,&s->msr);
	340	qemu_get_8s(f,&s->scr);
	341
	342	return 0;
	343	}
	344
b41a2cd1	345	/* If fd is zero, it means that the serial device uses the console */
d537cf6c	346	SerialState serial_init(int base, qemu_irq irq, CharDriverState chr)
b41a2cd1 FB	347	{
	348	SerialState *s;
	349
	350	s = qemu_mallocz(sizeof(SerialState));
	351	if (!s)
	352	return NULL;
80cabfad FB	353	s->irq = irq;
	354	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	355	s->iir = UART_IIR_NO_INT;
3e749fe1	356	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
b41a2cd1	357
508d92d0	358	register_savevm("serial", base, 2, serial_save, serial_load, s);
8738a8d0	359
b41a2cd1 FB	360	register_ioport_write(base, 8, 1, serial_ioport_write, s);
b41a2cd1 FB	361	register_ioport_read(base, 8, 1, serial_ioport_read, s);
82c643ff	362	s->chr = chr;
e5b0bc44 PB	363	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	364	serial_event, s);
b41a2cd1	365	return s;
80cabfad	366	}
e5d13e2f FB	367
e5d13e2f FB	368	/* Memory mapped interface */
a4bc3afc	369	uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	370	{
	371	SerialState *s = opaque;
	372
	373	return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
	374	}
	375
a4bc3afc TS	376	void serial_mm_writeb (void *opaque,
a4bc3afc TS	377	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	378	{
	379	SerialState *s = opaque;
	380
	381	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	382	}
	383
a4bc3afc	384	uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	385	{
e5d13e2f FB	386	SerialState *s = opaque;
e918ee04	387	uint32_t val;
e5d13e2f	388
e918ee04 TS	389	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	390	#ifdef TARGET_WORDS_BIGENDIAN
	391	val = bswap16(val);
	392	#endif
	393	return val;
e5d13e2f FB	394	}
e5d13e2f FB	395
a4bc3afc TS	396	void serial_mm_writew (void *opaque,
a4bc3afc TS	397	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	398	{
e5d13e2f FB	399	SerialState *s = opaque;
e918ee04 TS	400	#ifdef TARGET_WORDS_BIGENDIAN
	401	value = bswap16(value);
	402	#endif
e5d13e2f FB	403	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	404	}
	405
a4bc3afc	406	uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	407	{
e5d13e2f FB	408	SerialState *s = opaque;
e918ee04	409	uint32_t val;
e5d13e2f	410
e918ee04 TS	411	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
	412	#ifdef TARGET_WORDS_BIGENDIAN
	413	val = bswap32(val);
	414	#endif
	415	return val;
e5d13e2f FB	416	}
e5d13e2f FB	417
a4bc3afc TS	418	void serial_mm_writel (void *opaque,
a4bc3afc TS	419	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	420	{
e5d13e2f FB	421	SerialState *s = opaque;
e918ee04 TS	422	#ifdef TARGET_WORDS_BIGENDIAN
	423	value = bswap32(value);
	424	#endif
e5d13e2f FB	425	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
	426	}
	427
	428	static CPUReadMemoryFunc *serial_mm_read[] = {
	429	&serial_mm_readb,
	430	&serial_mm_readw,
	431	&serial_mm_readl,
	432	};
	433
	434	static CPUWriteMemoryFunc *serial_mm_write[] = {
	435	&serial_mm_writeb,
	436	&serial_mm_writew,
	437	&serial_mm_writel,
	438	};
	439
71db710f	440	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
d537cf6c	441	qemu_irq irq, CharDriverState *chr,
a4bc3afc	442	int ioregister)
e5d13e2f FB	443	{
	444	SerialState *s;
	445	int s_io_memory;
	446
	447	s = qemu_mallocz(sizeof(SerialState));
	448	if (!s)
	449	return NULL;
e5d13e2f FB	450	s->irq = irq;
	451	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	452	s->iir = UART_IIR_NO_INT;
3e749fe1	453	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
e5d13e2f FB	454	s->base = base;
	455	s->it_shift = it_shift;
	456
508d92d0	457	register_savevm("serial", base, 2, serial_save, serial_load, s);
e5d13e2f	458
a4bc3afc TS	459	if (ioregister) {
	460	s_io_memory = cpu_register_io_memory(0, serial_mm_read,
	461	serial_mm_write, s);
	462	cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
	463	}
e5d13e2f	464	s->chr = chr;
e5b0bc44 PB	465	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	466	serial_event, s);
e5d13e2f FB	467	return s;
e5d13e2f FB	468	}