[qemu.git] / hw / i8254.c

/*
 * QEMU 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PIT

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

typedef struct PITChannelState {
    int count; /* can be 65536 */
    uint16_t latched_count;
    uint8_t count_latched;
    uint8_t status_latched;
    uint8_t status;
    uint8_t read_state;
    uint8_t write_state;
    uint8_t write_latch;
    uint8_t rw_mode;
    uint8_t mode;
    uint8_t bcd; /* not supported */
    uint8_t gate; /* timer start */
    int64_t count_load_time;
    /* irq handling */
    int64_t next_transition_time;
    QEMUTimer *irq_timer;
    qemu_irq irq;
} PITChannelState;

struct PITState {
    PITChannelState channels[3];
};

static PITState pit_state;

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);

static int pit_get_count(PITChannelState *s)
{
    uint64_t d;
    int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    case 0:
    case 1:
    case 4:
    case 5:
        counter = (s->count - d) & 0xffff;
        break;
    case 3:
        /* XXX: may be incorrect for odd counts */
        counter = s->count - ((2 * d) % s->count);
        break;
    default:
        counter = s->count - (d % s->count);
        break;
    }
    return counter;
}

/* get pit output bit */
static int pit_get_out1(PITChannelState *s, int64_t current_time)
{
    uint64_t d;
    int out;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    default:
    case 0:
        out = (d >= s->count);
        break;
    case 1:
        out = (d < s->count);
        break;
    case 2:
        if ((d % s->count) == 0 && d != 0)
            out = 1;
        else
            out = 0;
        break;
    case 3:
        out = (d % s->count) < ((s->count + 1) >> 1);
        break;
    case 4:
    case 5:
        out = (d == s->count);
        break;
    }
    return out;
}

int pit_get_out(PITState *pit, int channel, int64_t current_time)
{
    PITChannelState *s = &pit->channels[channel];
    return pit_get_out1(s, current_time);
}

/* return -1 if no transition will occur.  */
static int64_t pit_get_next_transition_time(PITChannelState *s,
                                            int64_t current_time)
{
    uint64_t d, next_time, base;
    int period2;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    default:
    case 0:
    case 1:
        if (d < s->count)
            next_time = s->count;
        else
            return -1;
        break;
    case 2:
        base = (d / s->count) * s->count;
        if ((d - base) == 0 && d != 0)
            next_time = base + s->count;
        else
            next_time = base + s->count + 1;
        break;
    case 3:
        base = (d / s->count) * s->count;
        period2 = ((s->count + 1) >> 1);
        if ((d - base) < period2)
            next_time = base + period2;
        else
            next_time = base + s->count;
        break;
    case 4:
    case 5:
        if (d < s->count)
            next_time = s->count;
        else if (d == s->count)
            next_time = s->count + 1;
        else
            return -1;
        break;
    }
    /* convert to timer units */
    next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
    /* fix potential rounding problems */
    /* XXX: better solution: use a clock at PIT_FREQ Hz */
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

/* val must be 0 or 1 */
void pit_set_gate(PITState *pit, int channel, int val)
{
    PITChannelState *s = &pit->channels[channel];

    switch(s->mode) {
    default:
    case 0:
    case 4:
        /* XXX: just disable/enable counting */
        break;
    case 1:
    case 5:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        break;
    case 2:
    case 3:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        /* XXX: disable/enable counting */
        break;
    }
    s->gate = val;
}

int pit_get_gate(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->gate;
}

int pit_get_initial_count(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->count;
}

int pit_get_mode(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->mode;
}

static inline void pit_load_count(PITChannelState *s, int val)
{
    if (val == 0)
        val = 0x10000;
    s->count_load_time = qemu_get_clock(vm_clock);
    s->count = val;
    pit_irq_timer_update(s, s->count_load_time);
}

/* if already latched, do not latch again */
static void pit_latch_count(PITChannelState *s)
{
    if (!s->count_latched) {
        s->latched_count = pit_get_count(s);
        s->count_latched = s->rw_mode;
    }
}

static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PITState *pit = opaque;
    int channel, access;
    PITChannelState *s;

    addr &= 3;
    if (addr == 3) {
        channel = val >> 6;
        if (channel == 3) {
            /* read back command */
            for(channel = 0; channel < 3; channel++) {
                s = &pit->channels[channel];
                if (val & (2 << channel)) {
                    if (!(val & 0x20)) {
                        pit_latch_count(s);
                    }
                    if (!(val & 0x10) && !s->status_latched) {
                        /* status latch */
                        /* XXX: add BCD and null count */
                        s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
                            (s->rw_mode << 4) |
                            (s->mode << 1) |
                            s->bcd;
                        s->status_latched = 1;
                    }
                }
            }
        } else {
            s = &pit->channels[channel];
            access = (val >> 4) & 3;
            if (access == 0) {
                pit_latch_count(s);
            } else {
                s->rw_mode = access;
                s->read_state = access;
                s->write_state = access;

                s->mode = (val >> 1) & 7;
                s->bcd = val & 1;
                /* XXX: update irq timer ? */
            }
        }
    } else {
        s = &pit->channels[addr];
        switch(s->write_state) {
        default:
        case RW_STATE_LSB:
            pit_load_count(s, val);
            break;
        case RW_STATE_MSB:
            pit_load_count(s, val << 8);
            break;
        case RW_STATE_WORD0:
            s->write_latch = val;
            s->write_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            pit_load_count(s, s->write_latch | (val << 8));
            s->write_state = RW_STATE_WORD0;
            break;
        }
    }
}

static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
{
    PITState *pit = opaque;
    int ret, count;
    PITChannelState *s;
   
    addr &= 3;
    s = &pit->channels[addr];
    if (s->status_latched) {
        s->status_latched = 0;
        ret = s->status;
    } else if (s->count_latched) {
        switch(s->count_latched) {
        default:
        case RW_STATE_LSB:
            ret = s->latched_count & 0xff;
            s->count_latched = 0;
            break;
        case RW_STATE_MSB:
            ret = s->latched_count >> 8;
            s->count_latched = 0;
            break;
        case RW_STATE_WORD0:
            ret = s->latched_count & 0xff;
            s->count_latched = RW_STATE_MSB;
            break;
        }
    } else {
        switch(s->read_state) {
        default:
        case RW_STATE_LSB:
            count = pit_get_count(s);
            ret = count & 0xff;
            break;
        case RW_STATE_MSB:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            break;
        case RW_STATE_WORD0:
            count = pit_get_count(s);
            ret = count & 0xff;
            s->read_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            s->read_state = RW_STATE_WORD0;
            break;
        }
    }
    return ret;
}

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
{
    int64_t expire_time;
    int irq_level;

    if (!s->irq_timer)
        return;
    expire_time = pit_get_next_transition_time(s, current_time);
    irq_level = pit_get_out1(s, current_time);
    qemu_set_irq(s->irq, irq_level);
#ifdef DEBUG_PIT
    printf("irq_level=%d next_delay=%f\n",
           irq_level,
           (double)(expire_time - current_time) / ticks_per_sec);
#endif
    s->next_transition_time = expire_time;
    if (expire_time != -1)
        qemu_mod_timer(s->irq_timer, expire_time);
    else
        qemu_del_timer(s->irq_timer);
}

static void pit_irq_timer(void *opaque)
{
    PITChannelState *s = opaque;

    pit_irq_timer_update(s, s->next_transition_time);
}

static void pit_save(QEMUFile *f, void *opaque)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;
   
    for(i = 0; i < 3; i++) {
        s = &pit->channels[i];
        qemu_put_be32s(f, &s->count);
        qemu_put_be16s(f, &s->latched_count);
        qemu_put_8s(f, &s->count_latched);
        qemu_put_8s(f, &s->status_latched);
        qemu_put_8s(f, &s->status);
        qemu_put_8s(f, &s->read_state);
        qemu_put_8s(f, &s->write_state);
        qemu_put_8s(f, &s->write_latch);
        qemu_put_8s(f, &s->rw_mode);
        qemu_put_8s(f, &s->mode);
        qemu_put_8s(f, &s->bcd);
        qemu_put_8s(f, &s->gate);
        qemu_put_be64s(f, &s->count_load_time);
        if (s->irq_timer) {
            qemu_put_be64s(f, &s->next_transition_time);
            qemu_put_timer(f, s->irq_timer);
        }
    }
}

static int pit_load(QEMUFile *f, void *opaque, int version_id)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;
   
    if (version_id != 1)
        return -EINVAL;

    for(i = 0; i < 3; i++) {
        s = &pit->channels[i];
        qemu_get_be32s(f, &s->count);
        qemu_get_be16s(f, &s->latched_count);
        qemu_get_8s(f, &s->count_latched);
        qemu_get_8s(f, &s->status_latched);
        qemu_get_8s(f, &s->status);
        qemu_get_8s(f, &s->read_state);
        qemu_get_8s(f, &s->write_state);
        qemu_get_8s(f, &s->write_latch);
        qemu_get_8s(f, &s->rw_mode);
        qemu_get_8s(f, &s->mode);
        qemu_get_8s(f, &s->bcd);
        qemu_get_8s(f, &s->gate);
        qemu_get_be64s(f, &s->count_load_time);
        if (s->irq_timer) {
            qemu_get_be64s(f, &s->next_transition_time);
            qemu_get_timer(f, s->irq_timer);
        }
    }
    return 0;
}

static void pit_reset(void *opaque)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;

    for(i = 0;i < 3; i++) {
        s = &pit->channels[i];
        s->mode = 3;
        s->gate = (i != 2);
        pit_load_count(s, 0);
    }
}

PITState *pit_init(int base, qemu_irq irq)
{
    PITState *pit = &pit_state;
    PITChannelState *s;

    s = &pit->channels[0];
    /* the timer 0 is connected to an IRQ */
    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
    s->irq = irq;

    register_savevm("i8254", base, 1, pit_save, pit_load, pit);

    qemu_register_reset(pit_reset, pit);
    register_ioport_write(base, 4, 1, pit_ioport_write, pit);
    register_ioport_read(base, 3, 1, pit_ioport_read, pit);

    pit_reset(pit);

    return pit;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8253/8254 interval timer emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
80cabfad FB	25
b0a21b53 FB	26	//#define DEBUG_PIT
b0a21b53 FB	27
ec844b96 FB	28	#define RW_STATE_LSB 1
	29	#define RW_STATE_MSB 2
	30	#define RW_STATE_WORD0 3
	31	#define RW_STATE_WORD1 4
80cabfad	32
ec844b96 FB	33	typedef struct PITChannelState {
	34	int count; /* can be 65536 */
	35	uint16_t latched_count;
	36	uint8_t count_latched;
	37	uint8_t status_latched;
	38	uint8_t status;
	39	uint8_t read_state;
	40	uint8_t write_state;
	41	uint8_t write_latch;
	42	uint8_t rw_mode;
	43	uint8_t mode;
	44	uint8_t bcd; /* not supported */
	45	uint8_t gate; /* timer start */
	46	int64_t count_load_time;
	47	/* irq handling */
	48	int64_t next_transition_time;
	49	QEMUTimer *irq_timer;
d537cf6c	50	qemu_irq irq;
ec844b96 FB	51	} PITChannelState;
	52
	53	struct PITState {
	54	PITChannelState channels[3];
	55	};
	56
	57	static PITState pit_state;
80cabfad	58
b0a21b53 FB	59	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
b0a21b53 FB	60
80cabfad FB	61	static int pit_get_count(PITChannelState *s)
	62	{
	63	uint64_t d;
	64	int counter;
	65
b0a21b53	66	d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	67	switch(s->mode) {
	68	case 0:
	69	case 1:
	70	case 4:
	71	case 5:
	72	counter = (s->count - d) & 0xffff;
	73	break;
	74	case 3:
	75	/* XXX: may be incorrect for odd counts */
	76	counter = s->count - ((2 * d) % s->count);
	77	break;
	78	default:
	79	counter = s->count - (d % s->count);
	80	break;
	81	}
	82	return counter;
	83	}
	84
	85	/* get pit output bit */
ec844b96	86	static int pit_get_out1(PITChannelState *s, int64_t current_time)
80cabfad FB	87	{
	88	uint64_t d;
	89	int out;
	90
b0a21b53	91	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	92	switch(s->mode) {
	93	default:
	94	case 0:
	95	out = (d >= s->count);
	96	break;
	97	case 1:
	98	out = (d < s->count);
	99	break;
	100	case 2:
	101	if ((d % s->count) == 0 && d != 0)
	102	out = 1;
	103	else
	104	out = 0;
	105	break;
	106	case 3:
	107	out = (d % s->count) < ((s->count + 1) >> 1);
	108	break;
	109	case 4:
	110	case 5:
	111	out = (d == s->count);
	112	break;
	113	}
	114	return out;
	115	}
	116
ec844b96 FB	117	int pit_get_out(PITState *pit, int channel, int64_t current_time)
	118	{
	119	PITChannelState *s = &pit->channels[channel];
	120	return pit_get_out1(s, current_time);
	121	}
	122
b0a21b53	123	/* return -1 if no transition will occur. */
5fafdf24	124	static int64_t pit_get_next_transition_time(PITChannelState *s,
b0a21b53	125	int64_t current_time)
80cabfad	126	{
b0a21b53 FB	127	uint64_t d, next_time, base;
b0a21b53 FB	128	int period2;
80cabfad	129
b0a21b53	130	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	131	switch(s->mode) {
	132	default:
	133	case 0:
80cabfad	134	case 1:
b0a21b53 FB	135	if (d < s->count)
	136	next_time = s->count;
	137	else
	138	return -1;
80cabfad FB	139	break;
80cabfad FB	140	case 2:
b0a21b53 FB	141	base = (d / s->count) * s->count;
	142	if ((d - base) == 0 && d != 0)
	143	next_time = base + s->count;
	144	else
	145	next_time = base + s->count + 1;
80cabfad FB	146	break;
80cabfad FB	147	case 3:
b0a21b53 FB	148	base = (d / s->count) * s->count;
b0a21b53 FB	149	period2 = ((s->count + 1) >> 1);
5fafdf24	150	if ((d - base) < period2)
b0a21b53 FB	151	next_time = base + period2;
	152	else
	153	next_time = base + s->count;
80cabfad FB	154	break;
	155	case 4:
	156	case 5:
b0a21b53 FB	157	if (d < s->count)
	158	next_time = s->count;
	159	else if (d == s->count)
	160	next_time = s->count + 1;
80cabfad	161	else
b0a21b53	162	return -1;
80cabfad FB	163	break;
80cabfad FB	164	}
b0a21b53 FB	165	/* convert to timer units */
b0a21b53 FB	166	next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
1154e441 FB	167	/* fix potential rounding problems */
	168	/* XXX: better solution: use a clock at PIT_FREQ Hz */
	169	if (next_time <= current_time)
	170	next_time = current_time + 1;
b0a21b53	171	return next_time;
80cabfad FB	172	}
	173
	174	/* val must be 0 or 1 */
ec844b96	175	void pit_set_gate(PITState *pit, int channel, int val)
80cabfad	176	{
ec844b96 FB	177	PITChannelState *s = &pit->channels[channel];
ec844b96 FB	178
80cabfad FB	179	switch(s->mode) {
	180	default:
	181	case 0:
	182	case 4:
	183	/* XXX: just disable/enable counting */
	184	break;
	185	case 1:
	186	case 5:
	187	if (s->gate < val) {
	188	/* restart counting on rising edge */
b0a21b53 FB	189	s->count_load_time = qemu_get_clock(vm_clock);
b0a21b53 FB	190	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	191	}
	192	break;
	193	case 2:
	194	case 3:
	195	if (s->gate < val) {
	196	/* restart counting on rising edge */
b0a21b53 FB	197	s->count_load_time = qemu_get_clock(vm_clock);
b0a21b53 FB	198	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	199	}
	200	/* XXX: disable/enable counting */
	201	break;
	202	}
	203	s->gate = val;
	204	}
	205
ec844b96 FB	206	int pit_get_gate(PITState *pit, int channel)
	207	{
	208	PITChannelState *s = &pit->channels[channel];
	209	return s->gate;
	210	}
	211
fd06c375 FB	212	int pit_get_initial_count(PITState *pit, int channel)
	213	{
	214	PITChannelState *s = &pit->channels[channel];
	215	return s->count;
	216	}
	217
	218	int pit_get_mode(PITState *pit, int channel)
	219	{
	220	PITChannelState *s = &pit->channels[channel];
	221	return s->mode;
	222	}
	223
80cabfad FB	224	static inline void pit_load_count(PITChannelState *s, int val)
	225	{
	226	if (val == 0)
	227	val = 0x10000;
b0a21b53	228	s->count_load_time = qemu_get_clock(vm_clock);
80cabfad	229	s->count = val;
b0a21b53	230	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	231	}
80cabfad FB	232
ec844b96 FB	233	/* if already latched, do not latch again */
	234	static void pit_latch_count(PITChannelState *s)
	235	{
	236	if (!s->count_latched) {
	237	s->latched_count = pit_get_count(s);
	238	s->count_latched = s->rw_mode;
	239	}
	240	}
	241
b41a2cd1	242	static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	243	{
ec844b96	244	PITState *pit = opaque;
80cabfad FB	245	int channel, access;
	246	PITChannelState *s;
	247
	248	addr &= 3;
	249	if (addr == 3) {
	250	channel = val >> 6;
ec844b96 FB	251	if (channel == 3) {
	252	/* read back command */
	253	for(channel = 0; channel < 3; channel++) {
	254	s = &pit->channels[channel];
	255	if (val & (2 << channel)) {
	256	if (!(val & 0x20)) {
	257	pit_latch_count(s);
	258	}
	259	if (!(val & 0x10) && !s->status_latched) {
	260	/* status latch */
	261	/* XXX: add BCD and null count */
	262	s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) \|
	263	(s->rw_mode << 4) \|
	264	(s->mode << 1) \|
	265	s->bcd;
	266	s->status_latched = 1;
	267	}
	268	}
	269	}
	270	} else {
	271	s = &pit->channels[channel];
	272	access = (val >> 4) & 3;
	273	if (access == 0) {
	274	pit_latch_count(s);
	275	} else {
	276	s->rw_mode = access;
	277	s->read_state = access;
	278	s->write_state = access;
	279
	280	s->mode = (val >> 1) & 7;
	281	s->bcd = val & 1;
	282	/* XXX: update irq timer ? */
	283	}
80cabfad FB	284	}
80cabfad FB	285	} else {
ec844b96 FB	286	s = &pit->channels[addr];
	287	switch(s->write_state) {
	288	default:
80cabfad FB	289	case RW_STATE_LSB:
	290	pit_load_count(s, val);
	291	break;
	292	case RW_STATE_MSB:
	293	pit_load_count(s, val << 8);
	294	break;
	295	case RW_STATE_WORD0:
ec844b96 FB	296	s->write_latch = val;
	297	s->write_state = RW_STATE_WORD1;
	298	break;
80cabfad	299	case RW_STATE_WORD1:
ec844b96 FB	300	pit_load_count(s, s->write_latch \| (val << 8));
ec844b96 FB	301	s->write_state = RW_STATE_WORD0;
80cabfad FB	302	break;
	303	}
	304	}
	305	}
	306
b41a2cd1	307	static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
80cabfad	308	{
ec844b96	309	PITState *pit = opaque;
80cabfad FB	310	int ret, count;
80cabfad FB	311	PITChannelState *s;
5fafdf24	312
80cabfad	313	addr &= 3;
ec844b96 FB	314	s = &pit->channels[addr];
	315	if (s->status_latched) {
	316	s->status_latched = 0;
	317	ret = s->status;
	318	} else if (s->count_latched) {
	319	switch(s->count_latched) {
	320	default:
	321	case RW_STATE_LSB:
	322	ret = s->latched_count & 0xff;
	323	s->count_latched = 0;
	324	break;
	325	case RW_STATE_MSB:
80cabfad	326	ret = s->latched_count >> 8;
ec844b96 FB	327	s->count_latched = 0;
	328	break;
	329	case RW_STATE_WORD0:
80cabfad	330	ret = s->latched_count & 0xff;
ec844b96 FB	331	s->count_latched = RW_STATE_MSB;
	332	break;
	333	}
	334	} else {
	335	switch(s->read_state) {
	336	default:
	337	case RW_STATE_LSB:
	338	count = pit_get_count(s);
	339	ret = count & 0xff;
	340	break;
	341	case RW_STATE_MSB:
	342	count = pit_get_count(s);
	343	ret = (count >> 8) & 0xff;
	344	break;
	345	case RW_STATE_WORD0:
	346	count = pit_get_count(s);
	347	ret = count & 0xff;
	348	s->read_state = RW_STATE_WORD1;
	349	break;
	350	case RW_STATE_WORD1:
	351	count = pit_get_count(s);
	352	ret = (count >> 8) & 0xff;
	353	s->read_state = RW_STATE_WORD0;
	354	break;
	355	}
80cabfad FB	356	}
	357	return ret;
	358	}
	359
b0a21b53 FB	360	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
	361	{
	362	int64_t expire_time;
	363	int irq_level;
	364
	365	if (!s->irq_timer)
	366	return;
	367	expire_time = pit_get_next_transition_time(s, current_time);
ec844b96	368	irq_level = pit_get_out1(s, current_time);
d537cf6c	369	qemu_set_irq(s->irq, irq_level);
b0a21b53 FB	370	#ifdef DEBUG_PIT
b0a21b53 FB	371	printf("irq_level=%d next_delay=%f\n",
5fafdf24	372	irq_level,
b0a21b53 FB	373	(double)(expire_time - current_time) / ticks_per_sec);
	374	#endif
	375	s->next_transition_time = expire_time;
	376	if (expire_time != -1)
	377	qemu_mod_timer(s->irq_timer, expire_time);
	378	else
	379	qemu_del_timer(s->irq_timer);
	380	}
	381
	382	static void pit_irq_timer(void *opaque)
	383	{
	384	PITChannelState *s = opaque;
	385
	386	pit_irq_timer_update(s, s->next_transition_time);
	387	}
	388
	389	static void pit_save(QEMUFile f, void opaque)
	390	{
ec844b96	391	PITState *pit = opaque;
b0a21b53 FB	392	PITChannelState *s;
b0a21b53 FB	393	int i;
5fafdf24	394
b0a21b53	395	for(i = 0; i < 3; i++) {
ec844b96	396	s = &pit->channels[i];
b0a21b53 FB	397	qemu_put_be32s(f, &s->count);
b0a21b53 FB	398	qemu_put_be16s(f, &s->latched_count);
ec844b96 FB	399	qemu_put_8s(f, &s->count_latched);
	400	qemu_put_8s(f, &s->status_latched);
	401	qemu_put_8s(f, &s->status);
	402	qemu_put_8s(f, &s->read_state);
	403	qemu_put_8s(f, &s->write_state);
	404	qemu_put_8s(f, &s->write_latch);
	405	qemu_put_8s(f, &s->rw_mode);
b0a21b53 FB	406	qemu_put_8s(f, &s->mode);
	407	qemu_put_8s(f, &s->bcd);
	408	qemu_put_8s(f, &s->gate);
	409	qemu_put_be64s(f, &s->count_load_time);
	410	if (s->irq_timer) {
	411	qemu_put_be64s(f, &s->next_transition_time);
	412	qemu_put_timer(f, s->irq_timer);
	413	}
	414	}
	415	}
	416
	417	static int pit_load(QEMUFile f, void opaque, int version_id)
	418	{
ec844b96	419	PITState *pit = opaque;
b0a21b53 FB	420	PITChannelState *s;
b0a21b53 FB	421	int i;
5fafdf24	422
b0a21b53 FB	423	if (version_id != 1)
	424	return -EINVAL;
	425
	426	for(i = 0; i < 3; i++) {
ec844b96	427	s = &pit->channels[i];
b0a21b53 FB	428	qemu_get_be32s(f, &s->count);
b0a21b53 FB	429	qemu_get_be16s(f, &s->latched_count);
ec844b96 FB	430	qemu_get_8s(f, &s->count_latched);
	431	qemu_get_8s(f, &s->status_latched);
	432	qemu_get_8s(f, &s->status);
	433	qemu_get_8s(f, &s->read_state);
	434	qemu_get_8s(f, &s->write_state);
	435	qemu_get_8s(f, &s->write_latch);
	436	qemu_get_8s(f, &s->rw_mode);
b0a21b53 FB	437	qemu_get_8s(f, &s->mode);
	438	qemu_get_8s(f, &s->bcd);
	439	qemu_get_8s(f, &s->gate);
	440	qemu_get_be64s(f, &s->count_load_time);
	441	if (s->irq_timer) {
	442	qemu_get_be64s(f, &s->next_transition_time);
	443	qemu_get_timer(f, s->irq_timer);
	444	}
	445	}
	446	return 0;
	447	}
	448
d7d02e3c	449	static void pit_reset(void *opaque)
80cabfad	450	{
d7d02e3c	451	PITState *pit = opaque;
80cabfad FB	452	PITChannelState *s;
	453	int i;
	454
	455	for(i = 0;i < 3; i++) {
ec844b96	456	s = &pit->channels[i];
80cabfad FB	457	s->mode = 3;
	458	s->gate = (i != 2);
	459	pit_load_count(s, 0);
	460	}
d7d02e3c FB	461	}
d7d02e3c FB	462
d537cf6c	463	PITState *pit_init(int base, qemu_irq irq)
d7d02e3c FB	464	{
	465	PITState *pit = &pit_state;
	466	PITChannelState *s;
	467
	468	s = &pit->channels[0];
	469	/* the timer 0 is connected to an IRQ */
	470	s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
	471	s->irq = irq;
80cabfad	472
ec844b96	473	register_savevm("i8254", base, 1, pit_save, pit_load, pit);
b0a21b53	474
d7d02e3c	475	qemu_register_reset(pit_reset, pit);
ec844b96 FB	476	register_ioport_write(base, 4, 1, pit_ioport_write, pit);
ec844b96 FB	477	register_ioport_read(base, 3, 1, pit_ioport_read, pit);
d7d02e3c FB	478
	479	pit_reset(pit);
	480
ec844b96	481	return pit;
80cabfad	482	}