[qemu.git] / hw / arm_boot.c

/*
 * ARM kernel loader.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "config.h"
#include "hw.h"
#include "arm-misc.h"
#include "sysemu.h"
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "device_tree.h"

#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x00010000
#define INITRD_LOAD_ADDR 0x00d00000

/* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */
static uint32_t bootloader[] = {
  0xe3a00000, /* mov     r0, #0 */
  0xe59f1004, /* ldr     r1, [pc, #4] */
  0xe59f2004, /* ldr     r2, [pc, #4] */
  0xe59ff004, /* ldr     pc, [pc, #4] */
  0, /* Board ID */
  0, /* Address of kernel args.  Set by integratorcp_init.  */
  0  /* Kernel entry point.  Set by integratorcp_init.  */
};

/* Handling for secondary CPU boot in a multicore system.
 * Unlike the uniprocessor/primary CPU boot, this is platform
 * dependent. The default code here is based on the secondary
 * CPU boot protocol used on realview/vexpress boards, with
 * some parameterisation to increase its flexibility.
 * QEMU platform models for which this code is not appropriate
 * should override write_secondary_boot and secondary_cpu_reset_hook
 * instead.
 *
 * This code enables the interrupt controllers for the secondary
 * CPUs and then puts all the secondary CPUs into a loop waiting
 * for an interprocessor interrupt and polling a configurable
 * location for the kernel secondary CPU entry point.
 */
static uint32_t smpboot[] = {
  0xe59f201c, /* ldr r2, gic_cpu_if */
  0xe59f001c, /* ldr r0, startaddr */
  0xe3a01001, /* mov r1, #1 */
  0xe5821000, /* str r1, [r2] */
  0xe320f003, /* wfi */
  0xe5901000, /* ldr     r1, [r0] */
  0xe1110001, /* tst     r1, r1 */
  0x0afffffb, /* beq     <wfi> */
  0xe12fff11, /* bx      r1 */
  0,          /* gic_cpu_if: base address of GIC CPU interface */
  0           /* bootreg: Boot register address is held here */
};

static void default_write_secondary(ARMCPU *cpu,
                                    const struct arm_boot_info *info)
{
    int n;
    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
                       info->smp_loader_start);
}

static void default_reset_secondary(ARMCPU *cpu,
                                    const struct arm_boot_info *info)
{
    CPUARMState *env = &cpu->env;

    stl_phys_notdirty(info->smp_bootreg_addr, 0);
    env->regs[15] = info->smp_loader_start;
}

#define WRITE_WORD(p, value) do { \
    stl_phys_notdirty(p, value);  \
    p += 4;                       \
} while (0)

static void set_kernel_args(const struct arm_boot_info *info)
{
    int initrd_size = info->initrd_size;
    target_phys_addr_t base = info->loader_start;
    target_phys_addr_t p;

    p = base + KERNEL_ARGS_ADDR;
    /* ATAG_CORE */
    WRITE_WORD(p, 5);
    WRITE_WORD(p, 0x54410001);
    WRITE_WORD(p, 1);
    WRITE_WORD(p, 0x1000);
    WRITE_WORD(p, 0);
    /* ATAG_MEM */
    /* TODO: handle multiple chips on one ATAG list */
    WRITE_WORD(p, 4);
    WRITE_WORD(p, 0x54410002);
    WRITE_WORD(p, info->ram_size);
    WRITE_WORD(p, info->loader_start);
    if (initrd_size) {
        /* ATAG_INITRD2 */
        WRITE_WORD(p, 4);
        WRITE_WORD(p, 0x54420005);
        WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
        WRITE_WORD(p, initrd_size);
    }
    if (info->kernel_cmdline && *info->kernel_cmdline) {
        /* ATAG_CMDLINE */
        int cmdline_size;

        cmdline_size = strlen(info->kernel_cmdline);
        cpu_physical_memory_write(p + 8, (void *)info->kernel_cmdline,
                                  cmdline_size + 1);
        cmdline_size = (cmdline_size >> 2) + 1;
        WRITE_WORD(p, cmdline_size + 2);
        WRITE_WORD(p, 0x54410009);
        p += cmdline_size * 4;
    }
    if (info->atag_board) {
        /* ATAG_BOARD */
        int atag_board_len;
        uint8_t atag_board_buf[0x1000];

        atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
        WRITE_WORD(p, (atag_board_len + 8) >> 2);
        WRITE_WORD(p, 0x414f4d50);
        cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
        p += atag_board_len;
    }
    /* ATAG_END */
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
}

static void set_kernel_args_old(const struct arm_boot_info *info)
{
    target_phys_addr_t p;
    const char *s;
    int initrd_size = info->initrd_size;
    target_phys_addr_t base = info->loader_start;

    /* see linux/include/asm-arm/setup.h */
    p = base + KERNEL_ARGS_ADDR;
    /* page_size */
    WRITE_WORD(p, 4096);
    /* nr_pages */
    WRITE_WORD(p, info->ram_size / 4096);
    /* ramdisk_size */
    WRITE_WORD(p, 0);
#define FLAG_READONLY	1
#define FLAG_RDLOAD	4
#define FLAG_RDPROMPT	8
    /* flags */
    WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
    /* rootdev */
    WRITE_WORD(p, (31 << 8) | 0);	/* /dev/mtdblock0 */
    /* video_num_cols */
    WRITE_WORD(p, 0);
    /* video_num_rows */
    WRITE_WORD(p, 0);
    /* video_x */
    WRITE_WORD(p, 0);
    /* video_y */
    WRITE_WORD(p, 0);
    /* memc_control_reg */
    WRITE_WORD(p, 0);
    /* unsigned char sounddefault */
    /* unsigned char adfsdrives */
    /* unsigned char bytes_per_char_h */
    /* unsigned char bytes_per_char_v */
    WRITE_WORD(p, 0);
    /* pages_in_bank[4] */
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    WRITE_WORD(p, 0);
    /* pages_in_vram */
    WRITE_WORD(p, 0);
    /* initrd_start */
    if (initrd_size)
        WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
    else
        WRITE_WORD(p, 0);
    /* initrd_size */
    WRITE_WORD(p, initrd_size);
    /* rd_start */
    WRITE_WORD(p, 0);
    /* system_rev */
    WRITE_WORD(p, 0);
    /* system_serial_low */
    WRITE_WORD(p, 0);
    /* system_serial_high */
    WRITE_WORD(p, 0);
    /* mem_fclk_21285 */
    WRITE_WORD(p, 0);
    /* zero unused fields */
    while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
        WRITE_WORD(p, 0);
    }
    s = info->kernel_cmdline;
    if (s) {
        cpu_physical_memory_write(p, (void *)s, strlen(s) + 1);
    } else {
        WRITE_WORD(p, 0);
    }
}

static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
{
#ifdef CONFIG_FDT
    uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start),
                                    cpu_to_be32(binfo->ram_size) };
    void *fdt = NULL;
    char *filename;
    int size, rc;

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
    if (!filename) {
        fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
        return -1;
    }

    fdt = load_device_tree(filename, &size);
    if (!fdt) {
        fprintf(stderr, "Couldn't open dtb file %s\n", filename);
        g_free(filename);
        return -1;
    }
    g_free(filename);

    rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
                               sizeof(mem_reg_property));
    if (rc < 0) {
        fprintf(stderr, "couldn't set /memory/reg\n");
    }

    rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
                                      binfo->kernel_cmdline);
    if (rc < 0) {
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    }

    if (binfo->initrd_size) {
        rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
                binfo->loader_start + INITRD_LOAD_ADDR);
        if (rc < 0) {
            fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
        }

        rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                    binfo->loader_start + INITRD_LOAD_ADDR +
                    binfo->initrd_size);
        if (rc < 0) {
            fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
        }
    }

    cpu_physical_memory_write(addr, fdt, size);

    return 0;

#else
    fprintf(stderr, "Device tree requested, "
                "but qemu was compiled without fdt support\n");
    return -1;
#endif
}

static void do_cpu_reset(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    const struct arm_boot_info *info = env->boot_info;

    cpu_reset(CPU(cpu));
    if (info) {
        if (!info->is_linux) {
            /* Jump to the entry point.  */
            env->regs[15] = info->entry & 0xfffffffe;
            env->thumb = info->entry & 1;
        } else {
            if (env == first_cpu) {
                env->regs[15] = info->loader_start;
                if (!info->dtb_filename) {
                    if (old_param) {
                        set_kernel_args_old(info);
                    } else {
                        set_kernel_args(info);
                    }
                }
            } else {
                info->secondary_cpu_reset_hook(cpu, info);
            }
        }
    }
}

void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
    ARMCPU *cpu = arm_env_get_cpu(env);
    int kernel_size;
    int initrd_size;
    int n;
    int is_linux = 0;
    uint64_t elf_entry;
    target_phys_addr_t entry;
    int big_endian;
    QemuOpts *machine_opts;

    /* Load the kernel.  */
    if (!info->kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
    if (machine_opts) {
        info->dtb_filename = qemu_opt_get(machine_opts, "dtb");
    } else {
        info->dtb_filename = NULL;
    }

    if (!info->secondary_cpu_reset_hook) {
        info->secondary_cpu_reset_hook = default_reset_secondary;
    }
    if (!info->write_secondary_boot) {
        info->write_secondary_boot = default_write_secondary;
    }

    if (info->nb_cpus == 0)
        info->nb_cpus = 1;

#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

    /* Assume that raw images are linux kernels, and ELF images are not.  */
    kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
                           NULL, NULL, big_endian, ELF_MACHINE, 1);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
                                  &is_linux);
    }
    if (kernel_size < 0) {
        entry = info->loader_start + KERNEL_LOAD_ADDR;
        kernel_size = load_image_targphys(info->kernel_filename, entry,
                                          ram_size - KERNEL_LOAD_ADDR);
        is_linux = 1;
    }
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                info->kernel_filename);
        exit(1);
    }
    info->entry = entry;
    if (is_linux) {
        if (info->initrd_filename) {
            initrd_size = load_image_targphys(info->initrd_filename,
                                              info->loader_start
                                              + INITRD_LOAD_ADDR,
                                              ram_size - INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initrd '%s'\n",
                        info->initrd_filename);
                exit(1);
            }
        } else {
            initrd_size = 0;
        }
        info->initrd_size = initrd_size;

        bootloader[4] = info->board_id;

        /* for device tree boot, we pass the DTB directly in r2. Otherwise
         * we point to the kernel args.
         */
        if (info->dtb_filename) {
            /* Place the DTB after the initrd in memory */
            target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
                                                             + INITRD_LOAD_ADDR
                                                             + initrd_size);
            if (load_dtb(dtb_start, info)) {
                exit(1);
            }
            bootloader[5] = dtb_start;
        } else {
            bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
        }
        bootloader[6] = entry;
        for (n = 0; n < sizeof(bootloader) / 4; n++) {
            bootloader[n] = tswap32(bootloader[n]);
        }
        rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
                           info->loader_start);
        if (info->nb_cpus > 1) {
            info->write_secondary_boot(cpu, info);
        }
    }
    info->is_linux = is_linux;

    for (; env; env = env->next_cpu) {
        cpu = arm_env_get_cpu(env);
        env->boot_info = info;
        qemu_register_reset(do_cpu_reset, cpu);
    }
}
Commit	Line	Data
5fafdf24	1	/*
16406950 PB	2	* ARM kernel loader.
16406950 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
16406950 PB	5	* Written by Paul Brook
16406950 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
16406950 PB	8	*/
16406950 PB	9
412beee6	10	#include "config.h"
87ecb68b PB	11	#include "hw.h"
	12	#include "arm-misc.h"
	13	#include "sysemu.h"
412beee6	14	#include "boards.h"
ca20cf32 BS	15	#include "loader.h"
ca20cf32 BS	16	#include "elf.h"
412beee6	17	#include "device_tree.h"
16406950 PB	18
	19	#define KERNEL_ARGS_ADDR 0x100
	20	#define KERNEL_LOAD_ADDR 0x00010000
756ba3b0	21	#define INITRD_LOAD_ADDR 0x00d00000
16406950 PB	22
	23	/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
	24	static uint32_t bootloader[] = {
	25	0xe3a00000, /* mov r0, #0 */
f8414cb5 PM	26	0xe59f1004, /* ldr r1, [pc, #4] */
	27	0xe59f2004, /* ldr r2, [pc, #4] */
	28	0xe59ff004, /* ldr pc, [pc, #4] */
	29	0, /* Board ID */
16406950 PB	30	0, /* Address of kernel args. Set by integratorcp_init. */
	31	0 /* Kernel entry point. Set by integratorcp_init. */
	32	};
	33
9d5ba9bf ML	34	/* Handling for secondary CPU boot in a multicore system.
	35	* Unlike the uniprocessor/primary CPU boot, this is platform
	36	* dependent. The default code here is based on the secondary
	37	* CPU boot protocol used on realview/vexpress boards, with
	38	* some parameterisation to increase its flexibility.
	39	* QEMU platform models for which this code is not appropriate
	40	* should override write_secondary_boot and secondary_cpu_reset_hook
	41	* instead.
	42	*
	43	* This code enables the interrupt controllers for the secondary
	44	* CPUs and then puts all the secondary CPUs into a loop waiting
	45	* for an interprocessor interrupt and polling a configurable
	46	* location for the kernel secondary CPU entry point.
	47	*/
9ee6e8bb	48	static uint32_t smpboot[] = {
96eacf64	49	0xe59f201c, /* ldr r2, gic_cpu_if */
078758d0 EV	50	0xe59f001c, /* ldr r0, startaddr */
078758d0 EV	51	0xe3a01001, /* mov r1, #1 */
96eacf64	52	0xe5821000, /* str r1, [r2] */
9ee6e8bb PB	53	0xe320f003, /* wfi */
9ee6e8bb PB	54	0xe5901000, /* ldr r1, [r0] */
be0f204a PB	55	0xe1110001, /* tst r1, r1 */
be0f204a PB	56	0x0afffffb, /* beq <wfi> */
f7c70325	57	0xe12fff11, /* bx r1 */
96eacf64	58	0, /* gic_cpu_if: base address of GIC CPU interface */
078758d0	59	0 /* bootreg: Boot register address is held here */
9ee6e8bb PB	60	};
9ee6e8bb PB	61
9543b0cd	62	static void default_write_secondary(ARMCPU *cpu,
9d5ba9bf ML	63	const struct arm_boot_info *info)
	64	{
	65	int n;
	66	smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
96eacf64	67	smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
9d5ba9bf ML	68	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	69	smpboot[n] = tswap32(smpboot[n]);
	70	}
	71	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
	72	info->smp_loader_start);
	73	}
	74
5d309320	75	static void default_reset_secondary(ARMCPU *cpu,
9d5ba9bf ML	76	const struct arm_boot_info *info)
9d5ba9bf ML	77	{
5d309320 AF	78	CPUARMState *env = &cpu->env;
5d309320 AF	79
9d5ba9bf ML	80	stl_phys_notdirty(info->smp_bootreg_addr, 0);
	81	env->regs[15] = info->smp_loader_start;
	82	}
	83
52b43737 PB	84	#define WRITE_WORD(p, value) do { \
	85	stl_phys_notdirty(p, value); \
	86	p += 4; \
	87	} while (0)
	88
761c9eb0	89	static void set_kernel_args(const struct arm_boot_info *info)
16406950	90	{
761c9eb0 SW	91	int initrd_size = info->initrd_size;
761c9eb0 SW	92	target_phys_addr_t base = info->loader_start;
c227f099	93	target_phys_addr_t p;
16406950	94
52b43737	95	p = base + KERNEL_ARGS_ADDR;
16406950	96	/* ATAG_CORE */
52b43737 PB	97	WRITE_WORD(p, 5);
	98	WRITE_WORD(p, 0x54410001);
	99	WRITE_WORD(p, 1);
	100	WRITE_WORD(p, 0x1000);
	101	WRITE_WORD(p, 0);
16406950	102	/* ATAG_MEM */
f93eb9ff	103	/* TODO: handle multiple chips on one ATAG list */
52b43737 PB	104	WRITE_WORD(p, 4);
	105	WRITE_WORD(p, 0x54410002);
	106	WRITE_WORD(p, info->ram_size);
	107	WRITE_WORD(p, info->loader_start);
16406950 PB	108	if (initrd_size) {
16406950 PB	109	/* ATAG_INITRD2 */
52b43737 PB	110	WRITE_WORD(p, 4);
	111	WRITE_WORD(p, 0x54420005);
	112	WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
	113	WRITE_WORD(p, initrd_size);
16406950	114	}
f93eb9ff	115	if (info->kernel_cmdline && *info->kernel_cmdline) {
16406950 PB	116	/* ATAG_CMDLINE */
	117	int cmdline_size;
	118
f93eb9ff	119	cmdline_size = strlen(info->kernel_cmdline);
52b43737 PB	120	cpu_physical_memory_write(p + 8, (void *)info->kernel_cmdline,
52b43737 PB	121	cmdline_size + 1);
16406950	122	cmdline_size = (cmdline_size >> 2) + 1;
52b43737 PB	123	WRITE_WORD(p, cmdline_size + 2);
	124	WRITE_WORD(p, 0x54410009);
	125	p += cmdline_size * 4;
16406950	126	}
f93eb9ff AZ	127	if (info->atag_board) {
	128	/* ATAG_BOARD */
	129	int atag_board_len;
52b43737	130	uint8_t atag_board_buf[0x1000];
f93eb9ff	131
52b43737 PB	132	atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
	133	WRITE_WORD(p, (atag_board_len + 8) >> 2);
	134	WRITE_WORD(p, 0x414f4d50);
	135	cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
f93eb9ff AZ	136	p += atag_board_len;
f93eb9ff AZ	137	}
16406950	138	/* ATAG_END */
52b43737 PB	139	WRITE_WORD(p, 0);
52b43737 PB	140	WRITE_WORD(p, 0);
16406950 PB	141	}
16406950 PB	142
761c9eb0	143	static void set_kernel_args_old(const struct arm_boot_info *info)
2b8f2d41	144	{
c227f099	145	target_phys_addr_t p;
52b43737	146	const char *s;
761c9eb0 SW	147	int initrd_size = info->initrd_size;
761c9eb0 SW	148	target_phys_addr_t base = info->loader_start;
2b8f2d41 AZ	149
2b8f2d41 AZ	150	/* see linux/include/asm-arm/setup.h */
52b43737	151	p = base + KERNEL_ARGS_ADDR;
2b8f2d41	152	/* page_size */
52b43737	153	WRITE_WORD(p, 4096);
2b8f2d41	154	/* nr_pages */
52b43737	155	WRITE_WORD(p, info->ram_size / 4096);
2b8f2d41	156	/* ramdisk_size */
52b43737	157	WRITE_WORD(p, 0);
2b8f2d41 AZ	158	#define FLAG_READONLY 1
	159	#define FLAG_RDLOAD 4
	160	#define FLAG_RDPROMPT 8
	161	/* flags */
52b43737	162	WRITE_WORD(p, FLAG_READONLY \| FLAG_RDLOAD \| FLAG_RDPROMPT);
2b8f2d41	163	/* rootdev */
52b43737	164	WRITE_WORD(p, (31 << 8) \| 0); /* /dev/mtdblock0 */
2b8f2d41	165	/* video_num_cols */
52b43737	166	WRITE_WORD(p, 0);
2b8f2d41	167	/* video_num_rows */
52b43737	168	WRITE_WORD(p, 0);
2b8f2d41	169	/* video_x */
52b43737	170	WRITE_WORD(p, 0);
2b8f2d41	171	/* video_y */
52b43737	172	WRITE_WORD(p, 0);
2b8f2d41	173	/* memc_control_reg */
52b43737	174	WRITE_WORD(p, 0);
2b8f2d41 AZ	175	/* unsigned char sounddefault */
	176	/* unsigned char adfsdrives */
	177	/* unsigned char bytes_per_char_h */
	178	/* unsigned char bytes_per_char_v */
52b43737	179	WRITE_WORD(p, 0);
2b8f2d41	180	/* pages_in_bank[4] */
52b43737 PB	181	WRITE_WORD(p, 0);
	182	WRITE_WORD(p, 0);
	183	WRITE_WORD(p, 0);
	184	WRITE_WORD(p, 0);
2b8f2d41	185	/* pages_in_vram */
52b43737	186	WRITE_WORD(p, 0);
2b8f2d41 AZ	187	/* initrd_start */
2b8f2d41 AZ	188	if (initrd_size)
52b43737	189	WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR);
2b8f2d41	190	else
52b43737	191	WRITE_WORD(p, 0);
2b8f2d41	192	/* initrd_size */
52b43737	193	WRITE_WORD(p, initrd_size);
2b8f2d41	194	/* rd_start */
52b43737	195	WRITE_WORD(p, 0);
2b8f2d41	196	/* system_rev */
52b43737	197	WRITE_WORD(p, 0);
2b8f2d41	198	/* system_serial_low */
52b43737	199	WRITE_WORD(p, 0);
2b8f2d41	200	/* system_serial_high */
52b43737	201	WRITE_WORD(p, 0);
2b8f2d41	202	/* mem_fclk_21285 */
52b43737	203	WRITE_WORD(p, 0);
2b8f2d41	204	/* zero unused fields */
52b43737 PB	205	while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
	206	WRITE_WORD(p, 0);
	207	}
	208	s = info->kernel_cmdline;
	209	if (s) {
	210	cpu_physical_memory_write(p, (void *)s, strlen(s) + 1);
	211	} else {
	212	WRITE_WORD(p, 0);
	213	}
2b8f2d41 AZ	214	}
2b8f2d41 AZ	215
412beee6 GL	216	static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
	217	{
	218	#ifdef CONFIG_FDT
	219	uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start),
	220	cpu_to_be32(binfo->ram_size) };
	221	void *fdt = NULL;
	222	char *filename;
	223	int size, rc;
	224
	225	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
	226	if (!filename) {
	227	fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
	228	return -1;
	229	}
	230
	231	fdt = load_device_tree(filename, &size);
	232	if (!fdt) {
	233	fprintf(stderr, "Couldn't open dtb file %s\n", filename);
	234	g_free(filename);
	235	return -1;
	236	}
	237	g_free(filename);
	238
	239	rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
	240	sizeof(mem_reg_property));
	241	if (rc < 0) {
	242	fprintf(stderr, "couldn't set /memory/reg\n");
	243	}
	244
	245	rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
	246	binfo->kernel_cmdline);
	247	if (rc < 0) {
	248	fprintf(stderr, "couldn't set /chosen/bootargs\n");
	249	}
	250
	251	if (binfo->initrd_size) {
	252	rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
	253	binfo->loader_start + INITRD_LOAD_ADDR);
	254	if (rc < 0) {
	255	fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
	256	}
	257
	258	rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	259	binfo->loader_start + INITRD_LOAD_ADDR +
	260	binfo->initrd_size);
	261	if (rc < 0) {
	262	fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
	263	}
	264	}
	265
	266	cpu_physical_memory_write(addr, fdt, size);
	267
	268	return 0;
	269
	270	#else
	271	fprintf(stderr, "Device tree requested, "
	272	"but qemu was compiled without fdt support\n");
	273	return -1;
	274	#endif
	275	}
	276
6ed221b6	277	static void do_cpu_reset(void *opaque)
f2d74978	278	{
351d5666 AF	279	ARMCPU *cpu = opaque;
351d5666 AF	280	CPUARMState *env = &cpu->env;
462a8bc6	281	const struct arm_boot_info *info = env->boot_info;
f2d74978	282
351d5666	283	cpu_reset(CPU(cpu));
f2d74978 PB	284	if (info) {
	285	if (!info->is_linux) {
	286	/* Jump to the entry point. */
	287	env->regs[15] = info->entry & 0xfffffffe;
	288	env->thumb = info->entry & 1;
	289	} else {
6ed221b6 AL	290	if (env == first_cpu) {
6ed221b6 AL	291	env->regs[15] = info->loader_start;
412beee6 GL	292	if (!info->dtb_filename) {
	293	if (old_param) {
	294	set_kernel_args_old(info);
	295	} else {
	296	set_kernel_args(info);
	297	}
6ed221b6	298	}
f2d74978	299	} else {
5d309320	300	info->secondary_cpu_reset_hook(cpu, info);
f2d74978 PB	301	}
	302	}
	303	}
f2d74978 PB	304	}
f2d74978 PB	305
5ae93306	306	void arm_load_kernel(CPUARMState env, struct arm_boot_info info)
16406950	307	{
9543b0cd	308	ARMCPU *cpu = arm_env_get_cpu(env);
16406950 PB	309	int kernel_size;
	310	int initrd_size;
	311	int n;
1c7b3754 PB	312	int is_linux = 0;
1c7b3754 PB	313	uint64_t elf_entry;
c227f099	314	target_phys_addr_t entry;
ca20cf32	315	int big_endian;
412beee6	316	QemuOpts *machine_opts;
16406950 PB	317
16406950 PB	318	/* Load the kernel. */
f93eb9ff	319	if (!info->kernel_filename) {
16406950 PB	320	fprintf(stderr, "Kernel image must be specified\n");
	321	exit(1);
	322	}
daf90626	323
412beee6 GL	324	machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
	325	if (machine_opts) {
	326	info->dtb_filename = qemu_opt_get(machine_opts, "dtb");
	327	} else {
	328	info->dtb_filename = NULL;
	329	}
	330
9d5ba9bf ML	331	if (!info->secondary_cpu_reset_hook) {
	332	info->secondary_cpu_reset_hook = default_reset_secondary;
	333	}
	334	if (!info->write_secondary_boot) {
	335	info->write_secondary_boot = default_write_secondary;
	336	}
	337
f2d74978 PB	338	if (info->nb_cpus == 0)
f2d74978 PB	339	info->nb_cpus = 1;
f93eb9ff	340
ca20cf32 BS	341	#ifdef TARGET_WORDS_BIGENDIAN
	342	big_endian = 1;
	343	#else
	344	big_endian = 0;
	345	#endif
	346
1c7b3754	347	/* Assume that raw images are linux kernels, and ELF images are not. */
409dbce5 AJ	348	kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
409dbce5 AJ	349	NULL, NULL, big_endian, ELF_MACHINE, 1);
1c7b3754 PB	350	entry = elf_entry;
1c7b3754 PB	351	if (kernel_size < 0) {
5a9154e0 AL	352	kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
5a9154e0 AL	353	&is_linux);
1c7b3754 PB	354	}
1c7b3754 PB	355	if (kernel_size < 0) {
f93eb9ff	356	entry = info->loader_start + KERNEL_LOAD_ADDR;
3b760e04 PB	357	kernel_size = load_image_targphys(info->kernel_filename, entry,
3b760e04 PB	358	ram_size - KERNEL_LOAD_ADDR);
1c7b3754 PB	359	is_linux = 1;
	360	}
	361	if (kernel_size < 0) {
f93eb9ff AZ	362	fprintf(stderr, "qemu: could not load kernel '%s'\n",
f93eb9ff AZ	363	info->kernel_filename);
1c7b3754 PB	364	exit(1);
1c7b3754 PB	365	}
f2d74978 PB	366	info->entry = entry;
f2d74978 PB	367	if (is_linux) {
f93eb9ff	368	if (info->initrd_filename) {
3b760e04 PB	369	initrd_size = load_image_targphys(info->initrd_filename,
	370	info->loader_start
	371	+ INITRD_LOAD_ADDR,
	372	ram_size - INITRD_LOAD_ADDR);
daf90626 PB	373	if (initrd_size < 0) {
daf90626 PB	374	fprintf(stderr, "qemu: could not load initrd '%s'\n",
f93eb9ff	375	info->initrd_filename);
daf90626 PB	376	exit(1);
	377	}
	378	} else {
	379	initrd_size = 0;
	380	}
412beee6 GL	381	info->initrd_size = initrd_size;
412beee6 GL	382
f8414cb5	383	bootloader[4] = info->board_id;
412beee6 GL	384
	385	/* for device tree boot, we pass the DTB directly in r2. Otherwise
	386	* we point to the kernel args.
	387	*/
	388	if (info->dtb_filename) {
	389	/* Place the DTB after the initrd in memory */
	390	target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
	391	+ INITRD_LOAD_ADDR
	392	+ initrd_size);
	393	if (load_dtb(dtb_start, info)) {
	394	exit(1);
	395	}
	396	bootloader[5] = dtb_start;
	397	} else {
	398	bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
	399	}
1c7b3754	400	bootloader[6] = entry;
52b43737	401	for (n = 0; n < sizeof(bootloader) / 4; n++) {
f2d74978	402	bootloader[n] = tswap32(bootloader[n]);
52b43737	403	}
f2d74978 PB	404	rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
f2d74978 PB	405	info->loader_start);
52b43737	406	if (info->nb_cpus > 1) {
9543b0cd	407	info->write_secondary_boot(cpu, info);
52b43737	408	}
16406950	409	}
f2d74978	410	info->is_linux = is_linux;
6ed221b6 AL	411
6ed221b6 AL	412	for (; env; env = env->next_cpu) {
351d5666	413	cpu = arm_env_get_cpu(env);
6ed221b6	414	env->boot_info = info;
351d5666	415	qemu_register_reset(do_cpu_reset, cpu);
6ed221b6	416	}
16406950	417	}