[qemu.git] / target / nios2 / mmu.c

/*
 * Altera Nios II MMU emulation for qemu.
 *
 * Copyright (C) 2012 Chris Wulff <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see
 * <http://www.gnu.org/licenses/lgpl-2.1.html>
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "mmu.h"

#if !defined(CONFIG_USER_ONLY)

/* Define this to enable MMU debug messages */
/* #define DEBUG_MMU */

#ifdef DEBUG_MMU
#define MMU_LOG(x) x
#else
#define MMU_LOG(x)
#endif

void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
              int mmu_idx, uintptr_t retaddr)
{
    int ret;

    ret = nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(cs, retaddr);
        }
        cpu_loop_exit(cs);
    }
}

void mmu_read_debug(CPUNios2State *env, uint32_t rn)
{
    switch (rn) {
    case CR_TLBACC:
        MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn]));
        break;

    case CR_TLBMISC:
        MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn]));
        break;

    case CR_PTEADDR:
        MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn]));
        break;

    default:
        break;
    }
}

/* rw - 0 = read, 1 = write, 2 = fetch.  */
unsigned int mmu_translate(CPUNios2State *env,
                           Nios2MMULookup *lu,
                           target_ulong vaddr, int rw, int mmu_idx)
{
    Nios2CPU *cpu = nios2_env_get_cpu(env);
    int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
    int vpn = vaddr >> 12;

    MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n",
                     vaddr, pid, vpn));

    int way;
    for (way = 0; way < cpu->tlb_num_ways; way++) {

        Nios2TLBEntry *entry =
            &env->mmu.tlb[(way * cpu->tlb_num_ways) +
                          (vpn & env->mmu.tlb_entry_mask)];

        MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n",
                         (way * cpu->tlb_num_ways) +
                         (vpn & env->mmu.tlb_entry_mask),
                         entry->tag, (entry->tag >> 12)));

        if (((entry->tag >> 12) != vpn) ||
            (((entry->tag & (1 << 11)) == 0) &&
            ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
            continue;
        }
        lu->vaddr = vaddr & TARGET_PAGE_MASK;
        lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
        lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
                   ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
                   ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);

        MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n",
                         (way * cpu->tlb_num_ways) +
                         (vpn & env->mmu.tlb_entry_mask),
                         lu->vaddr, lu->paddr, lu->prot));
        return 1;
    }
    return 0;
}

static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
{
    CPUState *cs = ENV_GET_CPU(env);
    Nios2CPU *cpu = nios2_env_get_cpu(env);
    int idx;
    MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));

    for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
        Nios2TLBEntry *entry = &env->mmu.tlb[idx];

        MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n",
                         idx, entry->tag, entry->data));

        if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
            ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
            uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;

            MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr));

            tlb_flush_page(cs, vaddr);
        }
    }
}

void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
    CPUState *cs = ENV_GET_CPU(env);
    Nios2CPU *cpu = nios2_env_get_cpu(env);

    MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));

    switch (rn) {
    case CR_TLBACC:
        MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n",
                         v >> CR_TLBACC_IGN_SHIFT,
                         (v & CR_TLBACC_C) ? 'C' : '.',
                         (v & CR_TLBACC_R) ? 'R' : '.',
                         (v & CR_TLBACC_W) ? 'W' : '.',
                         (v & CR_TLBACC_X) ? 'X' : '.',
                         (v & CR_TLBACC_G) ? 'G' : '.',
                         v & CR_TLBACC_PFN_MASK));

        /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
        if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
            int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
            int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
            int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
            int g = (v & CR_TLBACC_G) ? 1 : 0;
            int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
            Nios2TLBEntry *entry =
                &env->mmu.tlb[(way * cpu->tlb_num_ways) +
                              (vpn & env->mmu.tlb_entry_mask)];
            uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
            uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
                                    CR_TLBACC_X | CR_TLBACC_PFN_MASK);

            if ((entry->tag != newTag) || (entry->data != newData)) {
                if (entry->tag & (1 << 10)) {
                    /* Flush existing entry */
                    MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n",
                                     entry->tag & TARGET_PAGE_MASK));
                    tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
                }
                entry->tag = newTag;
                entry->data = newData;
                MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n",
                                 (way * cpu->tlb_num_ways) +
                                 (vpn & env->mmu.tlb_entry_mask),
                                 entry->tag, entry->data));
            }
            /* Auto-increment tlbmisc.WAY */
            env->regs[CR_TLBMISC] =
                (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
                (((way + 1) & (cpu->tlb_num_ways - 1)) <<
                 CR_TLBMISC_WAY_SHIFT);
        }

        /* Writes to TLBACC don't change the read-back value */
        env->mmu.tlbacc_wr = v;
        break;

    case CR_TLBMISC:
        MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n",
                         v >> CR_TLBMISC_WAY_SHIFT,
                         (v & CR_TLBMISC_RD) ? 'R' : '.',
                         (v & CR_TLBMISC_WR) ? 'W' : '.',
                         (v & CR_TLBMISC_DBL) ? '2' : '.',
                         (v & CR_TLBMISC_BAD) ? 'B' : '.',
                         (v & CR_TLBMISC_PERM) ? 'P' : '.',
                         (v & CR_TLBMISC_D) ? 'D' : '.',
                         (v & CR_TLBMISC_PID_MASK) >> 4));

        if ((v & CR_TLBMISC_PID_MASK) !=
            (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
            mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
                               CR_TLBMISC_PID_SHIFT);
        }
        /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
        if (v & CR_TLBMISC_RD) {
            int way = (v >> CR_TLBMISC_WAY_SHIFT);
            int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
            Nios2TLBEntry *entry =
                &env->mmu.tlb[(way * cpu->tlb_num_ways) +
                              (vpn & env->mmu.tlb_entry_mask)];

            env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
            env->regs[CR_TLBACC] |= entry->data;
            env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
            env->regs[CR_TLBMISC] =
                (v & ~CR_TLBMISC_PID_MASK) |
                ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
                 CR_TLBMISC_PID_SHIFT);
            env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
            env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
            MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, "
                             "tlbacc %08X, tlbmisc %08X, pteaddr %08X\n",
                             way, vpn, entry->tag, entry->data,
                             env->regs[CR_TLBACC], env->regs[CR_TLBMISC],
                             env->regs[CR_PTEADDR]));
        } else {
            env->regs[CR_TLBMISC] = v;
        }

        env->mmu.tlbmisc_wr = v;
        break;

    case CR_PTEADDR:
        MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n",
                         v >> CR_PTEADDR_PTBASE_SHIFT,
                         (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT));

        /* Writes to PTEADDR don't change the read-back VPN value */
        env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
                                (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
        env->mmu.pteaddr_wr = v;
        break;

    default:
        break;
    }
}

void mmu_init(CPUNios2State *env)
{
    Nios2CPU *cpu = nios2_env_get_cpu(env);
    Nios2MMU *mmu = &env->mmu;

    MMU_LOG(qemu_log("mmu_init\n"));

    mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
    mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
}

void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env)
{
    Nios2CPU *cpu = nios2_env_get_cpu(env);
    int i;

    cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n",
                cpu->tlb_num_ways, cpu->tlb_num_entries,
                cpu->pid_num_bits);

    for (i = 0; i < cpu->tlb_num_entries; i++) {
        Nios2TLBEntry *entry = &env->mmu.tlb[i];
        cpu_fprintf(f, "TLB[%d] = %08X %08X %c VPN %05X "
                    "PID %02X %c PFN %05X %c%c%c%c\n",
                    i, entry->tag, entry->data,
                    (entry->tag & (1 << 10)) ? 'V' : '-',
                    entry->tag >> 12,
                    entry->tag & ((1 << cpu->pid_num_bits) - 1),
                    (entry->tag & (1 << 11)) ? 'G' : '-',
                    entry->data & CR_TLBACC_PFN_MASK,
                    (entry->data & CR_TLBACC_C) ? 'C' : '-',
                    (entry->data & CR_TLBACC_R) ? 'R' : '-',
                    (entry->data & CR_TLBACC_W) ? 'W' : '-',
                    (entry->data & CR_TLBACC_X) ? 'X' : '-');
    }
}

#endif /* !CONFIG_USER_ONLY */
Commit	Line	Data
032c76bc CW	1	/*
	2	* Altera Nios II MMU emulation for qemu.
	3	*
	4	* Copyright (C) 2012 Chris Wulff <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2.1 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see
	18	* <http://www.gnu.org/licenses/lgpl-2.1.html>
	19	*/
	20
	21	#include "qemu/osdep.h"
	22	#include "qemu-common.h"
	23	#include "cpu.h"
	24	#include "exec/exec-all.h"
	25	#include "mmu.h"
	26
	27	#if !defined(CONFIG_USER_ONLY)
	28
	29	/* Define this to enable MMU debug messages */
	30	/* #define DEBUG_MMU */
	31
	32	#ifdef DEBUG_MMU
	33	#define MMU_LOG(x) x
	34	#else
	35	#define MMU_LOG(x)
	36	#endif
	37
	38	void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
	39	int mmu_idx, uintptr_t retaddr)
	40	{
	41	int ret;
	42
	43	ret = nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
	44	if (unlikely(ret)) {
	45	if (retaddr) {
	46	/* now we have a real cpu fault */
	47	cpu_restore_state(cs, retaddr);
	48	}
	49	cpu_loop_exit(cs);
	50	}
	51	}
	52
	53	void mmu_read_debug(CPUNios2State *env, uint32_t rn)
	54	{
	55	switch (rn) {
	56	case CR_TLBACC:
	57	MMU_LOG(qemu_log("TLBACC READ %08X\n", env->regs[rn]));
	58	break;
	59
	60	case CR_TLBMISC:
	61	MMU_LOG(qemu_log("TLBMISC READ %08X\n", env->regs[rn]));
	62	break;
	63
	64	case CR_PTEADDR:
65	MMU_LOG(qemu_log("PTEADDR READ %08X\n", env->regs[rn]));
66	break;
67
68	default:
69	break;
70	}
71	}
72
73	/* rw - 0 = read, 1 = write, 2 = fetch. */
74	unsigned int mmu_translate(CPUNios2State *env,
75	Nios2MMULookup *lu,
76	target_ulong vaddr, int rw, int mmu_idx)
77	{
78	Nios2CPU *cpu = nios2_env_get_cpu(env);
79	int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
80	int vpn = vaddr >> 12;
81
82	MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n",
83	vaddr, pid, vpn));
84
85	int way;
86	for (way = 0; way < cpu->tlb_num_ways; way++) {
87
88	Nios2TLBEntry *entry =
89	&env->mmu.tlb[(way * cpu->tlb_num_ways) +
90	(vpn & env->mmu.tlb_entry_mask)];
91
92	MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n",
93	(way * cpu->tlb_num_ways) +
94	(vpn & env->mmu.tlb_entry_mask),
95	entry->tag, (entry->tag >> 12)));
96
97	if (((entry->tag >> 12) != vpn) \|\|
98	(((entry->tag & (1 << 11)) == 0) &&
99	((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
100	continue;
101	}
102	lu->vaddr = vaddr & TARGET_PAGE_MASK;
103	lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
104	lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) \|
105	((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) \|
106	((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
107
108	MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n",
109	(way * cpu->tlb_num_ways) +
110	(vpn & env->mmu.tlb_entry_mask),
111	lu->vaddr, lu->paddr, lu->prot));
112	return 1;
113	}
114	return 0;
115	}
116
117	static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
118	{
119	CPUState *cs = ENV_GET_CPU(env);
120	Nios2CPU *cpu = nios2_env_get_cpu(env);
121	int idx;
122	MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
123
124	for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
125	Nios2TLBEntry *entry = &env->mmu.tlb[idx];
126
127	MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n",
128	idx, entry->tag, entry->data));
129
130	if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
131	((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
132	uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;
133
134	MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr));
135
136	tlb_flush_page(cs, vaddr);
137	}
138	}
139	}
140
141	void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
142	{
143	CPUState *cs = ENV_GET_CPU(env);
144	Nios2CPU *cpu = nios2_env_get_cpu(env);
145
146	MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
147
148	switch (rn) {
149	case CR_TLBACC:
150	MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n",
151	v >> CR_TLBACC_IGN_SHIFT,
152	(v & CR_TLBACC_C) ? 'C' : '.',
153	(v & CR_TLBACC_R) ? 'R' : '.',
154	(v & CR_TLBACC_W) ? 'W' : '.',
155	(v & CR_TLBACC_X) ? 'X' : '.',
156	(v & CR_TLBACC_G) ? 'G' : '.',
157	v & CR_TLBACC_PFN_MASK));
158
159	/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
160	if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
161	int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
162	int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
163	int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
164	int g = (v & CR_TLBACC_G) ? 1 : 0;
165	int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
166	Nios2TLBEntry *entry =
167	&env->mmu.tlb[(way * cpu->tlb_num_ways) +
168	(vpn & env->mmu.tlb_entry_mask)];
169	uint32_t newTag = (vpn << 12) \| (g << 11) \| (valid << 10) \| pid;
170	uint32_t newData = v & (CR_TLBACC_C \| CR_TLBACC_R \| CR_TLBACC_W \|
171	CR_TLBACC_X \| CR_TLBACC_PFN_MASK);
172
173	if ((entry->tag != newTag) \|\| (entry->data != newData)) {
174	if (entry->tag & (1 << 10)) {
175	/* Flush existing entry */
176	MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n",
177	entry->tag & TARGET_PAGE_MASK));
178	tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
179	}
180	entry->tag = newTag;
181	entry->data = newData;
182	MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n",
183	(way * cpu->tlb_num_ways) +
184	(vpn & env->mmu.tlb_entry_mask),
185	entry->tag, entry->data));
186	}
187	/* Auto-increment tlbmisc.WAY */
188	env->regs[CR_TLBMISC] =
189	(env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) \|
190	(((way + 1) & (cpu->tlb_num_ways - 1)) <<
191	CR_TLBMISC_WAY_SHIFT);
192	}
193
194	/* Writes to TLBACC don't change the read-back value */
195	env->mmu.tlbacc_wr = v;
196	break;
197
198	case CR_TLBMISC:
199	MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n",
200	v >> CR_TLBMISC_WAY_SHIFT,
201	(v & CR_TLBMISC_RD) ? 'R' : '.',
202	(v & CR_TLBMISC_WR) ? 'W' : '.',
203	(v & CR_TLBMISC_DBL) ? '2' : '.',
204	(v & CR_TLBMISC_BAD) ? 'B' : '.',
205	(v & CR_TLBMISC_PERM) ? 'P' : '.',
206	(v & CR_TLBMISC_D) ? 'D' : '.',
207	(v & CR_TLBMISC_PID_MASK) >> 4));
208
209	if ((v & CR_TLBMISC_PID_MASK) !=
210	(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
211	mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
212	CR_TLBMISC_PID_SHIFT);
213	}
214	/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
215	if (v & CR_TLBMISC_RD) {
216	int way = (v >> CR_TLBMISC_WAY_SHIFT);
217	int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
218	Nios2TLBEntry *entry =
219	&env->mmu.tlb[(way * cpu->tlb_num_ways) +
220	(vpn & env->mmu.tlb_entry_mask)];
221
222	env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
223	env->regs[CR_TLBACC] \|= entry->data;
224	env->regs[CR_TLBACC] \|= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
225	env->regs[CR_TLBMISC] =
226	(v & ~CR_TLBMISC_PID_MASK) \|
227	((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
228	CR_TLBMISC_PID_SHIFT);
229	env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
230	env->regs[CR_PTEADDR] \|= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
231	MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, "
232	"tlbacc %08X, tlbmisc %08X, pteaddr %08X\n",
233	way, vpn, entry->tag, entry->data,
234	env->regs[CR_TLBACC], env->regs[CR_TLBMISC],
235	env->regs[CR_PTEADDR]));
236	} else {
237	env->regs[CR_TLBMISC] = v;
238	}
239
240	env->mmu.tlbmisc_wr = v;
241	break;
242
243	case CR_PTEADDR:
244	MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n",
245	v >> CR_PTEADDR_PTBASE_SHIFT,
246	(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT));
247
248	/* Writes to PTEADDR don't change the read-back VPN value */
249	env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) \|
250	(env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
251	env->mmu.pteaddr_wr = v;
252	break;
253
254	default:
255	break;
256	}
257	}
258
259	void mmu_init(CPUNios2State *env)
260	{
261	Nios2CPU *cpu = nios2_env_get_cpu(env);
262	Nios2MMU *mmu = &env->mmu;
263
264	MMU_LOG(qemu_log("mmu_init\n"));
265
266	mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
267	mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
268	}
269
270	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUNios2State env)
271	{
272	Nios2CPU *cpu = nios2_env_get_cpu(env);
273	int i;
274
275	cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n",
276	cpu->tlb_num_ways, cpu->tlb_num_entries,
277	cpu->pid_num_bits);
278
279	for (i = 0; i < cpu->tlb_num_entries; i++) {
280	Nios2TLBEntry *entry = &env->mmu.tlb[i];
281	cpu_fprintf(f, "TLB[%d] = %08X %08X %c VPN %05X "
282	"PID %02X %c PFN %05X %c%c%c%c\n",
283	i, entry->tag, entry->data,
284	(entry->tag & (1 << 10)) ? 'V' : '-',
285	entry->tag >> 12,
286	entry->tag & ((1 << cpu->pid_num_bits) - 1),
287	(entry->tag & (1 << 11)) ? 'G' : '-',
288	entry->data & CR_TLBACC_PFN_MASK,
289	(entry->data & CR_TLBACC_C) ? 'C' : '-',
290	(entry->data & CR_TLBACC_R) ? 'R' : '-',
291	(entry->data & CR_TLBACC_W) ? 'W' : '-',
292	(entry->data & CR_TLBACC_X) ? 'X' : '-');
293	}
294	}
295
296	#endif /* !CONFIG_USER_ONLY */