]> Git Repo - qemu.git/blame - hw/unin_pci.c
unin_pci: QOM'ify UniNorth PCI host bridges
[qemu.git] / hw / unin_pci.c
CommitLineData
502a5395
PB
1/*
2 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5fafdf24 5 *
502a5395
PB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB
24#include "hw.h"
25#include "ppc_mac.h"
26#include "pci.h"
4f5e19e6 27#include "pci_host.h"
87ecb68b 28
f3902383
BS
29/* debug UniNorth */
30//#define DEBUG_UNIN
31
32#ifdef DEBUG_UNIN
001faf32
BS
33#define UNIN_DPRINTF(fmt, ...) \
34 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383 35#else
001faf32 36#define UNIN_DPRINTF(fmt, ...)
f3902383
BS
37#endif
38
fa0be69a
AG
39static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
40
57fd7b7f
AF
41#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
42#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
43#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
44#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
45
46#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
48#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
49 OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
50#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
51 OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
52#define U3_AGP_HOST_BRIDGE(obj) \
53 OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
54
2e29bd04 55typedef struct UNINState {
2e29bd04 56 PCIHostState host_state;
57fd7b7f 57
46f3069c
BS
58 MemoryRegion pci_mmio;
59 MemoryRegion pci_hole;
2e29bd04 60} UNINState;
502a5395 61
d2b59317 62static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395 63{
fa0be69a
AG
64 int retval;
65 int devfn = pci_dev->devfn & 0x00FFFFFF;
66
67 retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
68
69 return retval;
d2b59317
PB
70}
71
5d4e84c8 72static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317 73{
5d4e84c8
JQ
74 qemu_irq *pic = opaque;
75
fa0be69a
AG
76 UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
77 unin_irq_line[irq_num], level);
78 qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395
PB
79}
80
d86f0e32
AG
81static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
82{
83 uint32_t retval;
84
85 if (reg & (1u << 31)) {
86 /* XXX OpenBIOS compatibility hack */
87 retval = reg | (addr & 3);
88 } else if (reg & 1) {
89 /* CFA1 style */
90 retval = (reg & ~7u) | (addr & 7);
91 } else {
92 uint32_t slot, func;
93
94 /* Grab CFA0 style values */
95 slot = ffs(reg & 0xfffff800) - 1;
96 func = (reg >> 8) & 7;
97
98 /* ... and then convert them to x86 format */
99 /* config pointer */
100 retval = (reg & (0xff - 7)) | (addr & 7);
101 /* slot */
102 retval |= slot << 11;
103 /* fn */
104 retval |= func << 8;
105 }
106
107
108 UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
109 reg, addr, retval);
110
111 return retval;
112}
113
d0ed8076
AK
114static void unin_data_write(void *opaque, target_phys_addr_t addr,
115 uint64_t val, unsigned len)
d86f0e32 116{
d0ed8076
AK
117 UNINState *s = opaque;
118 UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
119 addr, len, val);
d86f0e32
AG
120 pci_data_write(s->host_state.bus,
121 unin_get_config_reg(s->host_state.config_reg, addr),
122 val, len);
123}
124
d0ed8076
AK
125static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
126 unsigned len)
d86f0e32 127{
d0ed8076 128 UNINState *s = opaque;
d86f0e32
AG
129 uint32_t val;
130
131 val = pci_data_read(s->host_state.bus,
132 unin_get_config_reg(s->host_state.config_reg, addr),
133 len);
d0ed8076
AK
134 UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
135 addr, len, val);
d86f0e32
AG
136 return val;
137}
138
d0ed8076
AK
139static const MemoryRegionOps unin_data_ops = {
140 .read = unin_data_read,
141 .write = unin_data_write,
142 .endianness = DEVICE_LITTLE_ENDIAN,
143};
144
81a322d4 145static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 146{
ff452ace 147 PCIHostState *h;
502a5395
PB
148
149 /* Use values found on a real PowerMac */
150 /* Uninorth main bus */
ff452ace 151 h = FROM_SYSBUS(PCIHostState, dev);
502a5395 152
57fd7b7f
AF
153 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
154 dev, "pci-conf-idx", 0x1000);
155 memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
d0ed8076 156 "pci-conf-data", 0x1000);
57fd7b7f
AF
157 sysbus_init_mmio(dev, &h->conf_mem);
158 sysbus_init_mmio(dev, &h->data_mem);
2e29bd04 159
81a322d4 160 return 0;
2e29bd04
BS
161}
162
d0ed8076 163
0f921197
AG
164static int pci_u3_agp_init_device(SysBusDevice *dev)
165{
ff452ace 166 PCIHostState *h;
0f921197
AG
167
168 /* Uninorth U3 AGP bus */
ff452ace 169 h = FROM_SYSBUS(PCIHostState, dev);
0f921197 170
57fd7b7f
AF
171 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
172 dev, "pci-conf-idx", 0x1000);
173 memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
d0ed8076 174 "pci-conf-data", 0x1000);
57fd7b7f
AF
175 sysbus_init_mmio(dev, &h->conf_mem);
176 sysbus_init_mmio(dev, &h->data_mem);
0f921197 177
0f921197
AG
178 return 0;
179}
180
81a322d4 181static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 182{
ff452ace 183 PCIHostState *h;
2e29bd04
BS
184
185 /* Uninorth AGP bus */
ff452ace 186 h = FROM_SYSBUS(PCIHostState, dev);
57fd7b7f
AF
187
188 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
189 dev, "pci-conf-idx", 0x1000);
190 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
191 dev, "pci-conf-data", 0x1000);
192 sysbus_init_mmio(dev, &h->conf_mem);
193 sysbus_init_mmio(dev, &h->data_mem);
81a322d4 194 return 0;
2e29bd04
BS
195}
196
81a322d4 197static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 198{
ff452ace 199 PCIHostState *h;
2e29bd04
BS
200
201 /* Uninorth internal bus */
ff452ace 202 h = FROM_SYSBUS(PCIHostState, dev);
57fd7b7f
AF
203
204 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
205 dev, "pci-conf-idx", 0x1000);
206 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
207 dev, "pci-conf-data", 0x1000);
208 sysbus_init_mmio(dev, &h->conf_mem);
209 sysbus_init_mmio(dev, &h->data_mem);
81a322d4 210 return 0;
2e29bd04
BS
211}
212
aee97b84
AK
213PCIBus *pci_pmac_init(qemu_irq *pic,
214 MemoryRegion *address_space_mem,
215 MemoryRegion *address_space_io)
2e29bd04
BS
216{
217 DeviceState *dev;
218 SysBusDevice *s;
ff452ace 219 PCIHostState *h;
2e29bd04
BS
220 UNINState *d;
221
222 /* Use values found on a real PowerMac */
223 /* Uninorth main bus */
57fd7b7f 224 dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33 225 qdev_init_nofail(dev);
57fd7b7f 226 s = SYS_BUS_DEVICE(dev);
ff452ace 227 h = FROM_SYSBUS(PCIHostState, s);
57fd7b7f 228 d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
46f3069c
BS
229 memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
230 memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
231 0x80000000ULL, 0x70000000ULL);
232 memory_region_add_subregion(address_space_mem, 0x80000000ULL,
233 &d->pci_hole);
234
57fd7b7f
AF
235 h->bus = pci_register_bus(dev, "pci",
236 pci_unin_set_irq, pci_unin_map_irq,
237 pic,
238 &d->pci_mmio,
239 address_space_io,
240 PCI_DEVFN(11, 0), 4);
2e29bd04 241
60398748 242#if 0
57fd7b7f 243 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748 244#endif
2e29bd04
BS
245
246 sysbus_mmio_map(s, 0, 0xf2800000);
247 sysbus_mmio_map(s, 1, 0xf2c00000);
248
249 /* DEC 21154 bridge */
250#if 0
251 /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f 252 pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04
BS
253#endif
254
255 /* Uninorth AGP bus */
57fd7b7f
AF
256 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
257 dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2 258 qdev_init_nofail(dev);
57fd7b7f 259 s = SYS_BUS_DEVICE(dev);
d27d06f2
BS
260 sysbus_mmio_map(s, 0, 0xf0800000);
261 sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04
BS
262
263 /* Uninorth internal bus */
264#if 0
265 /* XXX: not needed for now */
57fd7b7f 266 pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987 267 "uni-north-internal-pci");
57fd7b7f 268 dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2 269 qdev_init_nofail(dev);
57fd7b7f 270 s = SYS_BUS_DEVICE(dev);
d27d06f2
BS
271 sysbus_mmio_map(s, 0, 0xf4800000);
272 sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04
BS
273#endif
274
57fd7b7f 275 return h->bus;
2e29bd04
BS
276}
277
aee97b84
AK
278PCIBus *pci_pmac_u3_init(qemu_irq *pic,
279 MemoryRegion *address_space_mem,
280 MemoryRegion *address_space_io)
0f921197
AG
281{
282 DeviceState *dev;
283 SysBusDevice *s;
ff452ace 284 PCIHostState *h;
0f921197
AG
285 UNINState *d;
286
287 /* Uninorth AGP bus */
288
57fd7b7f 289 dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197 290 qdev_init_nofail(dev);
57fd7b7f 291 s = SYS_BUS_DEVICE(dev);
ff452ace 292 h = FROM_SYSBUS(PCIHostState, s);
57fd7b7f 293 d = U3_AGP_HOST_BRIDGE(dev);
0f921197 294
46f3069c
BS
295 memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
296 memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
297 0x80000000ULL, 0x70000000ULL);
298 memory_region_add_subregion(address_space_mem, 0x80000000ULL,
299 &d->pci_hole);
300
57fd7b7f
AF
301 h->bus = pci_register_bus(dev, "pci",
302 pci_unin_set_irq, pci_unin_map_irq,
303 pic,
304 &d->pci_mmio,
305 address_space_io,
306 PCI_DEVFN(11, 0), 4);
0f921197
AG
307
308 sysbus_mmio_map(s, 0, 0xf0800000);
309 sysbus_mmio_map(s, 1, 0xf0c00000);
310
57fd7b7f 311 pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197 312
57fd7b7f 313 return h->bus;
0f921197
AG
314}
315
81a322d4 316static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04 317{
502a5395
PB
318 d->config[0x0C] = 0x08; // cache_line_size
319 d->config[0x0D] = 0x10; // latency_timer
502a5395 320 d->config[0x34] = 0x00; // capabilities_pointer
81a322d4 321 return 0;
2e29bd04 322}
502a5395 323
81a322d4 324static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04 325{
502a5395
PB
326 d->config[0x0C] = 0x08; // cache_line_size
327 d->config[0x0D] = 0x10; // latency_timer
502a5395 328 // d->config[0x34] = 0x80; // capabilities_pointer
81a322d4 329 return 0;
2e29bd04 330}
502a5395 331
0f921197
AG
332static int u3_agp_pci_host_init(PCIDevice *d)
333{
0f921197
AG
334 /* cache line size */
335 d->config[0x0C] = 0x08;
336 /* latency timer */
337 d->config[0x0D] = 0x10;
0f921197
AG
338 return 0;
339}
340
81a322d4 341static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04 342{
502a5395
PB
343 d->config[0x0C] = 0x08; // cache_line_size
344 d->config[0x0D] = 0x10; // latency_timer
502a5395 345 d->config[0x34] = 0x00; // capabilities_pointer
81a322d4 346 return 0;
2e29bd04
BS
347}
348
40021f08
AL
349static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
350{
351 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
352
353 k->init = unin_main_pci_host_init;
354 k->vendor_id = PCI_VENDOR_ID_APPLE;
355 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
356 k->revision = 0x00;
357 k->class_id = PCI_CLASS_BRIDGE_HOST;
358}
359
4240abff 360static const TypeInfo unin_main_pci_host_info = {
40021f08 361 .name = "uni-north-pci",
39bffca2
AL
362 .parent = TYPE_PCI_DEVICE,
363 .instance_size = sizeof(PCIDevice),
40021f08 364 .class_init = unin_main_pci_host_class_init,
2e29bd04
BS
365};
366
40021f08
AL
367static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
368{
369 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
370
371 k->init = u3_agp_pci_host_init;
372 k->vendor_id = PCI_VENDOR_ID_APPLE;
373 k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
374 k->revision = 0x00;
375 k->class_id = PCI_CLASS_BRIDGE_HOST;
376}
377
4240abff 378static const TypeInfo u3_agp_pci_host_info = {
40021f08 379 .name = "u3-agp",
39bffca2
AL
380 .parent = TYPE_PCI_DEVICE,
381 .instance_size = sizeof(PCIDevice),
40021f08 382 .class_init = u3_agp_pci_host_class_init,
0f921197
AG
383};
384
40021f08
AL
385static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
386{
387 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
388
389 k->init = unin_agp_pci_host_init;
390 k->vendor_id = PCI_VENDOR_ID_APPLE;
391 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
392 k->revision = 0x00;
393 k->class_id = PCI_CLASS_BRIDGE_HOST;
394}
395
4240abff 396static const TypeInfo unin_agp_pci_host_info = {
40021f08 397 .name = "uni-north-agp",
39bffca2
AL
398 .parent = TYPE_PCI_DEVICE,
399 .instance_size = sizeof(PCIDevice),
40021f08 400 .class_init = unin_agp_pci_host_class_init,
2e29bd04
BS
401};
402
40021f08
AL
403static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
404{
405 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
406
407 k->init = unin_internal_pci_host_init;
408 k->vendor_id = PCI_VENDOR_ID_APPLE;
409 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
410 k->revision = 0x00;
411 k->class_id = PCI_CLASS_BRIDGE_HOST;
412}
413
4240abff 414static const TypeInfo unin_internal_pci_host_info = {
40021f08 415 .name = "uni-north-internal-pci",
39bffca2
AL
416 .parent = TYPE_PCI_DEVICE,
417 .instance_size = sizeof(PCIDevice),
40021f08 418 .class_init = unin_internal_pci_host_class_init,
2e29bd04
BS
419};
420
999e12bb
AL
421static void pci_unin_main_class_init(ObjectClass *klass, void *data)
422{
423 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
424
425 sbc->init = pci_unin_main_init_device;
426}
427
4240abff 428static const TypeInfo pci_unin_main_info = {
57fd7b7f 429 .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
39bffca2
AL
430 .parent = TYPE_SYS_BUS_DEVICE,
431 .instance_size = sizeof(UNINState),
432 .class_init = pci_unin_main_class_init,
70f9c987
AF
433};
434
999e12bb
AL
435static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
436{
437 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
438
439 sbc->init = pci_u3_agp_init_device;
440}
441
4240abff 442static const TypeInfo pci_u3_agp_info = {
57fd7b7f 443 .name = TYPE_U3_AGP_HOST_BRIDGE,
39bffca2
AL
444 .parent = TYPE_SYS_BUS_DEVICE,
445 .instance_size = sizeof(UNINState),
446 .class_init = pci_u3_agp_class_init,
70f9c987
AF
447};
448
999e12bb
AL
449static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
450{
451 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
452
453 sbc->init = pci_unin_agp_init_device;
454}
455
4240abff 456static const TypeInfo pci_unin_agp_info = {
57fd7b7f 457 .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
39bffca2
AL
458 .parent = TYPE_SYS_BUS_DEVICE,
459 .instance_size = sizeof(UNINState),
460 .class_init = pci_unin_agp_class_init,
70f9c987
AF
461};
462
999e12bb
AL
463static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
464{
465 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
466
467 sbc->init = pci_unin_internal_init_device;
468}
469
4240abff 470static const TypeInfo pci_unin_internal_info = {
57fd7b7f 471 .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
39bffca2
AL
472 .parent = TYPE_SYS_BUS_DEVICE,
473 .instance_size = sizeof(UNINState),
474 .class_init = pci_unin_internal_class_init,
70f9c987
AF
475};
476
83f7d43a 477static void unin_register_types(void)
2e29bd04 478{
39bffca2
AL
479 type_register_static(&unin_main_pci_host_info);
480 type_register_static(&u3_agp_pci_host_info);
481 type_register_static(&unin_agp_pci_host_info);
482 type_register_static(&unin_internal_pci_host_info);
483
484 type_register_static(&pci_unin_main_info);
485 type_register_static(&pci_u3_agp_info);
486 type_register_static(&pci_unin_agp_info);
487 type_register_static(&pci_unin_internal_info);
502a5395 488}
2e29bd04 489
83f7d43a 490type_init(unin_register_types)
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