[qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#define CPUState struct CPUARMState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7
#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
#define EXCP_STREX          10

#define ARMV7M_EXCP_RESET   1
#define ARMV7M_EXCP_NMI     2
#define ARMV7M_EXCP_HARD    3
#define ARMV7M_EXCP_MEM     4
#define ARMV7M_EXCP_BUS     5
#define ARMV7M_EXCP_USAGE   6
#define ARMV7M_EXCP_SVC     11
#define ARMV7M_EXCP_DEBUG   12
#define ARMV7M_EXCP_PENDSV  14
#define ARMV7M_EXCP_SYSTICK 15

typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

struct arm_boot_info;

#define NB_MMU_MODES 2

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];

    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];

    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NF; /* N is bit 31. All other bits are undefined.  */
    uint32_t ZF; /* Z set if zero.  */
    uint32_t QF; /* 0 or 1 */
    uint32_t GE; /* cpsr[19:16] */
    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c0_ccsid[16]; /* Cache size.  */
        uint32_t c0_clid; /* Cache level.  */
        uint32_t c0_cssel; /* Cache size selection.  */
        uint32_t c0_c1[8]; /* Feature registers.  */
        uint32_t c0_c2[8]; /* Instruction set registers.  */
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base0; /* MMU translation table base 0.  */
        uint32_t c2_base1; /* MMU translation table base 1.  */
        uint32_t c2_control; /* MMU translation table base control.  */
        uint32_t c2_mask; /* MMU translation table base selection mask.  */
        uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c13_tls1; /* User RW Thread register.  */
        uint32_t c13_tls2; /* User RO Thread register.  */
        uint32_t c13_tls3; /* Privileged Thread register.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    struct {
        uint32_t other_sp;
        uint32_t vecbase;
        uint32_t basepri;
        uint32_t control;
        int current_sp;
        int exception;
        int pending_exception;
        void *nvic;
    } v7m;

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];

    /* Thumb-2 EE state.  */
    uint32_t teecr;
    uint32_t teehbr;

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* Callback for vectored interrupt controller.  */
    int (*get_irq_vector)(struct CPUARMState *);
    void *irq_opaque;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[32];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* scratch space when Tn are not sufficient.  */
        uint32_t scratch[8];

        float_status fp_status;
    } vfp;
    uint32_t exclusive_addr;
    uint32_t exclusive_val;
    uint32_t exclusive_high;
#if defined(CONFIG_USER_ONLY)
    uint32_t exclusive_test;
    uint32_t exclusive_info;
#endif

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */
    struct arm_boot_info *boot_info;
} CPUARMState;

CPUARMState *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmuu);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault

void cpu_lock(void);
void cpu_unlock(void);
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
  env->cp15.c13_tls2 = newtls;
}

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
#define CPSR_GE (0xf << 16)
#define CPSR_RESERVED (0xf << 20)
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_V (1 << 28)
#define CPSR_C (1 << 29)
#define CPSR_Z (1 << 30)
#define CPSR_N (1 << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
/* Bits writable in user mode.  */
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)

/* Return the current CPSR value.  */
uint32_t cpsr_read(CPUARMState *env);
/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);

/* Return the current xPSR value.  */
static inline uint32_t xpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->ZF == 0);
    return (env->NF & 0x80000000) | (ZF << 30)
        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | env->v7m.exception;
}

/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & (1 << 24))
        env->thumb = ((val & (1 << 24)) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & 0x1ff) {
        env->v7m.exception = val & 0x1ff;
    }
}

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_MVFR1   6
#define ARM_VFP_MVFR0   7
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_V6,
    ARM_FEATURE_V6K,
    ARM_FEATURE_V7,
    ARM_FEATURE_THUMB2,
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_VFP3,
    ARM_FEATURE_VFP_FP16,
    ARM_FEATURE_NEON,
    ARM_FEATURE_DIV,
    ARM_FEATURE_M, /* Microcontroller profile.  */
    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
    ARM_FEATURE_THUMB2EE
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

/* Interface between CPU and Interrupt controller.  */
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
   conventional cores (ie. Application or Realtime profile).  */

#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
#define ARM_CPUID(env) (env->cp15.c0_cpuid)

#define ARM_CPUID_ARM1026     0x4106a262
#define ARM_CPUID_ARM926      0x41069265
#define ARM_CPUID_ARM946      0x41059461
#define ARM_CPUID_TI915T      0x54029152
#define ARM_CPUID_TI925T      0x54029252
#define ARM_CPUID_PXA250      0x69052100
#define ARM_CPUID_PXA255      0x69052d00
#define ARM_CPUID_PXA260      0x69052903
#define ARM_CPUID_PXA261      0x69052d05
#define ARM_CPUID_PXA262      0x69052d06
#define ARM_CPUID_PXA270      0x69054110
#define ARM_CPUID_PXA270_A0   0x69054110
#define ARM_CPUID_PXA270_A1   0x69054111
#define ARM_CPUID_PXA270_B0   0x69054112
#define ARM_CPUID_PXA270_B1   0x69054113
#define ARM_CPUID_PXA270_C0   0x69054114
#define ARM_CPUID_PXA270_C5   0x69054117
#define ARM_CPUID_ARM1136     0x4117b363
#define ARM_CPUID_ARM1136_R2  0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8    0x410fc080
#define ARM_CPUID_CORTEXA9    0x410fc090
#define ARM_CPUID_CORTEXM3    0x410fc231
#define ARM_CPUID_ANY         0xffffffff

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

#define CPU_SAVE_VERSION 2

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regs[13] = newsp;
    env->regs[0] = 0;
}
#endif

#include "cpu-all.h"
#include "exec-all.h"

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->regs[15] = tb->pc;
}

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->regs[15];
    *cs_base = 0;
    *flags = env->thumb | (env->vfp.vec_len << 1)
            | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
        *flags |= (1 << 6);
    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
        *flags |= (1 << 7);
}

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af FB	18	*/
	19	#ifndef CPU_ARM_H
	20	#define CPU_ARM_H
	21
3cf1e035 FB	22	#define TARGET_LONG_BITS 32
3cf1e035 FB	23
9042c0e2 TS	24	#define ELF_MACHINE EM_ARM
9042c0e2 TS	25
c2764719 PB	26	#define CPUState struct CPUARMState
c2764719 PB	27
2c0262af FB	28	#include "cpu-defs.h"
2c0262af FB	29
53cd6637 FB	30	#include "softfloat.h"
53cd6637 FB	31
1fddef4b FB	32	#define TARGET_HAS_ICE 1
1fddef4b FB	33
b8a9e8f1 FB	34	#define EXCP_UDEF 1 /* undefined instruction */
	35	#define EXCP_SWI 2 /* software interrupt */
	36	#define EXCP_PREFETCH_ABORT 3
	37	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	38	#define EXCP_IRQ 5
b5ff1b31 FB	39	#define EXCP_FIQ 6
06c949e6	40	#define EXCP_BKPT 7
9ee6e8bb	41	#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
fbb4a2e3	42	#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
426f5abc	43	#define EXCP_STREX 10
9ee6e8bb PB	44
	45	#define ARMV7M_EXCP_RESET 1
	46	#define ARMV7M_EXCP_NMI 2
	47	#define ARMV7M_EXCP_HARD 3
	48	#define ARMV7M_EXCP_MEM 4
	49	#define ARMV7M_EXCP_BUS 5
	50	#define ARMV7M_EXCP_USAGE 6
	51	#define ARMV7M_EXCP_SVC 11
	52	#define ARMV7M_EXCP_DEBUG 12
	53	#define ARMV7M_EXCP_PENDSV 14
	54	#define ARMV7M_EXCP_SYSTICK 15
2c0262af	55
c1713132 AZ	56	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	57	int srcreg, int operand, uint32_t value);
	58	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	59	int dstreg, int operand);
	60
f93eb9ff AZ	61	struct arm_boot_info;
f93eb9ff AZ	62
6ebbf390 JM	63	#define NB_MMU_MODES 2
6ebbf390 JM	64
b7bcbe95 FB	65	/* We currently assume float and double are IEEE single and double
	66	precision respectively.
	67	Doing runtime conversions is tricky because VFP registers may contain
	68	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	69	s<2n> maps to the least significant half of d<n>
	70	s<2n+1> maps to the most significant half of d<n>
	71	*/
b7bcbe95	72
2c0262af	73	typedef struct CPUARMState {
b5ff1b31	74	/* Regs for current mode. */
2c0262af	75	uint32_t regs[16];
b5ff1b31	76	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	77	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	78	the whole CPSR. */
	79	uint32_t uncached_cpsr;
	80	uint32_t spsr;
	81
	82	/* Banked registers. */
	83	uint32_t banked_spsr[6];
	84	uint32_t banked_r13[6];
	85	uint32_t banked_r14[6];
3b46e624	86
b5ff1b31 FB	87	/* These hold r8-r12. */
	88	uint32_t usr_regs[5];
	89	uint32_t fiq_regs[5];
3b46e624	90
2c0262af FB	91	/* cpsr flag cache for faster execution */
	92	uint32_t CF; /* 0 or 1 */
	93	uint32_t VF; /* V is the bit 31. All other bits are undefined */
6fbe23d5 PB	94	uint32_t NF; /* N is bit 31. All other bits are undefined. */
6fbe23d5 PB	95	uint32_t ZF; /* Z set if zero. */
99c475ab	96	uint32_t QF; /* 0 or 1 */
9ee6e8bb	97	uint32_t GE; /* cpsr[19:16] */
b26eefb6	98	uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
9ee6e8bb	99	uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
2c0262af	100
b5ff1b31 FB	101	/* System control coprocessor (cp15) */
b5ff1b31 FB	102	struct {
40f137e1	103	uint32_t c0_cpuid;
c1713132	104	uint32_t c0_cachetype;
a49ea279 PB	105	uint32_t c0_ccsid[16]; /* Cache size. */
	106	uint32_t c0_clid; /* Cache level. */
	107	uint32_t c0_cssel; /* Cache size selection. */
9ee6e8bb PB	108	uint32_t c0_c1[8]; /* Feature registers. */
9ee6e8bb PB	109	uint32_t c0_c2[8]; /* Instruction set registers. */
b5ff1b31 FB	110	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	111	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	112	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
9ee6e8bb PB	113	uint32_t c2_base0; /* MMU translation table base 0. */
9ee6e8bb PB	114	uint32_t c2_base1; /* MMU translation table base 1. */
b2fa1797 PB	115	uint32_t c2_control; /* MMU translation table base control. */
	116	uint32_t c2_mask; /* MMU translation table base selection mask. */
	117	uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
ce819861 PB	118	uint32_t c2_data; /* MPU data cachable bits. */
	119	uint32_t c2_insn; /* MPU instruction cachable bits. */
	120	uint32_t c3; /* MMU domain access control register
	121	MPU write buffer control. */
b5ff1b31 FB	122	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	123	uint32_t c5_data;
ce819861	124	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	125	uint32_t c6_insn; /* Fault address registers. */
	126	uint32_t c6_data;
	127	uint32_t c9_insn; /* Cache lockdown registers. */
	128	uint32_t c9_data;
	129	uint32_t c13_fcse; /* FCSE PID. */
	130	uint32_t c13_context; /* Context ID. */
9ee6e8bb PB	131	uint32_t c13_tls1; /* User RW Thread register. */
	132	uint32_t c13_tls2; /* User RO Thread register. */
	133	uint32_t c13_tls3; /* Privileged Thread register. */
c1713132	134	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	135	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	136	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	137	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	138	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	139	} cp15;
40f137e1	140
9ee6e8bb PB	141	struct {
	142	uint32_t other_sp;
	143	uint32_t vecbase;
	144	uint32_t basepri;
	145	uint32_t control;
	146	int current_sp;
	147	int exception;
	148	int pending_exception;
	149	void *nvic;
	150	} v7m;
	151
c1713132 AZ	152	/* Coprocessor IO used by peripherals */
	153	struct {
	154	ARMReadCPFunc *cp_read;
	155	ARMWriteCPFunc *cp_write;
	156	void *opaque;
	157	} cp[15];
	158
fe1479c3 PB	159	/* Thumb-2 EE state. */
	160	uint32_t teecr;
	161	uint32_t teehbr;
	162
40f137e1 PB	163	/* Internal CPU feature flags. */
	164	uint32_t features;
	165
9ee6e8bb PB	166	/* Callback for vectored interrupt controller. */
	167	int (get_irq_vector)(struct CPUARMState );
	168	void *irq_opaque;
	169
b7bcbe95 FB	170	/* VFP coprocessor state. */
b7bcbe95 FB	171	struct {
9ee6e8bb	172	float64 regs[32];
b7bcbe95	173
40f137e1	174	uint32_t xregs[16];
b7bcbe95 FB	175	/* We store these fpcsr fields separately for convenience. */
	176	int vec_len;
	177	int vec_stride;
	178
9ee6e8bb PB	179	/* scratch space when Tn are not sufficient. */
9ee6e8bb PB	180	uint32_t scratch[8];
3b46e624	181
53cd6637	182	float_status fp_status;
b7bcbe95	183	} vfp;
426f5abc PB	184	uint32_t exclusive_addr;
	185	uint32_t exclusive_val;
	186	uint32_t exclusive_high;
9ee6e8bb	187	#if defined(CONFIG_USER_ONLY)
426f5abc PB	188	uint32_t exclusive_test;
426f5abc PB	189	uint32_t exclusive_info;
9ee6e8bb	190	#endif
b7bcbe95	191
18c9b560 AZ	192	/* iwMMXt coprocessor state. */
	193	struct {
	194	uint64_t regs[16];
	195	uint64_t val;
	196
	197	uint32_t cregs[16];
	198	} iwmmxt;
	199
ce4defa0 PB	200	#if defined(CONFIG_USER_ONLY)
	201	/* For usermode syscall translation. */
	202	int eabi;
	203	#endif
	204
a316d335 FB	205	CPU_COMMON
a316d335 FB	206
9d551997	207	/* These fields after the common ones so they are preserved on reset. */
f93eb9ff	208	struct arm_boot_info *boot_info;
2c0262af FB	209	} CPUARMState;
2c0262af FB	210
aaed909a	211	CPUARMState cpu_arm_init(const char cpu_model);
b26eefb6	212	void arm_translate_init(void);
2c0262af FB	213	int cpu_arm_exec(CPUARMState *s);
2c0262af FB	214	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	215	void do_interrupt(CPUARMState *);
b5ff1b31 FB	216	void switch_mode(CPUARMState *, int);
9ee6e8bb	217	uint32_t do_arm_semihosting(CPUARMState *env);
b5ff1b31	218
2c0262af FB	219	/* you can call this signal handler from your SIGBUS and SIGSEGV
	220	signal handlers to inform the virtual CPU of exceptions. non zero
	221	is returned if the signal was handled by the virtual CPU. */
5fafdf24	222	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af	223	void *puc);
84a031c6 AJ	224	int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
84a031c6 AJ	225	int mmu_idx, int is_softmuu);
0b5c1ce8	226	#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
2c0262af	227
9ee6e8bb PB	228	void cpu_lock(void);
9ee6e8bb PB	229	void cpu_unlock(void);
fbb4a2e3 PB	230	static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
	231	{
	232	env->cp15.c13_tls2 = newtls;
	233	}
9ee6e8bb	234
b5ff1b31 FB	235	#define CPSR_M (0x1f)
	236	#define CPSR_T (1 << 5)
	237	#define CPSR_F (1 << 6)
	238	#define CPSR_I (1 << 7)
	239	#define CPSR_A (1 << 8)
	240	#define CPSR_E (1 << 9)
	241	#define CPSR_IT_2_7 (0xfc00)
9ee6e8bb PB	242	#define CPSR_GE (0xf << 16)
9ee6e8bb PB	243	#define CPSR_RESERVED (0xf << 20)
b5ff1b31 FB	244	#define CPSR_J (1 << 24)
	245	#define CPSR_IT_0_1 (3 << 25)
	246	#define CPSR_Q (1 << 27)
9ee6e8bb PB	247	#define CPSR_V (1 << 28)
	248	#define CPSR_C (1 << 29)
	249	#define CPSR_Z (1 << 30)
	250	#define CPSR_N (1 << 31)
	251	#define CPSR_NZCV (CPSR_N \| CPSR_Z \| CPSR_C \| CPSR_V)
	252
	253	#define CPSR_IT (CPSR_IT_0_1 \| CPSR_IT_2_7)
	254	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_GE \| CPSR_IT \| CPSR_Q \| CPSR_NZCV)
	255	/* Bits writable in user mode. */
	256	#define CPSR_USER (CPSR_NZCV \| CPSR_Q \| CPSR_GE)
	257	/* Execution state bits. MRS read as zero, MSR writes ignored. */
	258	#define CPSR_EXEC (CPSR_T \| CPSR_IT \| CPSR_J)
b5ff1b31	259
b5ff1b31	260	/* Return the current CPSR value. */
2f4a40e5 AZ	261	uint32_t cpsr_read(CPUARMState *env);
	262	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	263	void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
9ee6e8bb PB	264
	265	/* Return the current xPSR value. */
	266	static inline uint32_t xpsr_read(CPUARMState *env)
	267	{
	268	int ZF;
6fbe23d5 PB	269	ZF = (env->ZF == 0);
6fbe23d5 PB	270	return (env->NF & 0x80000000) \| (ZF << 30)
9ee6e8bb PB	271	\| (env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	272	\| (env->thumb << 24) \| ((env->condexec_bits & 3) << 25)
	273	\| ((env->condexec_bits & 0xfc) << 8)
	274	\| env->v7m.exception;
b5ff1b31 FB	275	}
b5ff1b31 FB	276
9ee6e8bb PB	277	/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
	278	static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	279	{
9ee6e8bb	280	if (mask & CPSR_NZCV) {
6fbe23d5 PB	281	env->ZF = (~val) & CPSR_Z;
6fbe23d5 PB	282	env->NF = val;
9ee6e8bb PB	283	env->CF = (val >> 29) & 1;
	284	env->VF = (val << 3) & 0x80000000;
	285	}
	286	if (mask & CPSR_Q)
	287	env->QF = ((val & CPSR_Q) != 0);
	288	if (mask & (1 << 24))
	289	env->thumb = ((val & (1 << 24)) != 0);
	290	if (mask & CPSR_IT_0_1) {
	291	env->condexec_bits &= ~3;
	292	env->condexec_bits \|= (val >> 25) & 3;
	293	}
	294	if (mask & CPSR_IT_2_7) {
	295	env->condexec_bits &= 3;
	296	env->condexec_bits \|= (val >> 8) & 0xfc;
	297	}
	298	if (mask & 0x1ff) {
	299	env->v7m.exception = val & 0x1ff;
	300	}
	301	}
	302
b5ff1b31 FB	303	enum arm_cpu_mode {
	304	ARM_CPU_MODE_USR = 0x10,
	305	ARM_CPU_MODE_FIQ = 0x11,
	306	ARM_CPU_MODE_IRQ = 0x12,
	307	ARM_CPU_MODE_SVC = 0x13,
	308	ARM_CPU_MODE_ABT = 0x17,
	309	ARM_CPU_MODE_UND = 0x1b,
	310	ARM_CPU_MODE_SYS = 0x1f
	311	};
	312
40f137e1 PB	313	/* VFP system registers. */
	314	#define ARM_VFP_FPSID 0
	315	#define ARM_VFP_FPSCR 1
9ee6e8bb PB	316	#define ARM_VFP_MVFR1 6
9ee6e8bb PB	317	#define ARM_VFP_MVFR0 7
40f137e1 PB	318	#define ARM_VFP_FPEXC 8
	319	#define ARM_VFP_FPINST 9
	320	#define ARM_VFP_FPINST2 10
	321
18c9b560 AZ	322	/* iwMMXt coprocessor control registers. */
	323	#define ARM_IWMMXT_wCID 0
	324	#define ARM_IWMMXT_wCon 1
	325	#define ARM_IWMMXT_wCSSF 2
	326	#define ARM_IWMMXT_wCASF 3
	327	#define ARM_IWMMXT_wCGR0 8
	328	#define ARM_IWMMXT_wCGR1 9
	329	#define ARM_IWMMXT_wCGR2 10
	330	#define ARM_IWMMXT_wCGR3 11
	331
40f137e1 PB	332	enum arm_features {
40f137e1 PB	333	ARM_FEATURE_VFP,
c1713132 AZ	334	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	335	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	336	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
9ee6e8bb PB	337	ARM_FEATURE_V6,
	338	ARM_FEATURE_V6K,
	339	ARM_FEATURE_V7,
	340	ARM_FEATURE_THUMB2,
c3d2689d	341	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
9ee6e8bb	342	ARM_FEATURE_VFP3,
60011498	343	ARM_FEATURE_VFP_FP16,
9ee6e8bb PB	344	ARM_FEATURE_NEON,
	345	ARM_FEATURE_DIV,
	346	ARM_FEATURE_M, /* Microcontroller profile. */
fe1479c3 PB	347	ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
fe1479c3 PB	348	ARM_FEATURE_THUMB2EE
40f137e1 PB	349	};
	350
	351	static inline int arm_feature(CPUARMState *env, int feature)
	352	{
	353	return (env->features & (1u << feature)) != 0;
	354	}
	355
c732abe2	356	void arm_cpu_list(FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
40f137e1	357
9ee6e8bb PB	358	/* Interface between CPU and Interrupt controller. */
	359	void armv7m_nvic_set_pending(void *opaque, int irq);
	360	int armv7m_nvic_acknowledge_irq(void *opaque);
	361	void armv7m_nvic_complete_irq(void *opaque, int irq);
	362
c1713132 AZ	363	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	364	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	365	void *opaque);
	366
9ee6e8bb PB	367	/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
	368	Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
	369	conventional cores (ie. Application or Realtime profile). */
	370
	371	#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
	372	#define ARM_CPUID(env) (env->cp15.c0_cpuid)
	373
	374	#define ARM_CPUID_ARM1026 0x4106a262
	375	#define ARM_CPUID_ARM926 0x41069265
	376	#define ARM_CPUID_ARM946 0x41059461
	377	#define ARM_CPUID_TI915T 0x54029152
	378	#define ARM_CPUID_TI925T 0x54029252
	379	#define ARM_CPUID_PXA250 0x69052100
	380	#define ARM_CPUID_PXA255 0x69052d00
	381	#define ARM_CPUID_PXA260 0x69052903
	382	#define ARM_CPUID_PXA261 0x69052d05
	383	#define ARM_CPUID_PXA262 0x69052d06
	384	#define ARM_CPUID_PXA270 0x69054110
	385	#define ARM_CPUID_PXA270_A0 0x69054110
	386	#define ARM_CPUID_PXA270_A1 0x69054111
	387	#define ARM_CPUID_PXA270_B0 0x69054112
	388	#define ARM_CPUID_PXA270_B1 0x69054113
	389	#define ARM_CPUID_PXA270_C0 0x69054114
	390	#define ARM_CPUID_PXA270_C5 0x69054117
	391	#define ARM_CPUID_ARM1136 0x4117b363
827df9f3	392	#define ARM_CPUID_ARM1136_R2 0x4107b362
9ee6e8bb PB	393	#define ARM_CPUID_ARM11MPCORE 0x410fb022
9ee6e8bb PB	394	#define ARM_CPUID_CORTEXA8 0x410fc080
10055562	395	#define ARM_CPUID_CORTEXA9 0x410fc090
9ee6e8bb PB	396	#define ARM_CPUID_CORTEXM3 0x410fc231
9ee6e8bb PB	397	#define ARM_CPUID_ANY 0xffffffff
40f137e1	398
b5ff1b31	399	#if defined(CONFIG_USER_ONLY)
2c0262af	400	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	401	#else
	402	/* The ARM MMU allows 1k pages. */
	403	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	404	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	405	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	406	#endif
9467d44c	407
52705890 RH	408	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	409	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	410
9467d44c TS	411	#define cpu_init cpu_arm_init
	412	#define cpu_exec cpu_arm_exec
	413	#define cpu_gen_code cpu_arm_gen_code
	414	#define cpu_signal_handler cpu_arm_signal_handler
c732abe2	415	#define cpu_list arm_cpu_list
9467d44c	416
ffe47d33	417	#define CPU_SAVE_VERSION 2
9ee6e8bb	418
6ebbf390 JM	419	/* MMU modes definitions */
	420	#define MMU_MODE0_SUFFIX _kernel
	421	#define MMU_MODE1_SUFFIX _user
	422	#define MMU_USER_IDX 1
	423	static inline int cpu_mmu_index (CPUState *env)
	424	{
	425	return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
	426	}
	427
6e68e076 PB	428	#if defined(CONFIG_USER_ONLY)
	429	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	430	{
f8ed7070	431	if (newsp)
6e68e076 PB	432	env->regs[13] = newsp;
	433	env->regs[0] = 0;
	434	}
	435	#endif
	436
2c0262af	437	#include "cpu-all.h"
622ed360 AL	438	#include "exec-all.h"
	439
	440	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	441	{
	442	env->regs[15] = tb->pc;
	443	}
2c0262af	444
6b917547 AL	445	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	446	target_ulong cs_base, int flags)
	447	{
	448	*pc = env->regs[15];
	449	*cs_base = 0;
	450	*flags = env->thumb \| (env->vfp.vec_len << 1)
	451	\| (env->vfp.vec_stride << 4) \| (env->condexec_bits << 8);
	452	if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
	453	*flags \|= (1 << 6);
	454	if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
	455	*flags \|= (1 << 7);
	456	}
	457
2c0262af	458	#endif