[qemu.git] / hw / ppc / spapr_cpu_core.c

/*
 * sPAPR CPU core device, acts as container of CPU thread devices.
 *
 * Copyright (C) 2016 Bharata B Rao <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#include "hw/cpu/core.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "target-ppc/cpu.h"
#include "hw/ppc/spapr.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
#include "target-ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target-ppc/mmu-hash64.h"
#include "sysemu/numa.h"

static void spapr_cpu_reset(void *opaque)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;

    cpu_reset(cs);

    /* All CPUs start halted.  CPU0 is unhalted from the machine level
     * reset code and the rest are explicitly started up by the guest
     * using an RTAS call */
    cs->halted = 1;

    env->spr[SPR_HIOR] = 0;

    ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
                                &error_fatal);
}

static void spapr_cpu_destroy(PowerPCCPU *cpu)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());

    xics_cpu_destroy(spapr->xics, cpu);
    qemu_unregister_reset(spapr_cpu_reset, cpu);
}

void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    int i;

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);

    /* Enable PAPR mode in TCG or KVM */
    cpu_ppc_set_papr(cpu);

    if (cpu->max_compat) {
        Error *local_err = NULL;

        ppc_set_compat(cpu, cpu->max_compat, &local_err);
        if (local_err) {
            error_propagate(errp, local_err);
            return;
        }
    }

    /* Set NUMA node for the added CPUs  */
    i = numa_get_node_for_cpu(cs->cpu_index);
    if (i < nb_numa_nodes) {
            cs->numa_node = i;
    }

    xics_cpu_setup(spapr->xics, cpu);

    qemu_register_reset(spapr_cpu_reset, cpu);
    spapr_cpu_reset(cpu);
}

/*
 * Return the sPAPR CPU core type for @model which essentially is the CPU
 * model specified with -cpu cmdline option.
 */
char *spapr_get_cpu_core_type(const char *model)
{
    char *core_type;
    gchar **model_pieces = g_strsplit(model, ",", 2);

    core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);

    /* Check whether it exists or whether we have to look up an alias name */
    if (!object_class_by_name(core_type)) {
        const char *realmodel;

        g_free(core_type);
        core_type = NULL;
        realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
        if (realmodel) {
            core_type = spapr_get_cpu_core_type(realmodel);
        }
    }

    g_strfreev(model_pieces);
    return core_type;
}

static void spapr_core_release(DeviceState *dev, void *opaque)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
    const char *typename = object_class_get_name(scc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    CPUCore *cc = CPU_CORE(dev);
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        void *obj = sc->threads + i * size;
        DeviceState *dev = DEVICE(obj);
        CPUState *cs = CPU(dev);
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        spapr_cpu_destroy(cpu);
        cpu_remove_sync(cs);
        object_unparent(obj);
    }

    spapr->cores[cc->core_id / smp_threads] = NULL;

    g_free(sc->threads);
    object_unparent(OBJECT(dev));
}

void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
                       Error **errp)
{
    CPUCore *cc = CPU_CORE(dev);
    int smt = kvmppc_smt_threads();
    int index = cc->core_id / smp_threads;
    sPAPRDRConnector *drc =
        spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;

    if (index == 0) {
        error_setg(errp, "Boot CPU core may not be unplugged");
        return;
    }

    g_assert(drc);

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_hotplug_req_remove_by_index(drc);
}

void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                     Error **errp)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(dev);
    CPUState *cs = CPU(core->threads);
    sPAPRDRConnector *drc;
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;
    void *fdt = NULL;
    int fdt_offset = 0;
    int index = cc->core_id / smp_threads;
    int smt = kvmppc_smt_threads();

    drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
    spapr->cores[index] = OBJECT(dev);

    g_assert(drc);

    /*
     * Setup CPU DT entries only for hotplugged CPUs. For boot time or
     * coldplugged CPUs DT entries are setup in spapr_build_fdt().
     */
    if (dev->hotplugged) {
        fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
    }

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
    if (local_err) {
        g_free(fdt);
        spapr->cores[index] = NULL;
        error_propagate(errp, local_err);
        return;
    }

    if (dev->hotplugged) {
        /*
         * Send hotplug notification interrupt to the guest only in case
         * of hotplugged CPUs.
         */
        spapr_hotplug_req_add_by_index(drc);
    } else {
        /*
         * Set the right DRC states for cold plugged CPU.
         */
        drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
        drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
    }
}

void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                         Error **errp)
{
    MachineState *machine = MACHINE(OBJECT(hotplug_dev));
    MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    int spapr_max_cores = max_cpus / smp_threads;
    int index;
    Error *local_err = NULL;
    CPUCore *cc = CPU_CORE(dev);
    char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
    const char *type = object_get_typename(OBJECT(dev));

    if (!mc->query_hotpluggable_cpus) {
        error_setg(&local_err, "CPU hotplug not supported for this machine");
        goto out;
    }

    if (strcmp(base_core_type, type)) {
        error_setg(&local_err, "CPU core type should be %s", base_core_type);
        goto out;
    }

    if (cc->nr_threads != smp_threads) {
        error_setg(&local_err, "threads must be %d", smp_threads);
        goto out;
    }

    if (cc->core_id % smp_threads) {
        error_setg(&local_err, "invalid core id %d", cc->core_id);
        goto out;
    }

    index = cc->core_id / smp_threads;
    if (index < 0 || index >= spapr_max_cores) {
        error_setg(&local_err, "core id %d out of range", cc->core_id);
        goto out;
    }

    if (spapr->cores[index]) {
        error_setg(&local_err, "core %d already populated", cc->core_id);
        goto out;
    }

out:
    g_free(base_core_type);
    error_propagate(errp, local_err);
}

static void spapr_cpu_core_realize_child(Object *child, Error **errp)
{
    Error *local_err = NULL;
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    CPUState *cs = CPU(child);
    PowerPCCPU *cpu = POWERPC_CPU(cs);

    object_property_set_bool(child, true, "realized", &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_cpu_init(spapr, cpu, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }
}

static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    const char *typename = object_class_get_name(scc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    Error *local_err = NULL;
    void *obj;
    int i, j;

    sc->threads = g_malloc0(size * cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        char id[32];
        CPUState *cs;

        obj = sc->threads + i * size;

        object_initialize(obj, size, typename);
        cs = CPU(obj);
        cs->cpu_index = cc->core_id + i;
        snprintf(id, sizeof(id), "thread[%d]", i);
        object_property_add_child(OBJECT(sc), id, obj, &local_err);
        if (local_err) {
            goto err;
        }
        object_unref(obj);
    }

    for (j = 0; j < cc->nr_threads; j++) {
        obj = sc->threads + j * size;

        spapr_cpu_core_realize_child(obj, &local_err);
        if (local_err) {
            goto err;
        }
    }
    return;

err:
    while (--i >= 0) {
        obj = sc->threads + i * size;
        object_unparent(obj);
    }
    g_free(sc->threads);
    error_propagate(errp, local_err);
}

static const char *spapr_core_models[] = {
    /* 970 */
    "970_v2.2",

    /* 970MP variants */
    "970MP_v1.0",
    "970mp_v1.0",
    "970MP_v1.1",
    "970mp_v1.1",

    /* POWER5+ */
    "POWER5+_v2.1",

    /* POWER7 */
    "POWER7_v2.3",

    /* POWER7+ */
    "POWER7+_v2.1",

    /* POWER8 */
    "POWER8_v2.0",

    /* POWER8E */
    "POWER8E_v2.1",

    /* POWER8NVL */
    "POWER8NVL_v1.0",
};

void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);

    dc->realize = spapr_cpu_core_realize;
    scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
    g_assert(scc->cpu_class);
}

static const TypeInfo spapr_cpu_core_type_info = {
    .name = TYPE_SPAPR_CPU_CORE,
    .parent = TYPE_CPU_CORE,
    .abstract = true,
    .instance_size = sizeof(sPAPRCPUCore),
    .class_size = sizeof(sPAPRCPUCoreClass),
};

static void spapr_cpu_core_register_types(void)
{
    int i;

    type_register_static(&spapr_cpu_core_type_info);

    for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
        TypeInfo type_info = {
            .parent = TYPE_SPAPR_CPU_CORE,
            .instance_size = sizeof(sPAPRCPUCore),
            .class_init = spapr_cpu_core_class_init,
            .class_data = (void *) spapr_core_models[i],
        };

        type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
                                         spapr_core_models[i]);
        type_register(&type_info);
        g_free((void *)type_info.name);
    }
}

type_init(spapr_cpu_core_register_types)
Commit	Line	Data
3b542549 BR	1	/*
	2	* sPAPR CPU core device, acts as container of CPU thread devices.
	3	*
	4	* Copyright (C) 2016 Bharata B Rao <[email protected]>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9	#include "hw/cpu/core.h"
	10	#include "hw/ppc/spapr_cpu_core.h"
	11	#include "target-ppc/cpu.h"
	12	#include "hw/ppc/spapr.h"
	13	#include "hw/boards.h"
	14	#include "qapi/error.h"
a9c94277	15	#include "sysemu/cpus.h"
3b542549	16	#include "target-ppc/kvm_ppc.h"
afd10a0f BR	17	#include "hw/ppc/ppc.h"
afd10a0f BR	18	#include "target-ppc/mmu-hash64.h"
a9c94277	19	#include "sysemu/numa.h"
afd10a0f BR	20
	21	static void spapr_cpu_reset(void *opaque)
	22	{
	23	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	24	PowerPCCPU *cpu = opaque;
	25	CPUState *cs = CPU(cpu);
	26	CPUPPCState *env = &cpu->env;
	27
	28	cpu_reset(cs);
	29
	30	/* All CPUs start halted. CPU0 is unhalted from the machine level
	31	* reset code and the rest are explicitly started up by the guest
	32	* using an RTAS call */
	33	cs->halted = 1;
	34
	35	env->spr[SPR_HIOR] = 0;
	36
	37	ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
	38	&error_fatal);
	39	}
	40
6f4b5c3e BR	41	static void spapr_cpu_destroy(PowerPCCPU *cpu)
	42	{
	43	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	44
27f24582	45	xics_cpu_destroy(spapr->xics, cpu);
6f4b5c3e BR	46	qemu_unregister_reset(spapr_cpu_reset, cpu);
	47	}
	48
afd10a0f BR	49	void spapr_cpu_init(sPAPRMachineState spapr, PowerPCCPU cpu, Error **errp)
	50	{
	51	CPUPPCState *env = &cpu->env;
af81cf32 BR	52	CPUState *cs = CPU(cpu);
af81cf32 BR	53	int i;
afd10a0f BR	54
	55	/* Set time-base frequency to 512 MHz */
	56	cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
	57
	58	/* Enable PAPR mode in TCG or KVM */
	59	cpu_ppc_set_papr(cpu);
	60
	61	if (cpu->max_compat) {
	62	Error *local_err = NULL;
	63
	64	ppc_set_compat(cpu, cpu->max_compat, &local_err);
	65	if (local_err) {
	66	error_propagate(errp, local_err);
	67	return;
	68	}
	69	}
	70
af81cf32	71	/* Set NUMA node for the added CPUs */
6bea1ddf IM	72	i = numa_get_node_for_cpu(cs->cpu_index);
6bea1ddf IM	73	if (i < nb_numa_nodes) {
af81cf32	74	cs->numa_node = i;
af81cf32 BR	75	}
af81cf32 BR	76
27f24582	77	xics_cpu_setup(spapr->xics, cpu);
afd10a0f BR	78
afd10a0f BR	79	qemu_register_reset(spapr_cpu_reset, cpu);
af81cf32	80	spapr_cpu_reset(cpu);
afd10a0f	81	}
3b542549	82
94a94e4c BR	83	/*
	84	* Return the sPAPR CPU core type for @model which essentially is the CPU
	85	* model specified with -cpu cmdline option.
	86	*/
	87	char spapr_get_cpu_core_type(const char model)
	88	{
	89	char *core_type;
	90	gchar **model_pieces = g_strsplit(model, ",", 2);
	91
	92	core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
4babfaf0 TH	93
	94	/* Check whether it exists or whether we have to look up an alias name */
	95	if (!object_class_by_name(core_type)) {
	96	const char *realmodel;
	97
	98	g_free(core_type);
e17a8779 GK	99	core_type = NULL;
e17a8779 GK	100	realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
4babfaf0	101	if (realmodel) {
e17a8779	102	core_type = spapr_get_cpu_core_type(realmodel);
4babfaf0	103	}
4babfaf0 TH	104	}
4babfaf0 TH	105
e17a8779	106	g_strfreev(model_pieces);
94a94e4c BR	107	return core_type;
	108	}
	109
6f4b5c3e BR	110	static void spapr_core_release(DeviceState dev, void opaque)
	111	{
	112	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
7ebaf795 BR	113	sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
7ebaf795 BR	114	const char *typename = object_class_get_name(scc->cpu_class);
6f4b5c3e BR	115	size_t size = object_type_get_instance_size(typename);
6f4b5c3e BR	116	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
6f4b5c3e	117	CPUCore *cc = CPU_CORE(dev);
6f4b5c3e BR	118	int i;
	119
	120	for (i = 0; i < cc->nr_threads; i++) {
	121	void obj = sc->threads + i size;
	122	DeviceState *dev = DEVICE(obj);
	123	CPUState *cs = CPU(dev);
	124	PowerPCCPU *cpu = POWERPC_CPU(cs);
	125
	126	spapr_cpu_destroy(cpu);
	127	cpu_remove_sync(cs);
	128	object_unparent(obj);
	129	}
	130
12bf2d33	131	spapr->cores[cc->core_id / smp_threads] = NULL;
6f4b5c3e	132
8a1eb71b	133	g_free(sc->threads);
6f4b5c3e BR	134	object_unparent(OBJECT(dev));
	135	}
	136
	137	void spapr_core_unplug(HotplugHandler hotplug_dev, DeviceState dev,
	138	Error **errp)
	139	{
44d691f7	140	CPUCore *cc = CPU_CORE(dev);
12bf2d33 GK	141	int smt = kvmppc_smt_threads();
12bf2d33 GK	142	int index = cc->core_id / smp_threads;
6f4b5c3e	143	sPAPRDRConnector *drc =
12bf2d33	144	spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
6f4b5c3e BR	145	sPAPRDRConnectorClass *drck;
	146	Error *local_err = NULL;
	147
62be8b04 BR	148	if (index == 0) {
	149	error_setg(errp, "Boot CPU core may not be unplugged");
	150	return;
	151	}
	152
6f4b5c3e BR	153	g_assert(drc);
	154
	155	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	156	drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
	157	if (local_err) {
	158	error_propagate(errp, local_err);
	159	return;
	160	}
	161
	162	spapr_hotplug_req_remove_by_index(drc);
	163	}
	164
af81cf32 BR	165	void spapr_core_plug(HotplugHandler hotplug_dev, DeviceState dev,
	166	Error **errp)
	167	{
af81cf32 BR	168	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
	169	sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
	170	CPUCore *cc = CPU_CORE(dev);
	171	CPUState *cs = CPU(core->threads);
	172	sPAPRDRConnector *drc;
	173	sPAPRDRConnectorClass *drck;
	174	Error *local_err = NULL;
	175	void *fdt = NULL;
	176	int fdt_offset = 0;
12bf2d33	177	int index = cc->core_id / smp_threads;
af81cf32 BR	178	int smt = kvmppc_smt_threads();
af81cf32 BR	179
12bf2d33	180	drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
af81cf32 BR	181	spapr->cores[index] = OBJECT(dev);
af81cf32 BR	182
af81cf32 BR	183	g_assert(drc);
	184
	185	/*
	186	* Setup CPU DT entries only for hotplugged CPUs. For boot time or
997b6cfc	187	* coldplugged CPUs DT entries are setup in spapr_build_fdt().
af81cf32 BR	188	*/
	189	if (dev->hotplugged) {
	190	fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
	191	}
	192
	193	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	194	drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
	195	if (local_err) {
	196	g_free(fdt);
	197	spapr->cores[index] = NULL;
	198	error_propagate(errp, local_err);
	199	return;
	200	}
	201
	202	if (dev->hotplugged) {
	203	/*
	204	* Send hotplug notification interrupt to the guest only in case
	205	* of hotplugged CPUs.
	206	*/
	207	spapr_hotplug_req_add_by_index(drc);
	208	} else {
	209	/*
	210	* Set the right DRC states for cold plugged CPU.
	211	*/
	212	drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
	213	drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
	214	}
	215	}
	216
94a94e4c BR	217	void spapr_core_pre_plug(HotplugHandler hotplug_dev, DeviceState dev,
	218	Error **errp)
	219	{
	220	MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3c0c47e3	221	MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
94a94e4c BR	222	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
94a94e4c BR	223	int spapr_max_cores = max_cpus / smp_threads;
7cdd7613	224	int index;
94a94e4c BR	225	Error *local_err = NULL;
	226	CPUCore *cc = CPU_CORE(dev);
	227	char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
	228	const char *type = object_get_typename(OBJECT(dev));
	229
3c0c47e3	230	if (!mc->query_hotpluggable_cpus) {
c8721d35	231	error_setg(&local_err, "CPU hotplug not supported for this machine");
94a94e4c BR	232	goto out;
	233	}
	234
c8721d35 BR	235	if (strcmp(base_core_type, type)) {
c8721d35 BR	236	error_setg(&local_err, "CPU core type should be %s", base_core_type);
af81cf32 BR	237	goto out;
	238	}
	239
94a94e4c BR	240	if (cc->nr_threads != smp_threads) {
	241	error_setg(&local_err, "threads must be %d", smp_threads);
	242	goto out;
	243	}
	244
12bf2d33	245	if (cc->core_id % smp_threads) {
df3c286c	246	error_setg(&local_err, "invalid core id %d", cc->core_id);
94a94e4c BR	247	goto out;
	248	}
	249
12bf2d33	250	index = cc->core_id / smp_threads;
94a94e4c BR	251	if (index < 0 \|\| index >= spapr_max_cores) {
	252	error_setg(&local_err, "core id %d out of range", cc->core_id);
	253	goto out;
	254	}
	255
	256	if (spapr->cores[index]) {
	257	error_setg(&local_err, "core %d already populated", cc->core_id);
	258	goto out;
	259	}
	260
	261	out:
	262	g_free(base_core_type);
	263	error_propagate(errp, local_err);
	264	}
	265
7093645a	266	static void spapr_cpu_core_realize_child(Object child, Error *errp)
3b542549	267	{
7093645a	268	Error *local_err = NULL;
3b542549 BR	269	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	270	CPUState *cs = CPU(child);
	271	PowerPCCPU *cpu = POWERPC_CPU(cs);
	272
f11235b9 GK	273	object_property_set_bool(child, true, "realized", &local_err);
	274	if (local_err) {
	275	error_propagate(errp, local_err);
7093645a	276	return;
3b542549 BR	277	}
3b542549 BR	278
f11235b9 GK	279	spapr_cpu_init(spapr, cpu, &local_err);
	280	if (local_err) {
	281	error_propagate(errp, local_err);
7093645a	282	return;
3b542549	283	}
3b542549 BR	284	}
	285
	286	static void spapr_cpu_core_realize(DeviceState dev, Error *errp)
	287	{
	288	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
7ebaf795	289	sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
3b542549	290	CPUCore *cc = CPU_CORE(OBJECT(dev));
7ebaf795	291	const char *typename = object_class_get_name(scc->cpu_class);
3b542549 BR	292	size_t size = object_type_get_instance_size(typename);
3b542549 BR	293	Error *local_err = NULL;
7093645a BR	294	void *obj;
7093645a BR	295	int i, j;
3b542549 BR	296
	297	sc->threads = g_malloc0(size * cc->nr_threads);
	298	for (i = 0; i < cc->nr_threads; i++) {
	299	char id[32];
b63578bd IM	300	CPUState *cs;
b63578bd IM	301
7093645a	302	obj = sc->threads + i * size;
3b542549 BR	303
3b542549 BR	304	object_initialize(obj, size, typename);
b63578bd IM	305	cs = CPU(obj);
b63578bd IM	306	cs->cpu_index = cc->core_id + i;
3b542549 BR	307	snprintf(id, sizeof(id), "thread[%d]", i);
	308	object_property_add_child(OBJECT(sc), id, obj, &local_err);
	309	if (local_err) {
	310	goto err;
	311	}
8e758dee	312	object_unref(obj);
3b542549	313	}
7093645a BR	314
	315	for (j = 0; j < cc->nr_threads; j++) {
	316	obj = sc->threads + j * size;
	317
	318	spapr_cpu_core_realize_child(obj, &local_err);
	319	if (local_err) {
	320	goto err;
	321	}
3b542549	322	}
7093645a	323	return;
3b542549 BR	324
3b542549 BR	325	err:
dde35bc9	326	while (--i >= 0) {
3b542549 BR	327	obj = sc->threads + i * size;
3b542549 BR	328	object_unparent(obj);
3b542549 BR	329	}
	330	g_free(sc->threads);
	331	error_propagate(errp, local_err);
	332	}
	333
7ebaf795	334	static const char *spapr_core_models[] = {
4babfaf0	335	/* 970 */
7ebaf795	336	"970_v2.2",
ff461b8d	337
4babfaf0	338	/* 970MP variants */
7ebaf795 BR	339	"970MP_v1.0",
	340	"970mp_v1.0",
	341	"970MP_v1.1",
	342	"970mp_v1.1",
470f2157	343
4babfaf0	344	/* POWER5+ */
7ebaf795	345	"POWER5+_v2.1",
ff461b8d	346
4babfaf0	347	/* POWER7 */
7ebaf795	348	"POWER7_v2.3",
3b542549	349
4babfaf0	350	/* POWER7+ */
7ebaf795	351	"POWER7+_v2.1",
3b542549	352
4babfaf0	353	/* POWER8 */
7ebaf795	354	"POWER8_v2.0",
3b542549	355
4babfaf0	356	/* POWER8E */
7ebaf795	357	"POWER8E_v2.1",
3b542549	358
4babfaf0	359	/* POWER8NVL */
7ebaf795	360	"POWER8NVL_v1.0",
3b542549 BR	361	};
3b542549 BR	362
7ebaf795	363	void spapr_cpu_core_class_init(ObjectClass oc, void data)
3b542549	364	{
7ebaf795 BR	365	DeviceClass *dc = DEVICE_CLASS(oc);
	366	sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
	367
	368	dc->realize = spapr_cpu_core_realize;
	369	scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
	370	g_assert(scc->cpu_class);
3b542549 BR	371	}
	372
	373	static const TypeInfo spapr_cpu_core_type_info = {
	374	.name = TYPE_SPAPR_CPU_CORE,
	375	.parent = TYPE_CPU_CORE,
	376	.abstract = true,
	377	.instance_size = sizeof(sPAPRCPUCore),
7ebaf795	378	.class_size = sizeof(sPAPRCPUCoreClass),
3b542549 BR	379	};
	380
	381	static void spapr_cpu_core_register_types(void)
	382	{
7ebaf795	383	int i;
3b542549 BR	384
3b542549 BR	385	type_register_static(&spapr_cpu_core_type_info);
7ebaf795 BR	386
	387	for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
	388	TypeInfo type_info = {
	389	.parent = TYPE_SPAPR_CPU_CORE,
	390	.instance_size = sizeof(sPAPRCPUCore),
	391	.class_init = spapr_cpu_core_class_init,
	392	.class_data = (void *) spapr_core_models[i],
	393	};
	394
	395	type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
	396	spapr_core_models[i]);
	397	type_register(&type_info);
	398	g_free((void *)type_info.name);
3b542549 BR	399	}
	400	}
	401
	402	type_init(spapr_cpu_core_register_types)