[qemu.git] / hw / ppc / spapr_cpu_core.c

/*
 * sPAPR CPU core device, acts as container of CPU thread devices.
 *
 * Copyright (C) 2016 Bharata B Rao <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#include "hw/cpu/core.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "target-ppc/cpu.h"
#include "hw/ppc/spapr.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include <sysemu/cpus.h>
#include "target-ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target-ppc/mmu-hash64.h"
#include <sysemu/numa.h>

static void spapr_cpu_reset(void *opaque)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;

    cpu_reset(cs);

    /* All CPUs start halted.  CPU0 is unhalted from the machine level
     * reset code and the rest are explicitly started up by the guest
     * using an RTAS call */
    cs->halted = 1;

    env->spr[SPR_HIOR] = 0;

    ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
                                &error_fatal);
}

static void spapr_cpu_destroy(PowerPCCPU *cpu)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());

    xics_cpu_destroy(spapr->xics, cpu);
    qemu_unregister_reset(spapr_cpu_reset, cpu);
}

void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    int i;

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);

    /* Enable PAPR mode in TCG or KVM */
    cpu_ppc_set_papr(cpu);

    if (cpu->max_compat) {
        Error *local_err = NULL;

        ppc_set_compat(cpu, cpu->max_compat, &local_err);
        if (local_err) {
            error_propagate(errp, local_err);
            return;
        }
    }

    /* Set NUMA node for the added CPUs  */
    for (i = 0; i < nb_numa_nodes; i++) {
        if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) {
            cs->numa_node = i;
            break;
        }
    }

    xics_cpu_setup(spapr->xics, cpu);

    qemu_register_reset(spapr_cpu_reset, cpu);
    spapr_cpu_reset(cpu);
}

/*
 * Return the sPAPR CPU core type for @model which essentially is the CPU
 * model specified with -cpu cmdline option.
 */
char *spapr_get_cpu_core_type(const char *model)
{
    char *core_type;
    gchar **model_pieces = g_strsplit(model, ",", 2);

    core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
    g_strfreev(model_pieces);
    return core_type;
}

static void spapr_core_release(DeviceState *dev, void *opaque)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    const char *typename = object_class_get_name(sc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(dev);
    int smt = kvmppc_smt_threads();
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        void *obj = sc->threads + i * size;
        DeviceState *dev = DEVICE(obj);
        CPUState *cs = CPU(dev);
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        spapr_cpu_destroy(cpu);
        cpu_remove_sync(cs);
        object_unparent(obj);
    }

    spapr->cores[cc->core_id / smt] = NULL;

    g_free(core->threads);
    object_unparent(OBJECT(dev));
}

void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
                       Error **errp)
{
    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
    PowerPCCPU *cpu = POWERPC_CPU(core->threads);
    int id = ppc_get_vcpu_dt_id(cpu);
    sPAPRDRConnector *drc =
        spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, id);
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;

    g_assert(drc);

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_hotplug_req_remove_by_index(drc);
}

void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                     Error **errp)
{
    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev));
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(dev);
    CPUState *cs = CPU(core->threads);
    sPAPRDRConnector *drc;
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;
    void *fdt = NULL;
    int fdt_offset = 0;
    int index;
    int smt = kvmppc_smt_threads();

    drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, cc->core_id);
    index = cc->core_id / smt;
    spapr->cores[index] = OBJECT(dev);

    if (!smc->dr_cpu_enabled) {
        /*
         * This is a cold plugged CPU core but the machine doesn't support
         * DR. So skip the hotplug path ensuring that the core is brought
         * up online with out an associated DR connector.
         */
        return;
    }

    g_assert(drc);

    /*
     * Setup CPU DT entries only for hotplugged CPUs. For boot time or
     * coldplugged CPUs DT entries are setup in spapr_finalize_fdt().
     */
    if (dev->hotplugged) {
        fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
    }

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
    if (local_err) {
        g_free(fdt);
        spapr->cores[index] = NULL;
        error_propagate(errp, local_err);
        return;
    }

    if (dev->hotplugged) {
        /*
         * Send hotplug notification interrupt to the guest only in case
         * of hotplugged CPUs.
         */
        spapr_hotplug_req_add_by_index(drc);
    } else {
        /*
         * Set the right DRC states for cold plugged CPU.
         */
        drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
        drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
    }
}

void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                         Error **errp)
{
    MachineState *machine = MACHINE(OBJECT(hotplug_dev));
    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev));
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    int spapr_max_cores = max_cpus / smp_threads;
    int index;
    int smt = kvmppc_smt_threads();
    Error *local_err = NULL;
    CPUCore *cc = CPU_CORE(dev);
    char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
    const char *type = object_get_typename(OBJECT(dev));

    if (strcmp(base_core_type, type)) {
        error_setg(&local_err, "CPU core type should be %s", base_core_type);
        goto out;
    }

    if (!smc->dr_cpu_enabled && dev->hotplugged) {
        error_setg(&local_err, "CPU hotplug not supported for this machine");
        goto out;
    }

    if (cc->nr_threads != smp_threads) {
        error_setg(&local_err, "threads must be %d", smp_threads);
        goto out;
    }

    if (cc->core_id % smt) {
        error_setg(&local_err, "invalid core id %d\n", cc->core_id);
        goto out;
    }

    index = cc->core_id / smt;
    if (index < 0 || index >= spapr_max_cores) {
        error_setg(&local_err, "core id %d out of range", cc->core_id);
        goto out;
    }

    if (spapr->cores[index]) {
        error_setg(&local_err, "core %d already populated", cc->core_id);
        goto out;
    }

out:
    g_free(base_core_type);
    error_propagate(errp, local_err);
}

static int spapr_cpu_core_realize_child(Object *child, void *opaque)
{
    Error **errp = opaque, *local_err = NULL;
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    CPUState *cs = CPU(child);
    PowerPCCPU *cpu = POWERPC_CPU(cs);

    object_property_set_bool(child, true, "realized", &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return 1;
    }

    spapr_cpu_init(spapr, cpu, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return 1;
    }
    return 0;
}

static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    const char *typename = object_class_get_name(sc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    Error *local_err = NULL;
    Object *obj;
    int i;

    sc->threads = g_malloc0(size * cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        char id[32];
        void *obj = sc->threads + i * size;

        object_initialize(obj, size, typename);
        snprintf(id, sizeof(id), "thread[%d]", i);
        object_property_add_child(OBJECT(sc), id, obj, &local_err);
        if (local_err) {
            goto err;
        }
        object_unref(obj);
    }
    object_child_foreach(OBJECT(dev), spapr_cpu_core_realize_child, &local_err);
    if (local_err) {
        goto err;
    } else {
        return;
    }

err:
    while (--i >= 0) {
        obj = sc->threads + i * size;
        object_unparent(obj);
    }
    g_free(sc->threads);
    error_propagate(errp, local_err);
}

static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    dc->realize = spapr_cpu_core_realize;
}

/*
 * instance_init routines from different flavours of sPAPR CPU cores.
 */
#define SPAPR_CPU_CORE_INITFN(_type, _fname) \
static void glue(glue(spapr_cpu_core_, _fname), _initfn(Object *obj)) \
{ \
    sPAPRCPUCore *core = SPAPR_CPU_CORE(obj); \
    char *name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, stringify(_type)); \
    ObjectClass *oc = object_class_by_name(name); \
    g_assert(oc); \
    g_free((void *)name); \
    core->cpu_class = oc; \
}

SPAPR_CPU_CORE_INITFN(970mp_v1.0, 970MP_v10);
SPAPR_CPU_CORE_INITFN(970mp_v1.1, 970MP_v11);
SPAPR_CPU_CORE_INITFN(970_v2.2, 970);
SPAPR_CPU_CORE_INITFN(POWER5+_v2.1, POWER5plus);
SPAPR_CPU_CORE_INITFN(POWER7_v2.3, POWER7);
SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus);
SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8);
SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E);
SPAPR_CPU_CORE_INITFN(POWER8NVL_v1.0, POWER8NVL);

typedef struct SPAPRCoreInfo {
    const char *name;
    void (*initfn)(Object *obj);
} SPAPRCoreInfo;

static const SPAPRCoreInfo spapr_cores[] = {
    /* 970 and aliaes */
    { .name = "970_v2.2", .initfn = spapr_cpu_core_970_initfn },
    { .name = "970", .initfn = spapr_cpu_core_970_initfn },

    /* 970MP variants and aliases */
    { .name = "970MP_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
    { .name = "970mp_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
    { .name = "970MP_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
    { .name = "970mp_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
    { .name = "970mp", .initfn = spapr_cpu_core_970MP_v11_initfn },

    /* POWER5 and aliases */
    { .name = "POWER5+_v2.1", .initfn = spapr_cpu_core_POWER5plus_initfn },
    { .name = "POWER5+", .initfn = spapr_cpu_core_POWER5plus_initfn },

    /* POWER7 and aliases */
    { .name = "POWER7_v2.3", .initfn = spapr_cpu_core_POWER7_initfn },
    { .name = "POWER7", .initfn = spapr_cpu_core_POWER7_initfn },

    /* POWER7+ and aliases */
    { .name = "POWER7+_v2.1", .initfn = spapr_cpu_core_POWER7plus_initfn },
    { .name = "POWER7+", .initfn = spapr_cpu_core_POWER7plus_initfn },

    /* POWER8 and aliases */
    { .name = "POWER8_v2.0", .initfn = spapr_cpu_core_POWER8_initfn },
    { .name = "POWER8", .initfn = spapr_cpu_core_POWER8_initfn },
    { .name = "power8", .initfn = spapr_cpu_core_POWER8_initfn },

    /* POWER8E and aliases */
    { .name = "POWER8E_v2.1", .initfn = spapr_cpu_core_POWER8E_initfn },
    { .name = "POWER8E", .initfn = spapr_cpu_core_POWER8E_initfn },

    /* POWER8NVL and aliases */
    { .name = "POWER8NVL_v1.0", .initfn = spapr_cpu_core_POWER8NVL_initfn },
    { .name = "POWER8NVL", .initfn = spapr_cpu_core_POWER8NVL_initfn },

    { .name = NULL }
};

static void spapr_cpu_core_register(const SPAPRCoreInfo *info)
{
    TypeInfo type_info = {
        .parent = TYPE_SPAPR_CPU_CORE,
        .instance_size = sizeof(sPAPRCPUCore),
        .instance_init = info->initfn,
    };

    type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, info->name);
    type_register(&type_info);
    g_free((void *)type_info.name);
}

static const TypeInfo spapr_cpu_core_type_info = {
    .name = TYPE_SPAPR_CPU_CORE,
    .parent = TYPE_CPU_CORE,
    .abstract = true,
    .instance_size = sizeof(sPAPRCPUCore),
    .class_init = spapr_cpu_core_class_init,
};

static void spapr_cpu_core_register_types(void)
{
    const SPAPRCoreInfo *info = spapr_cores;

    type_register_static(&spapr_cpu_core_type_info);
    while (info->name) {
        spapr_cpu_core_register(info);
        info++;
    }
}

type_init(spapr_cpu_core_register_types)
Commit	Line	Data
3b542549 BR	1	/*
	2	* sPAPR CPU core device, acts as container of CPU thread devices.
	3	*
	4	* Copyright (C) 2016 Bharata B Rao <[email protected]>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9	#include "hw/cpu/core.h"
	10	#include "hw/ppc/spapr_cpu_core.h"
	11	#include "target-ppc/cpu.h"
	12	#include "hw/ppc/spapr.h"
	13	#include "hw/boards.h"
	14	#include "qapi/error.h"
	15	#include <sysemu/cpus.h>
	16	#include "target-ppc/kvm_ppc.h"
afd10a0f BR	17	#include "hw/ppc/ppc.h"
	18	#include "target-ppc/mmu-hash64.h"
	19	#include <sysemu/numa.h>
	20
	21	static void spapr_cpu_reset(void *opaque)
	22	{
	23	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	24	PowerPCCPU *cpu = opaque;
	25	CPUState *cs = CPU(cpu);
	26	CPUPPCState *env = &cpu->env;
	27
	28	cpu_reset(cs);
	29
	30	/* All CPUs start halted. CPU0 is unhalted from the machine level
	31	* reset code and the rest are explicitly started up by the guest
	32	* using an RTAS call */
	33	cs->halted = 1;
	34
	35	env->spr[SPR_HIOR] = 0;
	36
	37	ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
	38	&error_fatal);
	39	}
	40
6f4b5c3e BR	41	static void spapr_cpu_destroy(PowerPCCPU *cpu)
	42	{
	43	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	44
27f24582	45	xics_cpu_destroy(spapr->xics, cpu);
6f4b5c3e BR	46	qemu_unregister_reset(spapr_cpu_reset, cpu);
	47	}
	48
afd10a0f BR	49	void spapr_cpu_init(sPAPRMachineState spapr, PowerPCCPU cpu, Error **errp)
	50	{
	51	CPUPPCState *env = &cpu->env;
af81cf32 BR	52	CPUState *cs = CPU(cpu);
af81cf32 BR	53	int i;
afd10a0f BR	54
	55	/* Set time-base frequency to 512 MHz */
	56	cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
	57
	58	/* Enable PAPR mode in TCG or KVM */
	59	cpu_ppc_set_papr(cpu);
	60
	61	if (cpu->max_compat) {
	62	Error *local_err = NULL;
	63
	64	ppc_set_compat(cpu, cpu->max_compat, &local_err);
	65	if (local_err) {
	66	error_propagate(errp, local_err);
	67	return;
	68	}
	69	}
	70
af81cf32 BR	71	/* Set NUMA node for the added CPUs */
	72	for (i = 0; i < nb_numa_nodes; i++) {
	73	if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) {
	74	cs->numa_node = i;
	75	break;
	76	}
	77	}
	78
27f24582	79	xics_cpu_setup(spapr->xics, cpu);
afd10a0f BR	80
afd10a0f BR	81	qemu_register_reset(spapr_cpu_reset, cpu);
af81cf32	82	spapr_cpu_reset(cpu);
afd10a0f	83	}
3b542549	84
94a94e4c BR	85	/*
	86	* Return the sPAPR CPU core type for @model which essentially is the CPU
	87	* model specified with -cpu cmdline option.
	88	*/
	89	char spapr_get_cpu_core_type(const char model)
	90	{
	91	char *core_type;
	92	gchar **model_pieces = g_strsplit(model, ",", 2);
	93
	94	core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
	95	g_strfreev(model_pieces);
	96	return core_type;
	97	}
	98
6f4b5c3e BR	99	static void spapr_core_release(DeviceState dev, void opaque)
	100	{
	101	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
	102	const char *typename = object_class_get_name(sc->cpu_class);
	103	size_t size = object_type_get_instance_size(typename);
	104	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	105	sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
	106	CPUCore *cc = CPU_CORE(dev);
	107	int smt = kvmppc_smt_threads();
	108	int i;
	109
	110	for (i = 0; i < cc->nr_threads; i++) {
	111	void obj = sc->threads + i size;
	112	DeviceState *dev = DEVICE(obj);
	113	CPUState *cs = CPU(dev);
	114	PowerPCCPU *cpu = POWERPC_CPU(cs);
	115
	116	spapr_cpu_destroy(cpu);
	117	cpu_remove_sync(cs);
	118	object_unparent(obj);
	119	}
	120
	121	spapr->cores[cc->core_id / smt] = NULL;
	122
	123	g_free(core->threads);
	124	object_unparent(OBJECT(dev));
	125	}
	126
	127	void spapr_core_unplug(HotplugHandler hotplug_dev, DeviceState dev,
	128	Error **errp)
	129	{
	130	sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
	131	PowerPCCPU *cpu = POWERPC_CPU(core->threads);
	132	int id = ppc_get_vcpu_dt_id(cpu);
	133	sPAPRDRConnector *drc =
	134	spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, id);
	135	sPAPRDRConnectorClass *drck;
	136	Error *local_err = NULL;
	137
	138	g_assert(drc);
	139
	140	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	141	drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
	142	if (local_err) {
	143	error_propagate(errp, local_err);
	144	return;
	145	}
	146
	147	spapr_hotplug_req_remove_by_index(drc);
	148	}
	149
af81cf32 BR	150	void spapr_core_plug(HotplugHandler hotplug_dev, DeviceState dev,
	151	Error **errp)
	152	{
	153	sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev));
	154	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
	155	sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
	156	CPUCore *cc = CPU_CORE(dev);
	157	CPUState *cs = CPU(core->threads);
	158	sPAPRDRConnector *drc;
	159	sPAPRDRConnectorClass *drck;
	160	Error *local_err = NULL;
	161	void *fdt = NULL;
	162	int fdt_offset = 0;
	163	int index;
	164	int smt = kvmppc_smt_threads();
	165
	166	drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, cc->core_id);
	167	index = cc->core_id / smt;
	168	spapr->cores[index] = OBJECT(dev);
	169
	170	if (!smc->dr_cpu_enabled) {
	171	/*
	172	* This is a cold plugged CPU core but the machine doesn't support
	173	* DR. So skip the hotplug path ensuring that the core is brought
	174	* up online with out an associated DR connector.
	175	*/
	176	return;
	177	}
	178
	179	g_assert(drc);
	180
	181	/*
	182	* Setup CPU DT entries only for hotplugged CPUs. For boot time or
	183	* coldplugged CPUs DT entries are setup in spapr_finalize_fdt().
	184	*/
	185	if (dev->hotplugged) {
	186	fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
	187	}
	188
	189	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	190	drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
	191	if (local_err) {
	192	g_free(fdt);
	193	spapr->cores[index] = NULL;
	194	error_propagate(errp, local_err);
	195	return;
	196	}
	197
	198	if (dev->hotplugged) {
	199	/*
	200	* Send hotplug notification interrupt to the guest only in case
	201	* of hotplugged CPUs.
	202	*/
	203	spapr_hotplug_req_add_by_index(drc);
	204	} else {
	205	/*
	206	* Set the right DRC states for cold plugged CPU.
	207	*/
	208	drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
	209	drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
	210	}
	211	}
	212
94a94e4c BR	213	void spapr_core_pre_plug(HotplugHandler hotplug_dev, DeviceState dev,
	214	Error **errp)
	215	{
	216	MachineState *machine = MACHINE(OBJECT(hotplug_dev));
af81cf32	217	sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev));
94a94e4c BR	218	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
	219	int spapr_max_cores = max_cpus / smp_threads;
	220	int index;
	221	int smt = kvmppc_smt_threads();
	222	Error *local_err = NULL;
	223	CPUCore *cc = CPU_CORE(dev);
	224	char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
	225	const char *type = object_get_typename(OBJECT(dev));
	226
	227	if (strcmp(base_core_type, type)) {
	228	error_setg(&local_err, "CPU core type should be %s", base_core_type);
	229	goto out;
	230	}
	231
af81cf32 BR	232	if (!smc->dr_cpu_enabled && dev->hotplugged) {
	233	error_setg(&local_err, "CPU hotplug not supported for this machine");
	234	goto out;
	235	}
	236
94a94e4c BR	237	if (cc->nr_threads != smp_threads) {
	238	error_setg(&local_err, "threads must be %d", smp_threads);
	239	goto out;
	240	}
	241
	242	if (cc->core_id % smt) {
	243	error_setg(&local_err, "invalid core id %d\n", cc->core_id);
	244	goto out;
	245	}
	246
	247	index = cc->core_id / smt;
	248	if (index < 0 \|\| index >= spapr_max_cores) {
	249	error_setg(&local_err, "core id %d out of range", cc->core_id);
	250	goto out;
	251	}
	252
	253	if (spapr->cores[index]) {
	254	error_setg(&local_err, "core %d already populated", cc->core_id);
	255	goto out;
	256	}
	257
	258	out:
	259	g_free(base_core_type);
	260	error_propagate(errp, local_err);
	261	}
	262
3b542549 BR	263	static int spapr_cpu_core_realize_child(Object child, void opaque)
3b542549 BR	264	{
f11235b9	265	Error *errp = opaque, local_err = NULL;
3b542549 BR	266	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	267	CPUState *cs = CPU(child);
	268	PowerPCCPU *cpu = POWERPC_CPU(cs);
	269
f11235b9 GK	270	object_property_set_bool(child, true, "realized", &local_err);
	271	if (local_err) {
	272	error_propagate(errp, local_err);
3b542549 BR	273	return 1;
	274	}
	275
f11235b9 GK	276	spapr_cpu_init(spapr, cpu, &local_err);
	277	if (local_err) {
	278	error_propagate(errp, local_err);
3b542549 BR	279	return 1;
	280	}
	281	return 0;
	282	}
	283
	284	static void spapr_cpu_core_realize(DeviceState dev, Error *errp)
	285	{
	286	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
	287	CPUCore *cc = CPU_CORE(OBJECT(dev));
	288	const char *typename = object_class_get_name(sc->cpu_class);
	289	size_t size = object_type_get_instance_size(typename);
	290	Error *local_err = NULL;
	291	Object *obj;
	292	int i;
	293
	294	sc->threads = g_malloc0(size * cc->nr_threads);
	295	for (i = 0; i < cc->nr_threads; i++) {
	296	char id[32];
	297	void obj = sc->threads + i size;
	298
	299	object_initialize(obj, size, typename);
	300	snprintf(id, sizeof(id), "thread[%d]", i);
	301	object_property_add_child(OBJECT(sc), id, obj, &local_err);
	302	if (local_err) {
	303	goto err;
	304	}
8e758dee	305	object_unref(obj);
3b542549 BR	306	}
	307	object_child_foreach(OBJECT(dev), spapr_cpu_core_realize_child, &local_err);
	308	if (local_err) {
	309	goto err;
	310	} else {
	311	return;
	312	}
	313
	314	err:
dde35bc9	315	while (--i >= 0) {
3b542549 BR	316	obj = sc->threads + i * size;
3b542549 BR	317	object_unparent(obj);
3b542549 BR	318	}
	319	g_free(sc->threads);
	320	error_propagate(errp, local_err);
	321	}
	322
	323	static void spapr_cpu_core_class_init(ObjectClass oc, void data)
	324	{
	325	DeviceClass *dc = DEVICE_CLASS(oc);
	326	dc->realize = spapr_cpu_core_realize;
	327	}
	328
	329	/*
	330	* instance_init routines from different flavours of sPAPR CPU cores.
3b542549 BR	331	*/
	332	#define SPAPR_CPU_CORE_INITFN(_type, _fname) \
	333	static void glue(glue(spapr_cpu_core_, _fname), _initfn(Object *obj)) \
	334	{ \
	335	sPAPRCPUCore *core = SPAPR_CPU_CORE(obj); \
	336	char *name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, stringify(_type)); \
	337	ObjectClass *oc = object_class_by_name(name); \
	338	g_assert(oc); \
	339	g_free((void *)name); \
	340	core->cpu_class = oc; \
	341	}
	342
470f2157 BR	343	SPAPR_CPU_CORE_INITFN(970mp_v1.0, 970MP_v10);
470f2157 BR	344	SPAPR_CPU_CORE_INITFN(970mp_v1.1, 970MP_v11);
ff461b8d BR	345	SPAPR_CPU_CORE_INITFN(970_v2.2, 970);
ff461b8d BR	346	SPAPR_CPU_CORE_INITFN(POWER5+_v2.1, POWER5plus);
3b542549 BR	347	SPAPR_CPU_CORE_INITFN(POWER7_v2.3, POWER7);
	348	SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus);
	349	SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8);
	350	SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E);
470f2157	351	SPAPR_CPU_CORE_INITFN(POWER8NVL_v1.0, POWER8NVL);
3b542549 BR	352
	353	typedef struct SPAPRCoreInfo {
	354	const char *name;
	355	void (initfn)(Object obj);
	356	} SPAPRCoreInfo;
	357
	358	static const SPAPRCoreInfo spapr_cores[] = {
470f2157 BR	359	/* 970 and aliaes */
470f2157 BR	360	{ .name = "970_v2.2", .initfn = spapr_cpu_core_970_initfn },
ff461b8d BR	361	{ .name = "970", .initfn = spapr_cpu_core_970_initfn },
ff461b8d BR	362
470f2157 BR	363	/* 970MP variants and aliases */
	364	{ .name = "970MP_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
	365	{ .name = "970mp_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
	366	{ .name = "970MP_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
	367	{ .name = "970mp_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
	368	{ .name = "970mp", .initfn = spapr_cpu_core_970MP_v11_initfn },
	369
	370	/* POWER5 and aliases */
	371	{ .name = "POWER5+_v2.1", .initfn = spapr_cpu_core_POWER5plus_initfn },
ff461b8d BR	372	{ .name = "POWER5+", .initfn = spapr_cpu_core_POWER5plus_initfn },
ff461b8d BR	373
3b542549 BR	374	/* POWER7 and aliases */
	375	{ .name = "POWER7_v2.3", .initfn = spapr_cpu_core_POWER7_initfn },
	376	{ .name = "POWER7", .initfn = spapr_cpu_core_POWER7_initfn },
	377
	378	/* POWER7+ and aliases */
	379	{ .name = "POWER7+_v2.1", .initfn = spapr_cpu_core_POWER7plus_initfn },
	380	{ .name = "POWER7+", .initfn = spapr_cpu_core_POWER7plus_initfn },
	381
	382	/* POWER8 and aliases */
	383	{ .name = "POWER8_v2.0", .initfn = spapr_cpu_core_POWER8_initfn },
	384	{ .name = "POWER8", .initfn = spapr_cpu_core_POWER8_initfn },
	385	{ .name = "power8", .initfn = spapr_cpu_core_POWER8_initfn },
	386
	387	/* POWER8E and aliases */
	388	{ .name = "POWER8E_v2.1", .initfn = spapr_cpu_core_POWER8E_initfn },
	389	{ .name = "POWER8E", .initfn = spapr_cpu_core_POWER8E_initfn },
	390
470f2157 BR	391	/* POWER8NVL and aliases */
	392	{ .name = "POWER8NVL_v1.0", .initfn = spapr_cpu_core_POWER8NVL_initfn },
	393	{ .name = "POWER8NVL", .initfn = spapr_cpu_core_POWER8NVL_initfn },
	394
3b542549 BR	395	{ .name = NULL }
	396	};
	397
	398	static void spapr_cpu_core_register(const SPAPRCoreInfo *info)
	399	{
	400	TypeInfo type_info = {
	401	.parent = TYPE_SPAPR_CPU_CORE,
	402	.instance_size = sizeof(sPAPRCPUCore),
	403	.instance_init = info->initfn,
	404	};
	405
	406	type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, info->name);
	407	type_register(&type_info);
	408	g_free((void *)type_info.name);
	409	}
	410
	411	static const TypeInfo spapr_cpu_core_type_info = {
	412	.name = TYPE_SPAPR_CPU_CORE,
	413	.parent = TYPE_CPU_CORE,
	414	.abstract = true,
	415	.instance_size = sizeof(sPAPRCPUCore),
	416	.class_init = spapr_cpu_core_class_init,
	417	};
	418
	419	static void spapr_cpu_core_register_types(void)
	420	{
	421	const SPAPRCoreInfo *info = spapr_cores;
	422
	423	type_register_static(&spapr_cpu_core_type_info);
	424	while (info->name) {
	425	spapr_cpu_core_register(info);
	426	info++;
	427	}
	428	}
	429
	430	type_init(spapr_cpu_core_register_types)