[qemu.git] / hw / acpi_ich9.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <[email protected]>
 *
 * This is based on acpi.c.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw.h"
#include "pc.h"
#include "pci/pci.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "acpi.h"
#include "sysemu/kvm.h"
#include "exec/address-spaces.h"

#include "ich9.h"

//#define DEBUG

#ifdef DEBUG
#define ICH9_DEBUG(fmt, ...) \
do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#else
#define ICH9_DEBUG(fmt, ...)    do { } while (0)
#endif

static void pm_update_sci(ICH9LPCPMRegs *pm)
{
    int sci_level, pm1a_sts;

    pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);

    sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    qemu_set_irq(pm->irq, sci_level);

    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&pm->acpi_regs,
                       (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
}

static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
    ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
    pm_update_sci(pm);
}

static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
}

static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
}

static const MemoryRegionOps ich9_gpe_ops = {
    .read = ich9_gpe_readb,
    .write = ich9_gpe_writeb,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 1,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    switch (addr) {
    case 0:
        return pm->smi_en;
    case 4:
        return pm->smi_sts;
    default:
        return 0;
    }
}

static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    switch (addr) {
    case 0:
        pm->smi_en = val;
        break;
    }
}

static const MemoryRegionOps ich9_smi_ops = {
    .read = ich9_smi_readl,
    .write = ich9_smi_writel,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
{
    ICH9_DEBUG("to 0x%x\n", pm_io_base);

    assert((pm_io_base & ICH9_PMIO_MASK) == 0);

    pm->pm_io_base = pm_io_base;
    memory_region_transaction_begin();
    memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
    memory_region_set_address(&pm->io, pm->pm_io_base);
    memory_region_transaction_commit();
}

static int ich9_pm_post_load(void *opaque, int version_id)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t pm_io_base = pm->pm_io_base;
    pm->pm_io_base = 0;
    ich9_pm_iospace_update(pm, pm_io_base);
    return 0;
}

#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 {                                                                   \
     .name       = (stringify(_field)),                              \
     .version_id = 0,                                                \
     .num        = ICH9_PMIO_GPE0_LEN,                               \
     .info       = &vmstate_info_uint8,                              \
     .size       = sizeof(uint8_t),                                  \
     .flags      = VMS_ARRAY | VMS_POINTER,                          \
     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 }

const VMStateDescription vmstate_ich9_pm = {
    .name = "ich9_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = ich9_pm_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
        VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
        VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    }
};

static void pm_reset(void *opaque)
{
    ICH9LPCPMRegs *pm = opaque;
    ich9_pm_iospace_update(pm, 0);

    acpi_pm1_evt_reset(&pm->acpi_regs);
    acpi_pm1_cnt_reset(&pm->acpi_regs);
    acpi_pm_tmr_reset(&pm->acpi_regs);
    acpi_gpe_reset(&pm->acpi_regs);

    if (kvm_enabled()) {
        /* Mark SMM as already inited to prevent SMM from running. KVM does not
         * support SMM mode. */
        pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
    }

    pm_update_sci(pm);
}

static void pm_powerdown_req(Notifier *n, void *opaque)
{
    ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);

    acpi_pm1_evt_power_down(&pm->acpi_regs);
}

void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
                  qemu_irq sci_irq, qemu_irq cmos_s3)
{
    memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
    memory_region_set_enabled(&pm->io, false);
    memory_region_add_subregion(pci_address_space_io(lpc_pci),
                                0, &pm->io);

    acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);

    acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
    memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
                          ICH9_PMIO_GPE0_LEN);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);

    memory_region_init_io(&pm->io_smi, &ich9_smi_ops, pm, "apci-smi",
                          8);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);

    pm->irq = sci_irq;
    qemu_register_reset(pm_reset, pm);
    pm->powerdown_notifier.notify = pm_powerdown_req;
    qemu_register_powerdown_notifier(&pm->powerdown_notifier);
}
Commit	Line	Data
e516572f JB	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
6f918e40 JB	5	* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
	6	* VA Linux Systems Japan K.K.
	7	* Copyright (C) 2012 Jason Baron <[email protected]>
	8	*
	9	* This is based on acpi.c.
e516572f JB	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License version 2 as published by the Free Software Foundation.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, see <http://www.gnu.org/licenses/>
e516572f	22	*
6f918e40 JB	23	* Contributions after 2012-01-13 are licensed under the terms of the
6f918e40 JB	24	* GNU GPL, version 2 or (at your option) any later version.
e516572f JB	25	*/
	26	#include "hw.h"
	27	#include "pc.h"
a2cb15b0	28	#include "pci/pci.h"
1de7afc9	29	#include "qemu/timer.h"
9c17d615	30	#include "sysemu/sysemu.h"
e516572f	31	#include "acpi.h"
9c17d615	32	#include "sysemu/kvm.h"
022c62cb	33	#include "exec/address-spaces.h"
e516572f JB	34
	35	#include "ich9.h"
	36
	37	//#define DEBUG
	38
	39	#ifdef DEBUG
	40	#define ICH9_DEBUG(fmt, ...) \
	41	do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
	42	#else
	43	#define ICH9_DEBUG(fmt, ...) do { } while (0)
	44	#endif
	45
e516572f JB	46	static void pm_update_sci(ICH9LPCPMRegs *pm)
	47	{
	48	int sci_level, pm1a_sts;
	49
	50	pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
	51
	52	sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
	53	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	54	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	55	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	56	ACPI_BITMASK_TIMER_ENABLE)) != 0);
	57	qemu_set_irq(pm->irq, sci_level);
	58
	59	/* schedule a timer interruption if needed */
	60	acpi_pm_tmr_update(&pm->acpi_regs,
	61	(pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
	62	!(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
	63	}
	64
	65	static void ich9_pm_update_sci_fn(ACPIREGS *regs)
	66	{
	67	ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
	68	pm_update_sci(pm);
	69	}
	70
76a7daf9 GH	71	static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
	72	{
	73	ICH9LPCPMRegs *pm = opaque;
	74	return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
	75	}
	76
	77	static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
	78	unsigned width)
	79	{
	80	ICH9LPCPMRegs *pm = opaque;
	81	acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
	82	}
	83
	84	static const MemoryRegionOps ich9_gpe_ops = {
	85	.read = ich9_gpe_readb,
	86	.write = ich9_gpe_writeb,
	87	.valid.min_access_size = 1,
	88	.valid.max_access_size = 4,
	89	.impl.min_access_size = 1,
	90	.impl.max_access_size = 1,
	91	.endianness = DEVICE_LITTLE_ENDIAN,
	92	};
	93
10cc69b0 GH	94	static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
	95	{
	96	ICH9LPCPMRegs *pm = opaque;
	97	switch (addr) {
	98	case 0:
	99	return pm->smi_en;
	100	case 4:
	101	return pm->smi_sts;
	102	default:
	103	return 0;
	104	}
	105	}
	106
	107	static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
	108	unsigned width)
	109	{
	110	ICH9LPCPMRegs *pm = opaque;
	111	switch (addr) {
	112	case 0:
	113	pm->smi_en = val;
	114	break;
	115	}
	116	}
	117
	118	static const MemoryRegionOps ich9_smi_ops = {
	119	.read = ich9_smi_readl,
	120	.write = ich9_smi_writel,
	121	.valid.min_access_size = 4,
	122	.valid.max_access_size = 4,
	123	.endianness = DEVICE_LITTLE_ENDIAN,
	124	};
	125
e516572f JB	126	void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
	127	{
	128	ICH9_DEBUG("to 0x%x\n", pm_io_base);
	129
	130	assert((pm_io_base & ICH9_PMIO_MASK) == 0);
	131
e516572f	132	pm->pm_io_base = pm_io_base;
cacaab8b GH	133	memory_region_transaction_begin();
	134	memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
	135	memory_region_set_address(&pm->io, pm->pm_io_base);
	136	memory_region_transaction_commit();
e516572f JB	137	}
	138
	139	static int ich9_pm_post_load(void *opaque, int version_id)
	140	{
	141	ICH9LPCPMRegs *pm = opaque;
	142	uint32_t pm_io_base = pm->pm_io_base;
	143	pm->pm_io_base = 0;
	144	ich9_pm_iospace_update(pm, pm_io_base);
	145	return 0;
	146	}
	147
	148	#define VMSTATE_GPE_ARRAY(_field, _state) \
	149	{ \
	150	.name = (stringify(_field)), \
	151	.version_id = 0, \
	152	.num = ICH9_PMIO_GPE0_LEN, \
	153	.info = &vmstate_info_uint8, \
	154	.size = sizeof(uint8_t), \
	155	.flags = VMS_ARRAY \| VMS_POINTER, \
	156	.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
	157	}
	158
	159	const VMStateDescription vmstate_ich9_pm = {
	160	.name = "ich9_pm",
	161	.version_id = 1,
	162	.minimum_version_id = 1,
	163	.minimum_version_id_old = 1,
	164	.post_load = ich9_pm_post_load,
	165	.fields = (VMStateField[]) {
	166	VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
	167	VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
	168	VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
	169	VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
	170	VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
	171	VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
	172	VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
	173	VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
	174	VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
	175	VMSTATE_END_OF_LIST()
	176	}
	177	};
	178
	179	static void pm_reset(void *opaque)
	180	{
	181	ICH9LPCPMRegs *pm = opaque;
	182	ich9_pm_iospace_update(pm, 0);
	183
	184	acpi_pm1_evt_reset(&pm->acpi_regs);
	185	acpi_pm1_cnt_reset(&pm->acpi_regs);
	186	acpi_pm_tmr_reset(&pm->acpi_regs);
	187	acpi_gpe_reset(&pm->acpi_regs);
	188
21bcfdd9 JK	189	if (kvm_enabled()) {
	190	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	191	* support SMM mode. */
	192	pm->smi_en \|= ICH9_PMIO_SMI_EN_APMC_EN;
	193	}
	194
e516572f JB	195	pm_update_sci(pm);
	196	}
	197
	198	static void pm_powerdown_req(Notifier n, void opaque)
	199	{
	200	ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
	201
	202	acpi_pm1_evt_power_down(&pm->acpi_regs);
	203	}
	204
503b19fc GH	205	void ich9_pm_init(PCIDevice lpc_pci, ICH9LPCPMRegs pm,
503b19fc GH	206	qemu_irq sci_irq, qemu_irq cmos_s3)
e516572f	207	{
4a522de0	208	memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
cacaab8b	209	memory_region_set_enabled(&pm->io, false);
503b19fc GH	210	memory_region_add_subregion(pci_address_space_io(lpc_pci),
503b19fc GH	211	0, &pm->io);
cacaab8b	212
77d58b1e	213	acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
b5a7c024	214	acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
afafe4bb	215	acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);
76a7daf9	216
e516572f	217	acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
76a7daf9 GH	218	memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
	219	ICH9_PMIO_GPE0_LEN);
	220	memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
e516572f	221
10cc69b0 GH	222	memory_region_init_io(&pm->io_smi, &ich9_smi_ops, pm, "apci-smi",
	223	8);
	224	memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
	225
e516572f JB	226	pm->irq = sci_irq;
	227	qemu_register_reset(pm_reset, pm);
	228	pm->powerdown_notifier.notify = pm_powerdown_req;
	229	qemu_register_powerdown_notifier(&pm->powerdown_notifier);
	230	}