[qemu.git] / hw / acpi_ich9.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 */
/*
 *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
 *                     VA Linux Systems Japan K.K.
 *  Copyright (C) 2012 Jason Baron <[email protected]>
 *
 *  This is based on acpi.c.
 */
#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "acpi.h"
#include "kvm.h"

#include "ich9.h"

//#define DEBUG

#ifdef DEBUG
#define ICH9_DEBUG(fmt, ...) \
do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#else
#define ICH9_DEBUG(fmt, ...)    do { } while (0)
#endif

static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
                                     uint32_t val);
static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);

static void pm_update_sci(ICH9LPCPMRegs *pm)
{
    int sci_level, pm1a_sts;

    pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);

    sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    qemu_set_irq(pm->irq, sci_level);

    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&pm->acpi_regs,
                       (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
}

static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
    ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
    pm_update_sci(pm);
}

static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    ICH9LPCPMRegs *pm = opaque;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
        acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
        break;
    default:
        break;
    }

    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
}

static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t val = 0;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
        val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
        break;
    default:
        val = 0;
        break;
    }
    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
    return val;
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    ICH9LPCPMRegs *pm = opaque;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_PM1_STS:
        acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
        pm_update_sci(pm);
        break;
    case ICH9_PMIO_PM1_EN:
        pm->acpi_regs.pm1.evt.en = val;
        pm_update_sci(pm);
        break;
    case ICH9_PMIO_PM1_CNT:
        acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
        break;
    default:
        pm_ioport_write_fallback(opaque, addr, 2, val);
        break;
    }
    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t val;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_PM1_STS:
        val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
        break;
    case ICH9_PMIO_PM1_EN:
        val = pm->acpi_regs.pm1.evt.en;
        break;
    case ICH9_PMIO_PM1_CNT:
        val = pm->acpi_regs.pm1.cnt.cnt;
        break;
    default:
        val = pm_ioport_read_fallback(opaque, addr, 2);
        break;
    }
    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    ICH9LPCPMRegs *pm = opaque;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_SMI_EN:
        pm->smi_en = val;
        break;
    default:
        pm_ioport_write_fallback(opaque, addr, 4, val);
        break;
    }
    ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t val;

    switch (addr & ICH9_PMIO_MASK) {
    case ICH9_PMIO_PM1_TMR:
        val = acpi_pm_tmr_get(&pm->acpi_regs);
        break;
    case ICH9_PMIO_SMI_EN:
        val = pm->smi_en;
        break;

    default:
        val = pm_ioport_read_fallback(opaque, addr, 4);
        break;
    }
    ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
    return val;
}

static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
                                     uint32_t val)
 {
    int subsize = (len == 4) ? 2 : 1;
    IOPortWriteFunc *ioport_write =
        (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;

    int i;

    for (i = 0; i < len; i += subsize) {
        ioport_write(opaque, addr, val);
        val >>= 8 * subsize;
    }
}

static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
{
    int subsize = (len == 4) ? 2 : 1;
    IOPortReadFunc *ioport_read =
        (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;

    uint32_t val;
    int i;

    val = 0;
    for (i = 0; i < len; i += subsize) {
        val <<= 8 * subsize;
        val |= ioport_read(opaque, addr);
    }

    return val;
}

void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
{
    ICH9_DEBUG("to 0x%x\n", pm_io_base);

    assert((pm_io_base & ICH9_PMIO_MASK) == 0);

    if (pm->pm_io_base != 0) {
        isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
    }

    /* don't map at 0 */
    if (pm_io_base == 0) {
        return;
    }

    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);

    pm->pm_io_base = pm_io_base;
    acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
}

static int ich9_pm_post_load(void *opaque, int version_id)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t pm_io_base = pm->pm_io_base;
    pm->pm_io_base = 0;
    ich9_pm_iospace_update(pm, pm_io_base);
    return 0;
}

#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 {                                                                   \
     .name       = (stringify(_field)),                              \
     .version_id = 0,                                                \
     .num        = ICH9_PMIO_GPE0_LEN,                               \
     .info       = &vmstate_info_uint8,                              \
     .size       = sizeof(uint8_t),                                  \
     .flags      = VMS_ARRAY | VMS_POINTER,                          \
     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 }

const VMStateDescription vmstate_ich9_pm = {
    .name = "ich9_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = ich9_pm_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
        VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
        VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    }
};

static void pm_reset(void *opaque)
{
    ICH9LPCPMRegs *pm = opaque;
    ich9_pm_iospace_update(pm, 0);

    acpi_pm1_evt_reset(&pm->acpi_regs);
    acpi_pm1_cnt_reset(&pm->acpi_regs);
    acpi_pm_tmr_reset(&pm->acpi_regs);
    acpi_gpe_reset(&pm->acpi_regs);

    if (kvm_enabled()) {
        /* Mark SMM as already inited to prevent SMM from running. KVM does not
         * support SMM mode. */
        pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
    }

    pm_update_sci(pm);
}

static void pm_powerdown_req(Notifier *n, void *opaque)
{
    ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);

    acpi_pm1_evt_power_down(&pm->acpi_regs);
}

void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
    acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
    acpi_pm1_cnt_init(&pm->acpi_regs);
    acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);

    pm->irq = sci_irq;
    qemu_register_reset(pm_reset, pm);
    pm->powerdown_notifier.notify = pm_powerdown_req;
    qemu_register_powerdown_notifier(&pm->powerdown_notifier);
}
Commit	Line	Data
e516572f JB	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, see <http://www.gnu.org/licenses/>
	17	*/
	18	/*
	19	* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
	20	* VA Linux Systems Japan K.K.
	21	* Copyright (C) 2012 Jason Baron <[email protected]>
	22	*
	23	* This is based on acpi.c.
	24	*/
	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
	28	#include "qemu-timer.h"
	29	#include "sysemu.h"
	30	#include "acpi.h"
21bcfdd9	31	#include "kvm.h"
e516572f JB	32
	33	#include "ich9.h"
	34
	35	//#define DEBUG
	36
	37	#ifdef DEBUG
	38	#define ICH9_DEBUG(fmt, ...) \
	39	do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
	40	#else
	41	#define ICH9_DEBUG(fmt, ...) do { } while (0)
	42	#endif
	43
	44	static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
	45	uint32_t val);
	46	static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
	47
	48	static void pm_update_sci(ICH9LPCPMRegs *pm)
	49	{
	50	int sci_level, pm1a_sts;
	51
	52	pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
	53
	54	sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
	55	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	56	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	57	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	58	ACPI_BITMASK_TIMER_ENABLE)) != 0);
	59	qemu_set_irq(pm->irq, sci_level);
	60
	61	/* schedule a timer interruption if needed */
	62	acpi_pm_tmr_update(&pm->acpi_regs,
	63	(pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
	64	!(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
	65	}
	66
	67	static void ich9_pm_update_sci_fn(ACPIREGS *regs)
	68	{
	69	ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
	70	pm_update_sci(pm);
	71	}
	72
	73	static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	74	{
	75	ICH9LPCPMRegs *pm = opaque;
	76
	77	switch (addr & ICH9_PMIO_MASK) {
	78	case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
	79	acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
	80	break;
	81	default:
	82	break;
	83	}
	84
	85	ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
	86	}
	87
	88	static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
	89	{
	90	ICH9LPCPMRegs *pm = opaque;
	91	uint32_t val = 0;
	92
	93	switch (addr & ICH9_PMIO_MASK) {
	94	case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
	95	val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
96	break;
97	default:
98	val = 0;
99	break;
100	}
101	ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
102	return val;
103	}
104
105	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
106	{
107	ICH9LPCPMRegs *pm = opaque;
108
109	switch (addr & ICH9_PMIO_MASK) {
110	case ICH9_PMIO_PM1_STS:
111	acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
112	pm_update_sci(pm);
113	break;
114	case ICH9_PMIO_PM1_EN:
115	pm->acpi_regs.pm1.evt.en = val;
116	pm_update_sci(pm);
117	break;
118	case ICH9_PMIO_PM1_CNT:
119	acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
120	break;
121	default:
122	pm_ioport_write_fallback(opaque, addr, 2, val);
123	break;
124	}
125	ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
126	}
127
128	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
129	{
130	ICH9LPCPMRegs *pm = opaque;
131	uint32_t val;
132
133	switch (addr & ICH9_PMIO_MASK) {
134	case ICH9_PMIO_PM1_STS:
135	val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
136	break;
137	case ICH9_PMIO_PM1_EN:
138	val = pm->acpi_regs.pm1.evt.en;
139	break;
140	case ICH9_PMIO_PM1_CNT:
141	val = pm->acpi_regs.pm1.cnt.cnt;
142	break;
143	default:
144	val = pm_ioport_read_fallback(opaque, addr, 2);
145	break;
146	}
147	ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
148	return val;
149	}
150
151	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
152	{
153	ICH9LPCPMRegs *pm = opaque;
154
155	switch (addr & ICH9_PMIO_MASK) {
156	case ICH9_PMIO_SMI_EN:
157	pm->smi_en = val;
158	break;
159	default:
160	pm_ioport_write_fallback(opaque, addr, 4, val);
161	break;
162	}
163	ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
164	}
165
166	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
167	{
168	ICH9LPCPMRegs *pm = opaque;
169	uint32_t val;
170
171	switch (addr & ICH9_PMIO_MASK) {
172	case ICH9_PMIO_PM1_TMR:
173	val = acpi_pm_tmr_get(&pm->acpi_regs);
174	break;
175	case ICH9_PMIO_SMI_EN:
176	val = pm->smi_en;
177	break;
178
179	default:
180	val = pm_ioport_read_fallback(opaque, addr, 4);
181	break;
182	}
183	ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
184	return val;
185	}
186
187	static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
188	uint32_t val)
189	{
190	int subsize = (len == 4) ? 2 : 1;
191	IOPortWriteFunc *ioport_write =
192	(subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
193
194	int i;
195
196	for (i = 0; i < len; i += subsize) {
197	ioport_write(opaque, addr, val);
198	val >>= 8 * subsize;
199	}
200	}
201
202	static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
203	{
204	int subsize = (len == 4) ? 2 : 1;
205	IOPortReadFunc *ioport_read =
206	(subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
207
208	uint32_t val;
209	int i;
210
211	val = 0;
212	for (i = 0; i < len; i += subsize) {
213	val <<= 8 * subsize;
214	val \|= ioport_read(opaque, addr);
215	}
216
217	return val;
218	}
219
220	void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
221	{
222	ICH9_DEBUG("to 0x%x\n", pm_io_base);
223
224	assert((pm_io_base & ICH9_PMIO_MASK) == 0);
225
226	if (pm->pm_io_base != 0) {
227	isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
228	}
229
230	/* don't map at 0 */
231	if (pm_io_base == 0) {
232	return;
233	}
234
235	register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
236	register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
237	register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
238	register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
239	register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
240	register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
241
242	pm->pm_io_base = pm_io_base;
243	acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
244	}
245
246	static int ich9_pm_post_load(void *opaque, int version_id)
247	{
248	ICH9LPCPMRegs *pm = opaque;
249	uint32_t pm_io_base = pm->pm_io_base;
250	pm->pm_io_base = 0;
251	ich9_pm_iospace_update(pm, pm_io_base);
252	return 0;
253	}
254
255	#define VMSTATE_GPE_ARRAY(_field, _state) \
256	{ \
257	.name = (stringify(_field)), \
258	.version_id = 0, \
259	.num = ICH9_PMIO_GPE0_LEN, \
260	.info = &vmstate_info_uint8, \
261	.size = sizeof(uint8_t), \
262	.flags = VMS_ARRAY \| VMS_POINTER, \
263	.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
264	}
265
266	const VMStateDescription vmstate_ich9_pm = {
267	.name = "ich9_pm",
268	.version_id = 1,
269	.minimum_version_id = 1,
270	.minimum_version_id_old = 1,
271	.post_load = ich9_pm_post_load,
272	.fields = (VMStateField[]) {
273	VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
274	VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
275	VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
276	VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
277	VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
278	VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
279	VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
280	VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
281	VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
282	VMSTATE_END_OF_LIST()
283	}
284	};
285
286	static void pm_reset(void *opaque)
287	{
288	ICH9LPCPMRegs *pm = opaque;
289	ich9_pm_iospace_update(pm, 0);
290
291	acpi_pm1_evt_reset(&pm->acpi_regs);
292	acpi_pm1_cnt_reset(&pm->acpi_regs);
293	acpi_pm_tmr_reset(&pm->acpi_regs);
294	acpi_gpe_reset(&pm->acpi_regs);
295
21bcfdd9 JK	296	if (kvm_enabled()) {
	297	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	298	* support SMM mode. */
	299	pm->smi_en \|= ICH9_PMIO_SMI_EN_APMC_EN;
	300	}
	301
e516572f JB	302	pm_update_sci(pm);
	303	}
	304
	305	static void pm_powerdown_req(Notifier n, void opaque)
	306	{
	307	ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
	308
	309	acpi_pm1_evt_power_down(&pm->acpi_regs);
	310	}
	311
	312	void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
	313	{
	314	acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
	315	acpi_pm1_cnt_init(&pm->acpi_regs);
	316	acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
	317
	318	pm->irq = sci_irq;
	319	qemu_register_reset(pm_reset, pm);
	320	pm->powerdown_notifier.notify = pm_powerdown_req;
	321	qemu_register_powerdown_notifier(&pm->powerdown_notifier);
	322	}