[qemu.git] / hw / ppc / virtex_ml507.c

/*
 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
 *
 * Copyright (c) 2010 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "sysemu/reset.h"
#include "hw/boards.h"
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/option.h"

#include "hw/intc/ppc-uic.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "ppc405.h"

#define EPAPR_MAGIC    (0x45504150)
#define FLASH_SIZE     (16 * MiB)

#define INTC_BASEADDR       0x81800000
#define UART16550_BASEADDR  0x83e01003
#define TIMER_BASEADDR      0x83c00000
#define PFLASH_BASEADDR     0xfc000000

#define TIMER_IRQ           3
#define UART16550_IRQ       9

static struct boot_info
{
    uint32_t bootstrap_pc;
    uint32_t cmdline;
    uint32_t fdt;
    uint32_t ima_size;
    void *vfdt;
} boot_info;

/* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
                                     target_ulong va,
                                     hwaddr pa)
{
    ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];

    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0x80000000  */
    tlb->EPN = va & TARGET_PAGE_MASK;
    tlb->RPN = pa & TARGET_PAGE_MASK;
    tlb->PID = 0;

    tlb = &env->tlb.tlbe[1];
    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1U << 31; /* up to 0xffffffff  */
    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->PID = 0;
}

static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
{
    PowerPCCPU *cpu;
    CPUPPCState *env;
    DeviceState *uicdev;
    SysBusDevice *uicsbd;

    cpu = POWERPC_CPU(cpu_create(cpu_type));
    env = &cpu->env;

    ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);

    ppc_dcr_init(env, NULL, NULL);

    /* interrupt controller */
    uicdev = qdev_new(TYPE_PPC_UIC);
    uicsbd = SYS_BUS_DEVICE(uicdev);

    object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
                             &error_fatal);
    sysbus_realize_and_unref(uicsbd, &error_fatal);

    sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
                       ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
    sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
                       ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);

    /* This board doesn't wire anything up to the inputs of the UIC. */
    return cpu;
}

static void main_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(CPU(cpu));
    /* Linux Kernel Parameters (passing device tree):
       *   r3: pointer to the fdt
       *   r4: 0
       *   r5: 0
       *   r6: epapr magic
       *   r7: size of IMA in bytes
       *   r8: 0
       *   r9: 0
    */
    env->gpr[1] = (16 * MiB) - 8;
    /* Provide a device-tree.  */
    env->gpr[3] = bi->fdt;
    env->nip = bi->bootstrap_pc;

    /* Create a mapping for the kernel.  */
    mmubooke_create_initial_mapping(env, 0, 0);
    env->gpr[6] = tswap32(EPAPR_MAGIC);
    env->gpr[7] = bi->ima_size;
}

#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
static int xilinx_load_device_tree(hwaddr addr,
                                      uint32_t ramsize,
                                      hwaddr initrd_base,
                                      hwaddr initrd_size,
                                      const char *kernel_cmdline)
{
    char *path;
    int fdt_size;
    void *fdt = NULL;
    int r;
    const char *dtb_filename;

    dtb_filename = current_machine->dtb;
    if (dtb_filename) {
        fdt = load_device_tree(dtb_filename, &fdt_size);
        if (!fdt) {
            error_report("Error while loading device tree file '%s'",
                dtb_filename);
        }
    } else {
        /* Try the local "ppc.dtb" override.  */
        fdt = load_device_tree("ppc.dtb", &fdt_size);
        if (!fdt) {
            path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
            if (path) {
                fdt = load_device_tree(path, &fdt_size);
                g_free(path);
            }
        }
    }
    if (!fdt) {
        return 0;
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
                              initrd_base);
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-start");
    }

    r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                              (initrd_base + initrd_size));
    if (r < 0) {
        error_report("couldn't set /chosen/linux,initrd-end");
    }

    r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
    if (r < 0)
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    cpu_physical_memory_write(addr, fdt, fdt_size);
    g_free(fdt);
    return fdt_size;
}

static void virtex_init(MachineState *machine)
{
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    hwaddr initrd_base = 0;
    int initrd_size = 0;
    MemoryRegion *address_space_mem = get_system_memory();
    DeviceState *dev;
    PowerPCCPU *cpu;
    CPUPPCState *env;
    hwaddr ram_base = 0;
    DriveInfo *dinfo;
    qemu_irq irq[32], *cpu_irq;
    int kernel_size;
    int i;

    /* init CPUs */
    cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
    env = &cpu->env;

    if (env->mmu_model != POWERPC_MMU_BOOKE) {
        error_report("MMU model %i not supported by this machine",
                     env->mmu_model);
        exit(1);
    }

    qemu_register_reset(main_cpu_reset, cpu);

    memory_region_add_subregion(address_space_mem, ram_base, machine->ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
    dev = qdev_new("xlnx.xps-intc");
    qdev_prop_set_uint32(dev, "kind-of-intr", 0);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
                   115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);

    /* 2 timers at irq 2 @ 62 Mhz.  */
    dev = qdev_new("xlnx.xps-timer");
    qdev_prop_set_uint32(dev, "one-timer-only", 0);
    qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);

    if (kernel_filename) {
        uint64_t entry, high;
        hwaddr boot_offset;

        /* Boots a kernel elf binary.  */
        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                               &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
                               0, 0);
        boot_info.bootstrap_pc = entry & 0x00ffffff;

        if (kernel_size < 0) {
            boot_offset = 0x1200000;
            /* If we failed loading ELF's try a raw image.  */
            kernel_size = load_image_targphys(kernel_filename,
                                              boot_offset,
                                              machine->ram_size);
            boot_info.bootstrap_pc = boot_offset;
            high = boot_info.bootstrap_pc + kernel_size + 8192;
        }

        boot_info.ima_size = kernel_size;

        /* Load initrd. */
        if (machine->initrd_filename) {
            initrd_base = high = ROUND_UP(high, 4);
            initrd_size = load_image_targphys(machine->initrd_filename,
                                              high, machine->ram_size - high);

            if (initrd_size < 0) {
                error_report("couldn't load ram disk '%s'",
                             machine->initrd_filename);
                exit(1);
            }
            high = ROUND_UP(high + initrd_size, 4);
        }

        /* Provide a device-tree.  */
        boot_info.fdt = high + (8192 * 2);
        boot_info.fdt &= ~8191;

        xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
                                initrd_base, initrd_size,
                                kernel_cmdline);
    }
    env->load_info = &boot_info;
}

static void virtex_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Virtex ML507 reference design";
    mc->init = virtex_init;
    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
    mc->default_ram_id = "ram";
}

DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
Commit	Line	Data
2c50e26e EI	1	/*
	2	* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
	3	*
	4	* Copyright (c) 2010 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
0d75590d	25	#include "qemu/osdep.h"
a8d25326	26	#include "qemu-common.h"
2c65db5e	27	#include "qemu/datadir.h"
ab3dd749	28	#include "qemu/units.h"
33c11879	29	#include "cpu.h"
83c9f4ca	30	#include "hw/sysbus.h"
0d09e41a PB	31	#include "hw/char/serial.h"
0d09e41a PB	32	#include "hw/block/flash.h"
9c17d615	33	#include "sysemu/sysemu.h"
71e8a915	34	#include "sysemu/reset.h"
83c9f4ca	35	#include "hw/boards.h"
9c17d615	36	#include "sysemu/device_tree.h"
83c9f4ca	37	#include "hw/loader.h"
2c50e26e	38	#include "elf.h"
3e80f690	39	#include "qapi/error.h"
d49b6836	40	#include "qemu/error-report.h"
922a01a0	41	#include "qemu/option.h"
2c50e26e	42
c5ac9dc6	43	#include "hw/intc/ppc-uic.h"
0d09e41a PB	44	#include "hw/ppc/ppc.h"
0d09e41a PB	45	#include "hw/ppc/ppc4xx.h"
a27bd6c7	46	#include "hw/qdev-properties.h"
47b43a1f	47	#include "ppc405.h"
2c50e26e	48
2c50e26e	49	#define EPAPR_MAGIC (0x45504150)
ab3dd749	50	#define FLASH_SIZE (16 * MiB)
2c50e26e	51
81cce07e PC	52	#define INTC_BASEADDR 0x81800000
	53	#define UART16550_BASEADDR 0x83e01003
	54	#define TIMER_BASEADDR 0x83c00000
	55	#define PFLASH_BASEADDR 0xfc000000
	56
	57	#define TIMER_IRQ 3
	58	#define UART16550_IRQ 9
	59
2c50e26e EI	60	static struct boot_info
	61	{
	62	uint32_t bootstrap_pc;
	63	uint32_t cmdline;
	64	uint32_t fdt;
	65	uint32_t ima_size;
	66	void *vfdt;
	67	} boot_info;
	68
	69	/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
e2684c0b	70	static void mmubooke_create_initial_mapping(CPUPPCState *env,
2c50e26e	71	target_ulong va,
a8170e5e	72	hwaddr pa)
2c50e26e	73	{
1c53accc	74	ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
2c50e26e EI	75
	76	tlb->attr = 0;
	77	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	78	tlb->size = 1U << 31; /* up to 0x80000000 */
2c50e26e EI	79	tlb->EPN = va & TARGET_PAGE_MASK;
	80	tlb->RPN = pa & TARGET_PAGE_MASK;
	81	tlb->PID = 0;
	82
1c53accc	83	tlb = &env->tlb.tlbe[1];
2c50e26e EI	84	tlb->attr = 0;
2c50e26e EI	85	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
a1f7f97b	86	tlb->size = 1U << 31; /* up to 0xffffffff */
2c50e26e EI	87	tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
	88	tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
	89	tlb->PID = 0;
	90	}
	91
79a87336	92	static PowerPCCPU ppc440_init_xilinx(const char cpu_type, uint32_t sysclk)
2c50e26e	93	{
d1d4938b	94	PowerPCCPU *cpu;
e2684c0b	95	CPUPPCState *env;
c5ac9dc6 PM	96	DeviceState *uicdev;
c5ac9dc6 PM	97	SysBusDevice *uicsbd;
2c50e26e	98
6bab8eaa	99	cpu = POWERPC_CPU(cpu_create(cpu_type));
d1d4938b	100	env = &cpu->env;
2c50e26e	101
a34a92b9	102	ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
2c50e26e EI	103
	104	ppc_dcr_init(env, NULL, NULL);
	105
	106	/* interrupt controller */
c5ac9dc6 PM	107	uicdev = qdev_new(TYPE_PPC_UIC);
	108	uicsbd = SYS_BUS_DEVICE(uicdev);
	109
	110	object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
	111	&error_fatal);
	112	sysbus_realize_and_unref(uicsbd, &error_fatal);
	113
	114	sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
	115	((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
	116	sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
	117	((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
	118
	119	/* This board doesn't wire anything up to the inputs of the UIC. */
68281699	120	return cpu;
2c50e26e EI	121	}
	122
	123	static void main_cpu_reset(void *opaque)
	124	{
f8031482 AF	125	PowerPCCPU *cpu = opaque;
f8031482 AF	126	CPUPPCState *env = &cpu->env;
2c50e26e EI	127	struct boot_info *bi = env->load_info;
2c50e26e EI	128
f8031482	129	cpu_reset(CPU(cpu));
2c50e26e EI	130	/* Linux Kernel Parameters (passing device tree):
	131	* r3: pointer to the fdt
	132	* r4: 0
	133	* r5: 0
	134	* r6: epapr magic
	135	* r7: size of IMA in bytes
	136	* r8: 0
	137	* r9: 0
	138	*/
ab3dd749	139	env->gpr[1] = (16 * MiB) - 8;
2c50e26e EI	140	/* Provide a device-tree. */
	141	env->gpr[3] = bi->fdt;
	142	env->nip = bi->bootstrap_pc;
	143
	144	/* Create a mapping for the kernel. */
	145	mmubooke_create_initial_mapping(env, 0, 0);
	146	env->gpr[6] = tswap32(EPAPR_MAGIC);
	147	env->gpr[7] = bi->ima_size;
	148	}
	149
	150	#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
a8170e5e	151	static int xilinx_load_device_tree(hwaddr addr,
2c50e26e	152	uint32_t ramsize,
a8170e5e AK	153	hwaddr initrd_base,
a8170e5e AK	154	hwaddr initrd_size,
2c50e26e EI	155	const char *kernel_cmdline)
	156	{
	157	char *path;
	158	int fdt_size;
daf285b6	159	void *fdt = NULL;
2c50e26e	160	int r;
daf285b6	161	const char *dtb_filename;
2c50e26e	162
f2ce39b4	163	dtb_filename = current_machine->dtb;
daf285b6 EV	164	if (dtb_filename) {
	165	fdt = load_device_tree(dtb_filename, &fdt_size);
	166	if (!fdt) {
	167	error_report("Error while loading device tree file '%s'",
	168	dtb_filename);
2c50e26e	169	}
daf285b6 EV	170	} else {
	171	/* Try the local "ppc.dtb" override. */
	172	fdt = load_device_tree("ppc.dtb", &fdt_size);
3b2e3dc9	173	if (!fdt) {
daf285b6 EV	174	path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
	175	if (path) {
	176	fdt = load_device_tree(path, &fdt_size);
	177	g_free(path);
	178	}
3b2e3dc9	179	}
2c50e26e	180	}
daf285b6 EV	181	if (!fdt) {
	182	return 0;
	183	}
0658aa9c EI	184
	185	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
	186	initrd_base);
	187	if (r < 0) {
	188	error_report("couldn't set /chosen/linux,initrd-start");
	189	}
	190
	191	r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	192	(initrd_base + initrd_size));
	193	if (r < 0) {
	194	error_report("couldn't set /chosen/linux,initrd-end");
	195	}
	196
5a4348d1	197	r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
2c50e26e EI	198	if (r < 0)
2c50e26e EI	199	fprintf(stderr, "couldn't set /chosen/bootargs\n");
e1fe50dc	200	cpu_physical_memory_write(addr, fdt, fdt_size);
438bafca	201	g_free(fdt);
2c50e26e EI	202	return fdt_size;
	203	}
	204
3ef96221	205	static void virtex_init(MachineState *machine)
2c50e26e	206	{
3ef96221 MA	207	const char *kernel_filename = machine->kernel_filename;
3ef96221 MA	208	const char *kernel_cmdline = machine->kernel_cmdline;
0658aa9c EI	209	hwaddr initrd_base = 0;
0658aa9c EI	210	int initrd_size = 0;
39186d8a	211	MemoryRegion *address_space_mem = get_system_memory();
2c50e26e	212	DeviceState *dev;
68281699	213	PowerPCCPU *cpu;
e2684c0b	214	CPUPPCState *env;
a8170e5e	215	hwaddr ram_base = 0;
2c50e26e	216	DriveInfo *dinfo;
2c50e26e	217	qemu_irq irq[32], *cpu_irq;
2c50e26e EI	218	int kernel_size;
	219	int i;
	220
	221	/* init CPUs */
79a87336	222	cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
68281699	223	env = &cpu->env;
00469dc3 VP	224
00469dc3 VP	225	if (env->mmu_model != POWERPC_MMU_BOOKE) {
6f76b817 AF	226	error_report("MMU model %i not supported by this machine",
6f76b817 AF	227	env->mmu_model);
00469dc3 VP	228	exit(1);
	229	}
	230
f8031482	231	qemu_register_reset(main_cpu_reset, cpu);
2c50e26e	232
9fe680ee	233	memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
2c50e26e	234
2c50e26e	235	dinfo = drive_get(IF_PFLASH, 0, 0);
940d5b13	236	pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
4be74634	237	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	238	64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
2c50e26e EI	239
2c50e26e EI	240	cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
3e80f690	241	dev = qdev_new("xlnx.xps-intc");
13c9bfbf	242	qdev_prop_set_uint32(dev, "kind-of-intr", 0);
3c6ef471	243	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
13c9bfbf PC	244	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
13c9bfbf PC	245	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
2c50e26e EI	246	for (i = 0; i < 32; i++) {
	247	irq[i] = qdev_get_gpio_in(dev, i);
	248	}
	249
81cce07e	250	serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
9bca0edb	251	115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
2c50e26e EI	252
2c50e26e EI	253	/* 2 timers at irq 2 @ 62 Mhz. */
3e80f690	254	dev = qdev_new("xlnx.xps-timer");
29873712 PC	255	qdev_prop_set_uint32(dev, "one-timer-only", 0);
29873712 PC	256	qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
3c6ef471	257	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29873712 PC	258	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
29873712 PC	259	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
2c50e26e EI	260
2c50e26e EI	261	if (kernel_filename) {
617160c9	262	uint64_t entry, high;
a8170e5e	263	hwaddr boot_offset;
2c50e26e EI	264
2c50e26e EI	265	/* Boots a kernel elf binary. */
4366e1db	266	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
617160c9	267	&entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
7ef295ea	268	0, 0);
2c50e26e EI	269	boot_info.bootstrap_pc = entry & 0x00ffffff;
	270
	271	if (kernel_size < 0) {
	272	boot_offset = 0x1200000;
	273	/* If we failed loading ELF's try a raw image. */
	274	kernel_size = load_image_targphys(kernel_filename,
	275	boot_offset,
9fe680ee	276	machine->ram_size);
2c50e26e EI	277	boot_info.bootstrap_pc = boot_offset;
	278	high = boot_info.bootstrap_pc + kernel_size + 8192;
	279	}
	280
	281	boot_info.ima_size = kernel_size;
	282
0658aa9c	283	/* Load initrd. */
3ef96221	284	if (machine->initrd_filename) {
0658aa9c	285	initrd_base = high = ROUND_UP(high, 4);
3ef96221	286	initrd_size = load_image_targphys(machine->initrd_filename,
9fe680ee	287	high, machine->ram_size - high);
0658aa9c EI	288
	289	if (initrd_size < 0) {
	290	error_report("couldn't load ram disk '%s'",
3ef96221	291	machine->initrd_filename);
0658aa9c EI	292	exit(1);
	293	}
	294	high = ROUND_UP(high + initrd_size, 4);
	295	}
	296
2c50e26e EI	297	/* Provide a device-tree. */
	298	boot_info.fdt = high + (8192 * 2);
	299	boot_info.fdt &= ~8191;
0658aa9c	300
9fe680ee	301	xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
0658aa9c EI	302	initrd_base, initrd_size,
0658aa9c EI	303	kernel_cmdline);
2c50e26e EI	304	}
	305	env->load_info = &boot_info;
	306	}
	307
e264d29d	308	static void virtex_machine_init(MachineClass *mc)
2c50e26e	309	{
e264d29d EH	310	mc->desc = "Xilinx Virtex ML507 reference design";
e264d29d EH	311	mc->init = virtex_init;
6bab8eaa	312	mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
9fe680ee	313	mc->default_ram_id = "ram";
2c50e26e EI	314	}
2c50e26e EI	315
e264d29d	316	DEFINE_MACHINE("virtex-ml507", virtex_machine_init)