[qemu.git] / hw / ppc / virtex_ml507.c

/*
 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
 *
 * Copyright (c) 2010 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/char/serial.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"

#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "ppc405.h"

#include "sysemu/blockdev.h"
#include "qapi/qmp/qerror.h"

#define EPAPR_MAGIC    (0x45504150)
#define FLASH_SIZE     (16 * 1024 * 1024)

#define INTC_BASEADDR       0x81800000
#define UART16550_BASEADDR  0x83e01003
#define TIMER_BASEADDR      0x83c00000
#define PFLASH_BASEADDR     0xfc000000

#define TIMER_IRQ           3
#define UART16550_IRQ       9

static struct boot_info
{
    uint32_t bootstrap_pc;
    uint32_t cmdline;
    uint32_t fdt;
    uint32_t ima_size;
    void *vfdt;
} boot_info;

/* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
                                     target_ulong va,
                                     hwaddr pa)
{
    ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];

    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1 << 31; /* up to 0x80000000  */
    tlb->EPN = va & TARGET_PAGE_MASK;
    tlb->RPN = pa & TARGET_PAGE_MASK;
    tlb->PID = 0;

    tlb = &env->tlb.tlbe[1];
    tlb->attr = 0;
    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
    tlb->size = 1 << 31; /* up to 0xffffffff  */
    tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
    tlb->PID = 0;
}

static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
                                      int do_init,
                                      const char *cpu_model,
                                      uint32_t sysclk)
{
    PowerPCCPU *cpu;
    CPUPPCState *env;
    qemu_irq *irqs;

    cpu = cpu_ppc_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "Unable to initialize CPU!\n");
        exit(1);
    }
    env = &cpu->env;

    ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);

    ppc_dcr_init(env, NULL, NULL);

    /* interrupt controller */
    irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
    irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
    irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
    ppcuic_init(env, irqs, 0x0C0, 0, 1);
    return cpu;
}

static void main_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(CPU(cpu));
    /* Linux Kernel Parameters (passing device tree):
       *   r3: pointer to the fdt
       *   r4: 0
       *   r5: 0
       *   r6: epapr magic
       *   r7: size of IMA in bytes
       *   r8: 0
       *   r9: 0
    */
    env->gpr[1] = (16<<20) - 8;
    /* Provide a device-tree.  */
    env->gpr[3] = bi->fdt;
    env->nip = bi->bootstrap_pc;

    /* Create a mapping for the kernel.  */
    mmubooke_create_initial_mapping(env, 0, 0);
    env->gpr[6] = tswap32(EPAPR_MAGIC);
    env->gpr[7] = bi->ima_size;
}

#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
static int xilinx_load_device_tree(hwaddr addr,
                                      uint32_t ramsize,
                                      hwaddr initrd_base,
                                      hwaddr initrd_size,
                                      const char *kernel_cmdline)
{
    char *path;
    int fdt_size;
    void *fdt = NULL;
    int r;
    const char *dtb_filename;

    dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
    if (dtb_filename) {
        fdt = load_device_tree(dtb_filename, &fdt_size);
        if (!fdt) {
            error_report("Error while loading device tree file '%s'",
                dtb_filename);
        }
    } else {
        /* Try the local "ppc.dtb" override.  */
        fdt = load_device_tree("ppc.dtb", &fdt_size);
        if (!fdt) {
            path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
            if (path) {
                fdt = load_device_tree(path, &fdt_size);
                g_free(path);
            }
        }
    }
    if (!fdt) {
        return 0;
    }
    r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
    if (r < 0)
        fprintf(stderr, "couldn't set /chosen/bootargs\n");
    cpu_physical_memory_write(addr, fdt, fdt_size);
    return fdt_size;
}

static void virtex_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    MemoryRegion *address_space_mem = get_system_memory();
    DeviceState *dev;
    PowerPCCPU *cpu;
    CPUPPCState *env;
    hwaddr ram_base = 0;
    DriveInfo *dinfo;
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32], *cpu_irq;
    int kernel_size;
    int i;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "440-Xilinx";
    }

    cpu = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000);
    env = &cpu->env;
    qemu_register_reset(main_cpu_reset, cpu);

    memory_region_init_ram(phys_ram, NULL, "ram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),
                          FLASH_SIZE >> 16,
                          1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
    dev = qdev_create(NULL, "xlnx.xps-intc");
    qdev_prop_set_uint32(dev, "kind-of-intr", 0);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
                   115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);

    /* 2 timers at irq 2 @ 62 Mhz.  */
    dev = qdev_create(NULL, "xlnx.xps-timer");
    qdev_prop_set_uint32(dev, "one-timer-only", 0);
    qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);

    if (kernel_filename) {
        uint64_t entry, low, high;
        hwaddr boot_offset;

        /* Boots a kernel elf binary.  */
        kernel_size = load_elf(kernel_filename, NULL, NULL,
                               &entry, &low, &high, 1, ELF_MACHINE, 0);
        boot_info.bootstrap_pc = entry & 0x00ffffff;

        if (kernel_size < 0) {
            boot_offset = 0x1200000;
            /* If we failed loading ELF's try a raw image.  */
            kernel_size = load_image_targphys(kernel_filename,
                                              boot_offset,
                                              ram_size);
            boot_info.bootstrap_pc = boot_offset;
            high = boot_info.bootstrap_pc + kernel_size + 8192;
        }

        boot_info.ima_size = kernel_size;

        /* Provide a device-tree.  */
        boot_info.fdt = high + (8192 * 2);
        boot_info.fdt &= ~8191;
        xilinx_load_device_tree(boot_info.fdt, ram_size, 0, 0, kernel_cmdline);
    }
    env->load_info = &boot_info;
}

static QEMUMachine virtex_machine = {
    .name = "virtex-ml507",
    .desc = "Xilinx Virtex ML507 reference design",
    .init = virtex_init,
};

static void virtex_machine_init(void)
{
    qemu_register_machine(&virtex_machine);
}

machine_init(virtex_machine_init);
Commit	Line	Data
2c50e26e EI	1	/*
	2	* Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
	3	*
	4	* Copyright (c) 2010 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
83c9f4ca PB	25	#include "hw/sysbus.h"
83c9f4ca PB	26	#include "hw/hw.h"
0d09e41a PB	27	#include "hw/char/serial.h"
0d09e41a PB	28	#include "hw/block/flash.h"
9c17d615	29	#include "sysemu/sysemu.h"
bd2be150	30	#include "hw/devices.h"
83c9f4ca	31	#include "hw/boards.h"
9c17d615	32	#include "sysemu/device_tree.h"
83c9f4ca	33	#include "hw/loader.h"
2c50e26e	34	#include "elf.h"
1de7afc9	35	#include "qemu/log.h"
022c62cb	36	#include "exec/address-spaces.h"
2c50e26e	37
0d09e41a PB	38	#include "hw/ppc/ppc.h"
0d09e41a PB	39	#include "hw/ppc/ppc4xx.h"
47b43a1f	40	#include "ppc405.h"
2c50e26e	41
9c17d615	42	#include "sysemu/blockdev.h"
d5001cf7	43	#include "qapi/qmp/qerror.h"
2c50e26e EI	44
	45	#define EPAPR_MAGIC (0x45504150)
	46	#define FLASH_SIZE (16 * 1024 * 1024)
	47
81cce07e PC	48	#define INTC_BASEADDR 0x81800000
	49	#define UART16550_BASEADDR 0x83e01003
	50	#define TIMER_BASEADDR 0x83c00000
	51	#define PFLASH_BASEADDR 0xfc000000
	52
	53	#define TIMER_IRQ 3
	54	#define UART16550_IRQ 9
	55
2c50e26e EI	56	static struct boot_info
	57	{
	58	uint32_t bootstrap_pc;
	59	uint32_t cmdline;
	60	uint32_t fdt;
	61	uint32_t ima_size;
	62	void *vfdt;
	63	} boot_info;
	64
	65	/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
e2684c0b	66	static void mmubooke_create_initial_mapping(CPUPPCState *env,
2c50e26e	67	target_ulong va,
a8170e5e	68	hwaddr pa)
2c50e26e	69	{
1c53accc	70	ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
2c50e26e EI	71
	72	tlb->attr = 0;
	73	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
	74	tlb->size = 1 << 31; /* up to 0x80000000 */
	75	tlb->EPN = va & TARGET_PAGE_MASK;
	76	tlb->RPN = pa & TARGET_PAGE_MASK;
	77	tlb->PID = 0;
	78
1c53accc	79	tlb = &env->tlb.tlbe[1];
2c50e26e EI	80	tlb->attr = 0;
	81	tlb->prot = PAGE_VALID \| ((PAGE_READ \| PAGE_WRITE \| PAGE_EXEC) << 4);
	82	tlb->size = 1 << 31; /* up to 0xffffffff */
	83	tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
	84	tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
	85	tlb->PID = 0;
	86	}
	87
68281699 AF	88	static PowerPCCPU ppc440_init_xilinx(ram_addr_t ram_size,
	89	int do_init,
	90	const char *cpu_model,
	91	uint32_t sysclk)
2c50e26e	92	{
d1d4938b	93	PowerPCCPU *cpu;
e2684c0b	94	CPUPPCState *env;
2c50e26e EI	95	qemu_irq *irqs;
2c50e26e EI	96
d1d4938b AF	97	cpu = cpu_ppc_init(cpu_model);
d1d4938b AF	98	if (cpu == NULL) {
2c50e26e EI	99	fprintf(stderr, "Unable to initialize CPU!\n");
	100	exit(1);
	101	}
d1d4938b	102	env = &cpu->env;
2c50e26e	103
a34a92b9	104	ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
2c50e26e EI	105
	106	ppc_dcr_init(env, NULL, NULL);
	107
	108	/* interrupt controller */
7267c094	109	irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2c50e26e EI	110	irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2c50e26e EI	111	irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
49a2942d	112	ppcuic_init(env, irqs, 0x0C0, 0, 1);
68281699	113	return cpu;
2c50e26e EI	114	}
	115
	116	static void main_cpu_reset(void *opaque)
	117	{
f8031482 AF	118	PowerPCCPU *cpu = opaque;
f8031482 AF	119	CPUPPCState *env = &cpu->env;
2c50e26e EI	120	struct boot_info *bi = env->load_info;
2c50e26e EI	121
f8031482	122	cpu_reset(CPU(cpu));
2c50e26e EI	123	/* Linux Kernel Parameters (passing device tree):
	124	* r3: pointer to the fdt
	125	* r4: 0
	126	* r5: 0
	127	* r6: epapr magic
	128	* r7: size of IMA in bytes
	129	* r8: 0
	130	* r9: 0
	131	*/
	132	env->gpr[1] = (16<<20) - 8;
	133	/* Provide a device-tree. */
	134	env->gpr[3] = bi->fdt;
	135	env->nip = bi->bootstrap_pc;
	136
	137	/* Create a mapping for the kernel. */
	138	mmubooke_create_initial_mapping(env, 0, 0);
	139	env->gpr[6] = tswap32(EPAPR_MAGIC);
	140	env->gpr[7] = bi->ima_size;
	141	}
	142
	143	#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
a8170e5e	144	static int xilinx_load_device_tree(hwaddr addr,
2c50e26e	145	uint32_t ramsize,
a8170e5e AK	146	hwaddr initrd_base,
a8170e5e AK	147	hwaddr initrd_size,
2c50e26e EI	148	const char *kernel_cmdline)
	149	{
	150	char *path;
	151	int fdt_size;
daf285b6	152	void *fdt = NULL;
2c50e26e	153	int r;
daf285b6	154	const char *dtb_filename;
2c50e26e	155
daf285b6 EV	156	dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
	157	if (dtb_filename) {
	158	fdt = load_device_tree(dtb_filename, &fdt_size);
	159	if (!fdt) {
	160	error_report("Error while loading device tree file '%s'",
	161	dtb_filename);
2c50e26e	162	}
daf285b6 EV	163	} else {
	164	/* Try the local "ppc.dtb" override. */
	165	fdt = load_device_tree("ppc.dtb", &fdt_size);
3b2e3dc9	166	if (!fdt) {
daf285b6 EV	167	path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
	168	if (path) {
	169	fdt = load_device_tree(path, &fdt_size);
	170	g_free(path);
	171	}
3b2e3dc9	172	}
2c50e26e	173	}
daf285b6 EV	174	if (!fdt) {
	175	return 0;
	176	}
5a4348d1	177	r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
2c50e26e EI	178	if (r < 0)
2c50e26e EI	179	fprintf(stderr, "couldn't set /chosen/bootargs\n");
e1fe50dc	180	cpu_physical_memory_write(addr, fdt, fdt_size);
2c50e26e EI	181	return fdt_size;
	182	}
	183
5f072e1f	184	static void virtex_init(QEMUMachineInitArgs *args)
2c50e26e	185	{
5f072e1f EH	186	ram_addr_t ram_size = args->ram_size;
	187	const char *cpu_model = args->cpu_model;
	188	const char *kernel_filename = args->kernel_filename;
	189	const char *kernel_cmdline = args->kernel_cmdline;
39186d8a	190	MemoryRegion *address_space_mem = get_system_memory();
2c50e26e	191	DeviceState *dev;
68281699	192	PowerPCCPU *cpu;
e2684c0b	193	CPUPPCState *env;
a8170e5e	194	hwaddr ram_base = 0;
2c50e26e	195	DriveInfo *dinfo;
333b13fc	196	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
2c50e26e	197	qemu_irq irq[32], *cpu_irq;
2c50e26e EI	198	int kernel_size;
	199	int i;
	200
	201	/* init CPUs */
	202	if (cpu_model == NULL) {
	203	cpu_model = "440-Xilinx";
	204	}
	205
68281699 AF	206	cpu = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000);
68281699 AF	207	env = &cpu->env;
f8031482	208	qemu_register_reset(main_cpu_reset, cpu);
2c50e26e	209
2c9b15ca	210	memory_region_init_ram(phys_ram, NULL, "ram", ram_size);
c5705a77	211	vmstate_register_ram_global(phys_ram);
333b13fc	212	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
2c50e26e	213
2c50e26e	214	dinfo = drive_get(IF_PFLASH, 0, 0);
81cce07e	215	pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
2c50e26e EI	216	dinfo ? dinfo->bdrv : NULL, (64 * 1024),
2c50e26e EI	217	FLASH_SIZE >> 16,
01e0451a	218	1, 0x89, 0x18, 0x0000, 0x0, 1);
2c50e26e EI	219
2c50e26e EI	220	cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
13c9bfbf PC	221	dev = qdev_create(NULL, "xlnx.xps-intc");
	222	qdev_prop_set_uint32(dev, "kind-of-intr", 0);
	223	qdev_init_nofail(dev);
	224	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
	225	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
2c50e26e EI	226	for (i = 0; i < 32; i++) {
	227	irq[i] = qdev_get_gpio_in(dev, i);
	228	}
	229
81cce07e PC	230	serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
81cce07e PC	231	115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
2c50e26e EI	232
2c50e26e EI	233	/* 2 timers at irq 2 @ 62 Mhz. */
29873712 PC	234	dev = qdev_create(NULL, "xlnx.xps-timer");
	235	qdev_prop_set_uint32(dev, "one-timer-only", 0);
	236	qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
	237	qdev_init_nofail(dev);
	238	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
	239	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
2c50e26e EI	240
	241	if (kernel_filename) {
	242	uint64_t entry, low, high;
a8170e5e	243	hwaddr boot_offset;
2c50e26e EI	244
	245	/* Boots a kernel elf binary. */
	246	kernel_size = load_elf(kernel_filename, NULL, NULL,
	247	&entry, &low, &high, 1, ELF_MACHINE, 0);
2c50e26e EI	248	boot_info.bootstrap_pc = entry & 0x00ffffff;
	249
	250	if (kernel_size < 0) {
	251	boot_offset = 0x1200000;
	252	/* If we failed loading ELF's try a raw image. */
	253	kernel_size = load_image_targphys(kernel_filename,
	254	boot_offset,
	255	ram_size);
	256	boot_info.bootstrap_pc = boot_offset;
	257	high = boot_info.bootstrap_pc + kernel_size + 8192;
	258	}
	259
	260	boot_info.ima_size = kernel_size;
	261
	262	/* Provide a device-tree. */
	263	boot_info.fdt = high + (8192 * 2);
	264	boot_info.fdt &= ~8191;
	265	xilinx_load_device_tree(boot_info.fdt, ram_size, 0, 0, kernel_cmdline);
	266	}
	267	env->load_info = &boot_info;
	268	}
	269
	270	static QEMUMachine virtex_machine = {
	271	.name = "virtex-ml507",
	272	.desc = "Xilinx Virtex ML507 reference design",
	273	.init = virtex_init,
	274	};
	275
	276	static void virtex_machine_init(void)
	277	{
	278	qemu_register_machine(&virtex_machine);
	279	}
	280
	281	machine_init(virtex_machine_init);