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xen: add a dummy xc_hvm_inject_msi for Xen < 4.2
[qemu.git] / hw / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
3ada003a 56#include "dma.h"
87ecb68b
PB		 57#include "qemu-timer.h"
58#include "net.h"
254111ec 59#include "loader.h"
1ca4d09a 60#include "sysemu.h"
bf6b87a8 61#include "iov.h"
a41b2ff2 62
a41b2ff2
PB		 63/* debug RTL8139 card */
64//#define DEBUG_RTL8139 1
65
6cadb320
FB		 66#define PCI_FREQUENCY 33000000L
67
a41b2ff2
PB		 68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
18dabfd1
BP		 75#define ETHER_ADDR_LEN 6
76#define ETHER_TYPE_LEN 2
77#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78#define ETH_P_IP 0x0800 /* Internet Protocol packet */
79#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80#define ETH_MTU 1500
81
82#define VLAN_TCI_LEN 2
83#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
6cadb320 85#if defined (DEBUG_RTL8139)
7cdeb319
BP		 86# define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 88#else
c6a0487b 89static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 90{
91 return 0;
92}
6cadb320
FB		 93#endif
94
a41b2ff2
PB		 95/* Symbolic offsets to registers. */
96enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142};
143
144enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148};
149
150enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155};
156
157/* C+ mode */
158enum CplusCmdBits {
6cadb320
FB		 159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 163};
164
165/* Interrupt register bits, using my own meaningful names. */
166enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
170 RxUnderrun = 0x20,
171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178};
179
180enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187};
188enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198};
199
200/* Bits in RxConfig. */
201enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208};
209
210/* Bits in TxConfig. */
211enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227};
228
229
230/* Transmit Status of All Descriptors (TSAD) Register */
231enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248};
249
250
251/* Bits in Config1 */
252enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263};
264
265/* Bits in Config3 */
266enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275};
276
277/* Bits in Config4 */
278enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280};
281
282/* Bits in Config5 */
283enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291};
292
293enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310};
311
312/* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314/*
315enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321*/
322enum CSCRBits {
5fafdf24 323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332};
333
334enum Cfg9346Bits {
eb46c5ed
JW		 335 Cfg9346_Normal = 0x00,
336 Cfg9346_Autoload = 0x40,
337 Cfg9346_Programming = 0x80,
338 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 339};
340
341typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
c227f099 352} chip_t;
a41b2ff2
PB		 353
354enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357};
358
359#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
6cadb320
FB		 363#define RTL8139_PCI_REVID_8139 0x10
364#define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
a41b2ff2
PB		 368/* Size is 64 * 16bit words */
369#define EEPROM_9346_ADDR_BITS 6
370#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373enum Chip9346Operation
374{
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382};
383
384enum Chip9346Mode
385{
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392};
393
394typedef struct EEprom9346
395{
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407} EEprom9346;
408
6cadb320
FB		 409typedef struct RTL8139TallyCounters
410{
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425} RTL8139TallyCounters;
426
427/* Clears all tally counters */
428static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
a41b2ff2 430typedef struct RTL8139State {
efd6dd45 431 PCIDevice dev;
a41b2ff2
PB		 432 uint8_t phys[8]; /* mac address */
433 uint8_t mult[8]; /* multicast mask array */
434
6cadb320 435 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 436 uint32_t TxAddr[4]; /* TxAddr0 */
437 uint32_t RxBuf; /* Receive buffer */
438 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439 uint32_t RxBufPtr;
440 uint32_t RxBufAddr;
441
442 uint16_t IntrStatus;
443 uint16_t IntrMask;
444
445 uint32_t TxConfig;
446 uint32_t RxConfig;
447 uint32_t RxMissed;
448
449 uint16_t CSCR;
450
451 uint8_t Cfg9346;
452 uint8_t Config0;
453 uint8_t Config1;
454 uint8_t Config3;
455 uint8_t Config4;
456 uint8_t Config5;
457
458 uint8_t clock_enabled;
459 uint8_t bChipCmdState;
460
461 uint16_t MultiIntr;
462
463 uint16_t BasicModeCtrl;
464 uint16_t BasicModeStatus;
465 uint16_t NWayAdvert;
466 uint16_t NWayLPAR;
467 uint16_t NWayExpansion;
468
469 uint16_t CpCmd;
470 uint8_t TxThresh;
471
1673ad51 472 NICState *nic;
254111ec 473 NICConf conf;
a41b2ff2
PB		 474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
2c3891ab
AL		 479 uint32_t cplus_enabled;
480
a41b2ff2
PB		 481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
6cadb320
FB		 488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
05447803 503 int64_t TimerExpire;
6cadb320 504
bd80f3fc
AK		 505 MemoryRegion bar_io;
506 MemoryRegion bar_mem;
507
c574ba5a
AW		 508 /* Support migration to/from old versions */
509 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 510} RTL8139State;
511
3ada003a
EGM		 512/* Writes tally counters to memory via DMA */
513static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
514
05447803
FZ		 515static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
516
9596ebb7 517static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 518{
7cdeb319 519 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 520
521 switch (command & Chip9346_op_mask)
522 {
523 case Chip9346_op_read:
524 {
525 eeprom->address = command & EEPROM_9346_ADDR_MASK;
526 eeprom->output = eeprom->contents[eeprom->address];
527 eeprom->eedo = 0;
528 eeprom->tick = 0;
529 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 530 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
531 eeprom->address, eeprom->output);
a41b2ff2
PB		 532 }
533 break;
534
535 case Chip9346_op_write:
536 {
537 eeprom->address = command & EEPROM_9346_ADDR_MASK;
538 eeprom->input = 0;
539 eeprom->tick = 0;
540 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 541 DPRINTF("eeprom begin write to address 0x%02x\n",
542 eeprom->address);
a41b2ff2
PB		 543 }
544 break;
545 default:
546 eeprom->mode = Chip9346_none;
547 switch (command & Chip9346_op_ext_mask)
548 {
549 case Chip9346_op_write_enable:
7cdeb319 550 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 551 break;
552 case Chip9346_op_write_all:
7cdeb319 553 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 554 break;
555 case Chip9346_op_write_disable:
7cdeb319 556 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 557 break;
558 }
559 break;
560 }
561}
562
9596ebb7 563static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 564{
565 int bit = eeprom->eedi?1:0;
566
567 ++ eeprom->tick;
568
7cdeb319
BP		 569 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
570 eeprom->eedo);
a41b2ff2
PB		 571
572 switch (eeprom->mode)
573 {
574 case Chip9346_enter_command_mode:
575 if (bit)
576 {
577 eeprom->mode = Chip9346_read_command;
578 eeprom->tick = 0;
579 eeprom->input = 0;
7cdeb319 580 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 581 }
582 break;
583
584 case Chip9346_read_command:
585 eeprom->input = (eeprom->input << 1) | (bit & 1);
586 if (eeprom->tick == 8)
587 {
588 prom9346_decode_command(eeprom, eeprom->input & 0xff);
589 }
590 break;
591
592 case Chip9346_data_read:
593 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
594 eeprom->output <<= 1;
595 if (eeprom->tick == 16)
596 {
6cadb320
FB		 597#if 1
598 // the FreeBSD drivers (rl and re) don't explicitly toggle
599 // CS between reads (or does setting Cfg9346 to 0 count too?),
600 // so we need to enter wait-for-command state here
601 eeprom->mode = Chip9346_enter_command_mode;
602 eeprom->input = 0;
603 eeprom->tick = 0;
604
7cdeb319 605 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 606#else
607 // original behaviour
a41b2ff2
PB		 608 ++eeprom->address;
609 eeprom->address &= EEPROM_9346_ADDR_MASK;
610 eeprom->output = eeprom->contents[eeprom->address];
611 eeprom->tick = 0;
612
7cdeb319
BP		 613 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
614 eeprom->address, eeprom->output);
a41b2ff2
PB		 615#endif
616 }
617 break;
618
619 case Chip9346_data_write:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
7cdeb319
BP		 623 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
624 eeprom->address, eeprom->input);
6cadb320 625
a41b2ff2
PB		 626 eeprom->contents[eeprom->address] = eeprom->input;
627 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 case Chip9346_data_write_all:
634 eeprom->input = (eeprom->input << 1) | (bit & 1);
635 if (eeprom->tick == 16)
636 {
637 int i;
638 for (i = 0; i < EEPROM_9346_SIZE; i++)
639 {
640 eeprom->contents[i] = eeprom->input;
641 }
7cdeb319 642 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 643
a41b2ff2
PB		 644 eeprom->mode = Chip9346_enter_command_mode;
645 eeprom->tick = 0;
646 eeprom->input = 0;
647 }
648 break;
649
650 default:
651 break;
652 }
653}
654
9596ebb7 655static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 656{
657 EEprom9346 *eeprom = &s->eeprom;
658 if (!eeprom->eecs)
659 return 0;
660
661 return eeprom->eedo;
662}
663
9596ebb7
PB		 664/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
665static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 666{
667 EEprom9346 *eeprom = &s->eeprom;
668 uint8_t old_eecs = eeprom->eecs;
669 uint8_t old_eesk = eeprom->eesk;
670
671 eeprom->eecs = eecs;
672 eeprom->eesk = eesk;
673 eeprom->eedi = eedi;
674
7cdeb319
BP		 675 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
676 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 677
678 if (!old_eecs && eecs)
679 {
680 /* Synchronize start */
681 eeprom->tick = 0;
682 eeprom->input = 0;
683 eeprom->output = 0;
684 eeprom->mode = Chip9346_enter_command_mode;
685
7cdeb319 686 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 687 }
688
689 if (!eecs)
690 {
7cdeb319 691 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 692 return;
693 }
694
695 if (!old_eesk && eesk)
696 {
697 /* SK front rules */
698 prom9346_shift_clock(eeprom);
699 }
700}
701
702static void rtl8139_update_irq(RTL8139State *s)
703{
704 int isr;
705 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 706
7cdeb319
BP		 707 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
708 s->IntrMask);
6cadb320 709
efd6dd45 710 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 711}
712
a41b2ff2
PB		 713static int rtl8139_RxWrap(RTL8139State *s)
714{
715 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
716 return (s->RxConfig & (1 << 7));
717}
718
719static int rtl8139_receiver_enabled(RTL8139State *s)
720{
721 return s->bChipCmdState & CmdRxEnb;
722}
723
724static int rtl8139_transmitter_enabled(RTL8139State *s)
725{
726 return s->bChipCmdState & CmdTxEnb;
727}
728
729static int rtl8139_cp_receiver_enabled(RTL8139State *s)
730{
731 return s->CpCmd & CPlusRxEnb;
732}
733
734static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
735{
736 return s->CpCmd & CPlusTxEnb;
737}
738
739static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
740{
741 if (s->RxBufAddr + size > s->RxBufferSize)
742 {
743 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
744
745 /* write packet data */
ccf1d14a 746 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 747 {
7cdeb319 748 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 749
750 if (size > wrapped)
751 {
3ada003a
EGM		 752 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
753 buf, size-wrapped);
a41b2ff2
PB		 754 }
755
756 /* reset buffer pointer */
757 s->RxBufAddr = 0;
758
3ada003a
EGM		 759 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
760 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 761
762 s->RxBufAddr = wrapped;
763
764 return;
765 }
766 }
767
768 /* non-wrapping path or overwrapping enabled */
3ada003a 769 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 770
771 s->RxBufAddr += size;
772}
773
774#define MIN_BUF_SIZE 60
3ada003a 775static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 776{
777#if TARGET_PHYS_ADDR_BITS > 32
c227f099 778 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 779#else
780 return low;
781#endif
782}
783
1673ad51 784static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 785{
1673ad51 786 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 787 int avail;
788
aa1f17c1 789 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 790 if (!s->clock_enabled)
791 return 1;
792 if (!rtl8139_receiver_enabled(s))
793 return 1;
ff71f2e8
JW		 794 /* network/host communication happens only in normal mode */
795 if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal)
796 return 0;
a41b2ff2
PB		 797
798 if (rtl8139_cp_receiver_enabled(s)) {
799 /* ??? Flow control not implemented in c+ mode.
800 This is a hack to work around slirp deficiencies anyway. */
801 return 1;
802 } else {
803 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
804 s->RxBufferSize);
805 return (avail == 0 || avail >= 1514);
806 }
807}
808
1673ad51 809static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 810{
1673ad51 811 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 812 /* size is the length of the buffer passed to the driver */
4f1c942b 813 int size = size_;
18dabfd1 814 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 815
816 uint32_t packet_header = 0;
817
18dabfd1 818 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 819 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 820 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
821
7cdeb319 822 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 823
824 /* test if board clock is stopped */
825 if (!s->clock_enabled)
826 {
7cdeb319 827 DPRINTF("stopped ==========================\n");
4f1c942b 828 return -1;
a41b2ff2
PB		 829 }
830
831 /* first check if receiver is enabled */
832
833 if (!rtl8139_receiver_enabled(s))
834 {
7cdeb319 835 DPRINTF("receiver disabled ================\n");
4f1c942b 836 return -1;
a41b2ff2
PB		 837 }
838
ff71f2e8
JW		 839 /* check whether we are in normal mode */
840 if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal) {
841 DPRINTF("not in normal op mode\n");
842 return -1;
843 }
844
a41b2ff2
PB		 845 /* XXX: check this */
846 if (s->RxConfig & AcceptAllPhys) {
847 /* promiscuous: receive all */
7cdeb319 848 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 849
850 } else {
851 if (!memcmp(buf, broadcast_macaddr, 6)) {
852 /* broadcast address */
853 if (!(s->RxConfig & AcceptBroadcast))
854 {
7cdeb319 855 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 856
857 /* update tally counter */
858 ++s->tally_counters.RxERR;
859
4f1c942b 860 return size;
a41b2ff2
PB		 861 }
862
863 packet_header |= RxBroadcast;
864
7cdeb319 865 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 866
867 /* update tally counter */
868 ++s->tally_counters.RxOkBrd;
869
a41b2ff2
PB		 870 } else if (buf[0] & 0x01) {
871 /* multicast */
872 if (!(s->RxConfig & AcceptMulticast))
873 {
7cdeb319 874 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 875
876 /* update tally counter */
877 ++s->tally_counters.RxERR;
878
4f1c942b 879 return size;
a41b2ff2
PB		 880 }
881
882 int mcast_idx = compute_mcast_idx(buf);
883
884 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
885 {
7cdeb319 886 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 887
888 /* update tally counter */
889 ++s->tally_counters.RxERR;
890
4f1c942b 891 return size;
a41b2ff2
PB		 892 }
893
894 packet_header |= RxMulticast;
895
7cdeb319 896 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 897
898 /* update tally counter */
899 ++s->tally_counters.RxOkMul;
900
a41b2ff2 901 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 902 s->phys[1] == buf[1] &&
903 s->phys[2] == buf[2] &&
904 s->phys[3] == buf[3] &&
905 s->phys[4] == buf[4] &&
a41b2ff2
PB		 906 s->phys[5] == buf[5]) {
907 /* match */
908 if (!(s->RxConfig & AcceptMyPhys))
909 {
7cdeb319 910 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 911
912 /* update tally counter */
913 ++s->tally_counters.RxERR;
914
4f1c942b 915 return size;
a41b2ff2
PB		 916 }
917
918 packet_header |= RxPhysical;
919
7cdeb319 920 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 921
922 /* update tally counter */
923 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 924
925 } else {
926
7cdeb319 927 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 928
929 /* update tally counter */
930 ++s->tally_counters.RxERR;
931
4f1c942b 932 return size;
a41b2ff2
PB		 933 }
934 }
935
18dabfd1
BP		 936 /* if too small buffer, then expand it
937 * Include some tailroom in case a vlan tag is later removed. */
938 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 939 memcpy(buf1, buf, size);
18dabfd1 940 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 941 buf = buf1;
18dabfd1
BP		 942 if (size < MIN_BUF_SIZE) {
943 size = MIN_BUF_SIZE;
944 }
a41b2ff2
PB		 945 }
946
947 if (rtl8139_cp_receiver_enabled(s))
948 {
7cdeb319 949 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 950
951 /* begin C+ receiver mode */
952
953/* w0 ownership flag */
954#define CP_RX_OWN (1<<31)
955/* w0 end of ring flag */
956#define CP_RX_EOR (1<<30)
957/* w0 bits 0...12 : buffer size */
958#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
959/* w1 tag available flag */
960#define CP_RX_TAVA (1<<16)
961/* w1 bits 0...15 : VLAN tag */
962#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
963/* w2 low 32bit of Rx buffer ptr */
964/* w3 high 32bit of Rx buffer ptr */
965
966 int descriptor = s->currCPlusRxDesc;
3ada003a 967 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 968
969 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
970 cplus_rx_ring_desc += 16 * descriptor;
971
7cdeb319 972 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 973 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 974 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 975
976 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
977
a6a29eea 978 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
a41b2ff2 979 rxdw0 = le32_to_cpu(val);
a6a29eea 980 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 981 rxdw1 = le32_to_cpu(val);
a6a29eea 982 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 983 rxbufLO = le32_to_cpu(val);
a6a29eea 984 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 985 rxbufHI = le32_to_cpu(val);
986
7cdeb319
BP		 987 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
988 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 989
990 if (!(rxdw0 & CP_RX_OWN))
991 {
7cdeb319
BP		 992 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
993 descriptor);
6cadb320 994
a41b2ff2
PB		 995 s->IntrStatus |= RxOverflow;
996 ++s->RxMissed;
6cadb320
FB		 997
998 /* update tally counter */
999 ++s->tally_counters.RxERR;
1000 ++s->tally_counters.MissPkt;
1001
a41b2ff2 1002 rtl8139_update_irq(s);
4f1c942b 1003 return size_;
a41b2ff2
PB		 1004 }
1005
1006 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1007
18dabfd1
BP		 1008 /* write VLAN info to descriptor variables. */
1009 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1010 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1011 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1012 size -= VLAN_HLEN;
1013 /* if too small buffer, use the tailroom added duing expansion */
1014 if (size < MIN_BUF_SIZE) {
1015 size = MIN_BUF_SIZE;
1016 }
1017
1018 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1019 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1020 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1021 &dot1q_buf[ETHER_TYPE_LEN]);
1022
7cdeb319
BP		 1023 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1024 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1025 } else {
1026 /* reset VLAN tag flag */
1027 rxdw1 &= ~CP_RX_TAVA;
1028 }
1029
6cadb320
FB		 1030 /* TODO: scatter the packet over available receive ring descriptors space */
1031
a41b2ff2
PB		 1032 if (size+4 > rx_space)
1033 {
7cdeb319
BP		 1034 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1035 descriptor, rx_space, size);
6cadb320 1036
a41b2ff2
PB		 1037 s->IntrStatus |= RxOverflow;
1038 ++s->RxMissed;
6cadb320
FB		 1039
1040 /* update tally counter */
1041 ++s->tally_counters.RxERR;
1042 ++s->tally_counters.MissPkt;
1043
a41b2ff2 1044 rtl8139_update_irq(s);
4f1c942b 1045 return size_;
a41b2ff2
PB		 1046 }
1047
3ada003a 1048 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1049
1050 /* receive/copy to target memory */
18dabfd1 1051 if (dot1q_buf) {
3ada003a
EGM		 1052 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1053 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1054 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1055 size - 2 * ETHER_ADDR_LEN);
18dabfd1 1056 } else {
3ada003a 1057 pci_dma_write(&s->dev, rx_addr, buf, size);
18dabfd1 1058 }
a41b2ff2 1059
6cadb320
FB		 1060 if (s->CpCmd & CPlusRxChkSum)
1061 {
1062 /* do some packet checksumming */
1063 }
1064
a41b2ff2 1065 /* write checksum */
18dabfd1 1066 val = cpu_to_le32(crc32(0, buf, size_));
3ada003a 1067 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1068
1069/* first segment of received packet flag */
1070#define CP_RX_STATUS_FS (1<<29)
1071/* last segment of received packet flag */
1072#define CP_RX_STATUS_LS (1<<28)
1073/* multicast packet flag */
1074#define CP_RX_STATUS_MAR (1<<26)
1075/* physical-matching packet flag */
1076#define CP_RX_STATUS_PAM (1<<25)
1077/* broadcast packet flag */
1078#define CP_RX_STATUS_BAR (1<<24)
1079/* runt packet flag */
1080#define CP_RX_STATUS_RUNT (1<<19)
1081/* crc error flag */
1082#define CP_RX_STATUS_CRC (1<<18)
1083/* IP checksum error flag */
1084#define CP_RX_STATUS_IPF (1<<15)
1085/* UDP checksum error flag */
1086#define CP_RX_STATUS_UDPF (1<<14)
1087/* TCP checksum error flag */
1088#define CP_RX_STATUS_TCPF (1<<13)
1089
1090 /* transfer ownership to target */
1091 rxdw0 &= ~CP_RX_OWN;
1092
1093 /* set first segment bit */
1094 rxdw0 |= CP_RX_STATUS_FS;
1095
1096 /* set last segment bit */
1097 rxdw0 |= CP_RX_STATUS_LS;
1098
1099 /* set received packet type flags */
1100 if (packet_header & RxBroadcast)
1101 rxdw0 |= CP_RX_STATUS_BAR;
1102 if (packet_header & RxMulticast)
1103 rxdw0 |= CP_RX_STATUS_MAR;
1104 if (packet_header & RxPhysical)
1105 rxdw0 |= CP_RX_STATUS_PAM;
1106
1107 /* set received size */
1108 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1109 rxdw0 |= (size+4);
1110
a41b2ff2
PB		 1111 /* update ring data */
1112 val = cpu_to_le32(rxdw0);
3ada003a 1113 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1114 val = cpu_to_le32(rxdw1);
3ada003a 1115 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1116
6cadb320
FB		 1117 /* update tally counter */
1118 ++s->tally_counters.RxOk;
1119
a41b2ff2
PB		 1120 /* seek to next Rx descriptor */
1121 if (rxdw0 & CP_RX_EOR)
1122 {
1123 s->currCPlusRxDesc = 0;
1124 }
1125 else
1126 {
1127 ++s->currCPlusRxDesc;
1128 }
1129
7cdeb319 1130 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1131
1132 }
1133 else
1134 {
7cdeb319 1135 DPRINTF("in ring Rx mode ================\n");
6cadb320 1136
a41b2ff2
PB		 1137 /* begin ring receiver mode */
1138 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1139
1140 /* if receiver buffer is empty then avail == 0 */
1141
1142 if (avail != 0 && size + 8 >= avail)
1143 {
7cdeb319
BP		 1144 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1145 "read 0x%04x === available 0x%04x need 0x%04x\n",
1146 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1147
a41b2ff2
PB		 1148 s->IntrStatus |= RxOverflow;
1149 ++s->RxMissed;
1150 rtl8139_update_irq(s);
4f1c942b 1151 return size_;
a41b2ff2
PB		 1152 }
1153
1154 packet_header |= RxStatusOK;
1155
1156 packet_header |= (((size+4) << 16) & 0xffff0000);
1157
1158 /* write header */
1159 uint32_t val = cpu_to_le32(packet_header);
1160
1161 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1162
1163 rtl8139_write_buffer(s, buf, size);
1164
1165 /* write checksum */
ccf1d14a 1166 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1167 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1168
1169 /* correct buffer write pointer */
1170 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1171
1172 /* now we can signal we have received something */
1173
7cdeb319
BP		 1174 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1175 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1176 }
1177
1178 s->IntrStatus |= RxOK;
6cadb320
FB		 1179
1180 if (do_interrupt)
1181 {
1182 rtl8139_update_irq(s);
1183 }
4f1c942b
MM		 1184
1185 return size_;
6cadb320
FB		 1186}
1187
1673ad51 1188static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1189{
1673ad51 1190 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1191}
1192
1193static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1194{
1195 s->RxBufferSize = bufferSize;
1196 s->RxBufPtr = 0;
1197 s->RxBufAddr = 0;
1198}
1199
7f23f812 1200static void rtl8139_reset(DeviceState *d)
a41b2ff2 1201{
7f23f812 1202 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1203 int i;
1204
1205 /* restore MAC address */
254111ec 1206 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1207
1208 /* reset interrupt mask */
1209 s->IntrStatus = 0;
1210 s->IntrMask = 0;
1211
1212 rtl8139_update_irq(s);
1213
a41b2ff2
PB		 1214 /* mark all status registers as owned by host */
1215 for (i = 0; i < 4; ++i)
1216 {
1217 s->TxStatus[i] = TxHostOwns;
1218 }
1219
1220 s->currTxDesc = 0;
1221 s->currCPlusRxDesc = 0;
1222 s->currCPlusTxDesc = 0;
1223
1224 s->RxRingAddrLO = 0;
1225 s->RxRingAddrHI = 0;
1226
1227 s->RxBuf = 0;
1228
1229 rtl8139_reset_rxring(s, 8192);
1230
1231 /* ACK the reset */
1232 s->TxConfig = 0;
1233
1234#if 0
1235// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1236 s->clock_enabled = 0;
1237#else
6cadb320 1238 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1239 s->clock_enabled = 1;
1240#endif
1241
1242 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1243
1244 /* set initial state data */
1245 s->Config0 = 0x0; /* No boot ROM */
1246 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1247 s->Config3 = 0x1; /* fast back-to-back compatible */
1248 s->Config5 = 0x0;
1249
5fafdf24 1250 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1251
1252 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1253 s->cplus_enabled = 0;
1254
a41b2ff2
PB		 1255
1256// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1257// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1258 s->BasicModeCtrl = 0x1000; // autonegotiation
1259
1260 s->BasicModeStatus = 0x7809;
1261 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1262 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1263 s->BasicModeStatus |= 0x0004; /* link is up */
1264
1265 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1266 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1267 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1268
1269 /* also reset timer and disable timer interrupt */
1270 s->TCTR = 0;
1271 s->TimerInt = 0;
1272 s->TCTR_base = 0;
1273
1274 /* reset tally counters */
1275 RTL8139TallyCounters_clear(&s->tally_counters);
1276}
1277
b1d8e52e 1278static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1279{
1280 counters->TxOk = 0;
1281 counters->RxOk = 0;
1282 counters->TxERR = 0;
1283 counters->RxERR = 0;
1284 counters->MissPkt = 0;
1285 counters->FAE = 0;
1286 counters->Tx1Col = 0;
1287 counters->TxMCol = 0;
1288 counters->RxOkPhy = 0;
1289 counters->RxOkBrd = 0;
1290 counters->RxOkMul = 0;
1291 counters->TxAbt = 0;
1292 counters->TxUndrn = 0;
1293}
1294
3ada003a 1295static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1296{
3ada003a 1297 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1298 uint16_t val16;
1299 uint32_t val32;
1300 uint64_t val64;
1301
1302 val64 = cpu_to_le64(tally_counters->TxOk);
3ada003a 1303 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1304
1305 val64 = cpu_to_le64(tally_counters->RxOk);
3ada003a 1306 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1307
1308 val64 = cpu_to_le64(tally_counters->TxERR);
3ada003a 1309 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1310
1311 val32 = cpu_to_le32(tally_counters->RxERR);
3ada003a 1312 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1313
1314 val16 = cpu_to_le16(tally_counters->MissPkt);
3ada003a 1315 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1316
1317 val16 = cpu_to_le16(tally_counters->FAE);
3ada003a 1318 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1319
1320 val32 = cpu_to_le32(tally_counters->Tx1Col);
3ada003a 1321 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1322
1323 val32 = cpu_to_le32(tally_counters->TxMCol);
3ada003a 1324 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1325
1326 val64 = cpu_to_le64(tally_counters->RxOkPhy);
3ada003a 1327 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1328
1329 val64 = cpu_to_le64(tally_counters->RxOkBrd);
3ada003a 1330 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1331
1332 val32 = cpu_to_le32(tally_counters->RxOkMul);
3ada003a 1333 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1334
1335 val16 = cpu_to_le16(tally_counters->TxAbt);
3ada003a 1336 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1337
1338 val16 = cpu_to_le16(tally_counters->TxUndrn);
3ada003a 1339 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1340}
1341
1342/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1343
1344static const VMStateDescription vmstate_tally_counters = {
1345 .name = "tally_counters",
1346 .version_id = 1,
1347 .minimum_version_id = 1,
1348 .minimum_version_id_old = 1,
1349 .fields = (VMStateField []) {
1350 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1351 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1352 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1353 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1354 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1355 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1356 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1357 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1358 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1359 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1360 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1361 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1362 VMSTATE_END_OF_LIST()
1363 }
1364};
a41b2ff2
PB		 1365
1366static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1367{
1368 val &= 0xff;
1369
7cdeb319 1370 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1371
1372 if (val & CmdReset)
1373 {
7cdeb319 1374 DPRINTF("ChipCmd reset\n");
7f23f812 1375 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1376 }
1377 if (val & CmdRxEnb)
1378 {
7cdeb319 1379 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1380
1381 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1382 }
1383 if (val & CmdTxEnb)
1384 {
7cdeb319 1385 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1386
1387 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1388 }
1389
ebabb67a 1390 /* mask unwritable bits */
a41b2ff2
PB		 1391 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1392
1393 /* Deassert reset pin before next read */
1394 val &= ~CmdReset;
1395
1396 s->bChipCmdState = val;
1397}
1398
1399static int rtl8139_RxBufferEmpty(RTL8139State *s)
1400{
1401 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1402
1403 if (unread != 0)
1404 {
7cdeb319 1405 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1406 return 0;
1407 }
1408
7cdeb319 1409 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1410
1411 return 1;
1412}
1413
1414static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1415{
1416 uint32_t ret = s->bChipCmdState;
1417
1418 if (rtl8139_RxBufferEmpty(s))
1419 ret |= RxBufEmpty;
1420
7cdeb319 1421 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1422
1423 return ret;
1424}
1425
1426static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1427{
1428 val &= 0xffff;
1429
7cdeb319 1430 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1431
2c3891ab
AL		 1432 s->cplus_enabled = 1;
1433
ebabb67a 1434 /* mask unwritable bits */
a41b2ff2
PB		 1435 val = SET_MASKED(val, 0xff84, s->CpCmd);
1436
1437 s->CpCmd = val;
1438}
1439
1440static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1441{
1442 uint32_t ret = s->CpCmd;
1443
7cdeb319 1444 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1445
1446 return ret;
1447}
1448
1449static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1450{
7cdeb319 1451 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1452}
1453
1454static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1455{
1456 uint32_t ret = 0;
1457
7cdeb319 1458 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1459
1460 return ret;
1461}
1462
ebabb67a 1463static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1464{
eb46c5ed 1465 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1466 {
1467 return 1;
1468 }
1469
7cdeb319 1470 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1471
1472 return 0;
1473}
1474
1475static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1476{
1477 val &= 0xffff;
1478
7cdeb319 1479 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1480
ebabb67a 1481 /* mask unwritable bits */
e3d7e843 1482 uint32_t mask = 0x4cff;
a41b2ff2 1483
ebabb67a 1484 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1485 {
1486 /* Speed setting and autonegotiation enable bits are read-only */
1487 mask |= 0x3000;
1488 /* Duplex mode setting is read-only */
1489 mask |= 0x0100;
1490 }
1491
1492 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1493
1494 s->BasicModeCtrl = val;
1495}
1496
1497static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1498{
1499 uint32_t ret = s->BasicModeCtrl;
1500
7cdeb319 1501 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1502
1503 return ret;
1504}
1505
1506static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1507{
1508 val &= 0xffff;
1509
7cdeb319 1510 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1511
ebabb67a 1512 /* mask unwritable bits */
a41b2ff2
PB		 1513 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1514
1515 s->BasicModeStatus = val;
1516}
1517
1518static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1519{
1520 uint32_t ret = s->BasicModeStatus;
1521
7cdeb319 1522 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1523
1524 return ret;
1525}
1526
1527static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1528{
1529 val &= 0xff;
1530
7cdeb319 1531 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1532
ebabb67a 1533 /* mask unwritable bits */
a41b2ff2
PB		 1534 val = SET_MASKED(val, 0x31, s->Cfg9346);
1535
1536 uint32_t opmode = val & 0xc0;
1537 uint32_t eeprom_val = val & 0xf;
1538
1539 if (opmode == 0x80) {
1540 /* eeprom access */
1541 int eecs = (eeprom_val & 0x08)?1:0;
1542 int eesk = (eeprom_val & 0x04)?1:0;
1543 int eedi = (eeprom_val & 0x02)?1:0;
1544 prom9346_set_wire(s, eecs, eesk, eedi);
1545 } else if (opmode == 0x40) {
1546 /* Reset. */
1547 val = 0;
7f23f812 1548 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1549 }
1550
1551 s->Cfg9346 = val;
1552}
1553
1554static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1555{
1556 uint32_t ret = s->Cfg9346;
1557
1558 uint32_t opmode = ret & 0xc0;
1559
1560 if (opmode == 0x80)
1561 {
1562 /* eeprom access */
1563 int eedo = prom9346_get_wire(s);
1564 if (eedo)
1565 {
1566 ret |= 0x01;
1567 }
1568 else
1569 {
1570 ret &= ~0x01;
1571 }
1572 }
1573
7cdeb319 1574 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1575
1576 return ret;
1577}
1578
1579static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1580{
1581 val &= 0xff;
1582
7cdeb319 1583 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1584
ebabb67a 1585 if (!rtl8139_config_writable(s)) {
a41b2ff2 1586 return;
ebabb67a 1587 }
a41b2ff2 1588
ebabb67a 1589 /* mask unwritable bits */
a41b2ff2
PB		 1590 val = SET_MASKED(val, 0xf8, s->Config0);
1591
1592 s->Config0 = val;
1593}
1594
1595static uint32_t rtl8139_Config0_read(RTL8139State *s)
1596{
1597 uint32_t ret = s->Config0;
1598
7cdeb319 1599 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1600
1601 return ret;
1602}
1603
1604static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1605{
1606 val &= 0xff;
1607
7cdeb319 1608 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1609
ebabb67a 1610 if (!rtl8139_config_writable(s)) {
a41b2ff2 1611 return;
ebabb67a 1612 }
a41b2ff2 1613
ebabb67a 1614 /* mask unwritable bits */
a41b2ff2
PB		 1615 val = SET_MASKED(val, 0xC, s->Config1);
1616
1617 s->Config1 = val;
1618}
1619
1620static uint32_t rtl8139_Config1_read(RTL8139State *s)
1621{
1622 uint32_t ret = s->Config1;
1623
7cdeb319 1624 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1625
1626 return ret;
1627}
1628
1629static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1630{
1631 val &= 0xff;
1632
7cdeb319 1633 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1634
ebabb67a 1635 if (!rtl8139_config_writable(s)) {
a41b2ff2 1636 return;
ebabb67a 1637 }
a41b2ff2 1638
ebabb67a 1639 /* mask unwritable bits */
a41b2ff2
PB		 1640 val = SET_MASKED(val, 0x8F, s->Config3);
1641
1642 s->Config3 = val;
1643}
1644
1645static uint32_t rtl8139_Config3_read(RTL8139State *s)
1646{
1647 uint32_t ret = s->Config3;
1648
7cdeb319 1649 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1650
1651 return ret;
1652}
1653
1654static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1655{
1656 val &= 0xff;
1657
7cdeb319 1658 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1659
ebabb67a 1660 if (!rtl8139_config_writable(s)) {
a41b2ff2 1661 return;
ebabb67a 1662 }
a41b2ff2 1663
ebabb67a 1664 /* mask unwritable bits */
a41b2ff2
PB		 1665 val = SET_MASKED(val, 0x0a, s->Config4);
1666
1667 s->Config4 = val;
1668}
1669
1670static uint32_t rtl8139_Config4_read(RTL8139State *s)
1671{
1672 uint32_t ret = s->Config4;
1673
7cdeb319 1674 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1675
1676 return ret;
1677}
1678
1679static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1680{
1681 val &= 0xff;
1682
7cdeb319 1683 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1684
ebabb67a 1685 /* mask unwritable bits */
a41b2ff2
PB		 1686 val = SET_MASKED(val, 0x80, s->Config5);
1687
1688 s->Config5 = val;
1689}
1690
1691static uint32_t rtl8139_Config5_read(RTL8139State *s)
1692{
1693 uint32_t ret = s->Config5;
1694
7cdeb319 1695 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1696
1697 return ret;
1698}
1699
1700static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1701{
1702 if (!rtl8139_transmitter_enabled(s))
1703 {
7cdeb319 1704 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1705 return;
1706 }
1707
7cdeb319 1708 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1709
1710 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1711
1712 s->TxConfig = val;
1713}
1714
1715static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1716{
7cdeb319 1717 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1718
1719 uint32_t tc = s->TxConfig;
1720 tc &= 0xFFFFFF00;
1721 tc |= (val & 0x000000FF);
1722 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1723}
1724
1725static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1726{
1727 uint32_t ret = s->TxConfig;
1728
7cdeb319 1729 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1730
1731 return ret;
1732}
1733
1734static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1735{
7cdeb319 1736 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1737
ebabb67a 1738 /* mask unwritable bits */
a41b2ff2
PB		 1739 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1740
1741 s->RxConfig = val;
1742
1743 /* reset buffer size and read/write pointers */
1744 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1745
7cdeb319 1746 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1747}
1748
1749static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1750{
1751 uint32_t ret = s->RxConfig;
1752
7cdeb319 1753 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1754
1755 return ret;
1756}
1757
bf6b87a8
BP		 1758static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1759 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1760{
bf6b87a8
BP		 1761 struct iovec *iov = NULL;
1762
718da2b9
FB		 1763 if (!size)
1764 {
7cdeb319 1765 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1766 return;
1767 }
1768
bf6b87a8
BP		 1769 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1770 iov = (struct iovec[3]) {
1771 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1772 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1773 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1774 .iov_len = size - ETHER_ADDR_LEN * 2 },
1775 };
1776 }
1777
718da2b9
FB		 1778 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1779 {
bf6b87a8
BP		 1780 size_t buf2_size;
1781 uint8_t *buf2;
1782
1783 if (iov) {
1784 buf2_size = iov_size(iov, 3);
7267c094 1785 buf2 = g_malloc(buf2_size);
bf6b87a8
BP		 1786 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1787 buf = buf2;
1788 }
1789
7cdeb319 1790 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1791 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1792
1793 if (iov) {
7267c094 1794 g_free(buf2);
bf6b87a8 1795 }
718da2b9
FB		 1796 }
1797 else
1798 {
bf6b87a8
BP		 1799 if (iov) {
1800 qemu_sendv_packet(&s->nic->nc, iov, 3);
1801 } else {
1802 qemu_send_packet(&s->nic->nc, buf, size);
1803 }
718da2b9
FB		 1804 }
1805}
1806
a41b2ff2
PB		 1807static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1808{
1809 if (!rtl8139_transmitter_enabled(s))
1810 {
7cdeb319
BP		 1811 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1812 "disabled\n", descriptor);
a41b2ff2
PB		 1813 return 0;
1814 }
1815
1816 if (s->TxStatus[descriptor] & TxHostOwns)
1817 {
7cdeb319
BP		 1818 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1819 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1820 return 0;
1821 }
1822
7cdeb319 1823 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1824
1825 int txsize = s->TxStatus[descriptor] & 0x1fff;
1826 uint8_t txbuffer[0x2000];
1827
7cdeb319
BP		 1828 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1829 txsize, s->TxAddr[descriptor]);
a41b2ff2 1830
3ada003a 1831 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1832
1833 /* Mark descriptor as transferred */
1834 s->TxStatus[descriptor] |= TxHostOwns;
1835 s->TxStatus[descriptor] |= TxStatOK;
1836
bf6b87a8 1837 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1838
7cdeb319
BP		 1839 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1840 descriptor);
a41b2ff2
PB		 1841
1842 /* update interrupt */
1843 s->IntrStatus |= TxOK;
1844 rtl8139_update_irq(s);
1845
1846 return 1;
1847}
1848
718da2b9
FB		 1849/* structures and macros for task offloading */
1850typedef struct ip_header
1851{
1852 uint8_t ip_ver_len; /* version and header length */
1853 uint8_t ip_tos; /* type of service */
1854 uint16_t ip_len; /* total length */
1855 uint16_t ip_id; /* identification */
1856 uint16_t ip_off; /* fragment offset field */
1857 uint8_t ip_ttl; /* time to live */
1858 uint8_t ip_p; /* protocol */
1859 uint16_t ip_sum; /* checksum */
1860 uint32_t ip_src,ip_dst; /* source and dest address */
1861} ip_header;
1862
1863#define IP_HEADER_VERSION_4 4
1864#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1865#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1866
1867typedef struct tcp_header
1868{
1869 uint16_t th_sport; /* source port */
1870 uint16_t th_dport; /* destination port */
1871 uint32_t th_seq; /* sequence number */
1872 uint32_t th_ack; /* acknowledgement number */
1873 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1874 uint16_t th_win; /* window */
1875 uint16_t th_sum; /* checksum */
1876 uint16_t th_urp; /* urgent pointer */
1877} tcp_header;
1878
1879typedef struct udp_header
1880{
1881 uint16_t uh_sport; /* source port */
1882 uint16_t uh_dport; /* destination port */
1883 uint16_t uh_ulen; /* udp length */
1884 uint16_t uh_sum; /* udp checksum */
1885} udp_header;
1886
1887typedef struct ip_pseudo_header
1888{
1889 uint32_t ip_src;
1890 uint32_t ip_dst;
1891 uint8_t zeros;
1892 uint8_t ip_proto;
1893 uint16_t ip_payload;
1894} ip_pseudo_header;
1895
1896#define IP_PROTO_TCP 6
1897#define IP_PROTO_UDP 17
1898
1899#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1900#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1901#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1902
1903#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1904
1905#define TCP_FLAG_FIN 0x01
1906#define TCP_FLAG_PUSH 0x08
1907
1908/* produces ones' complement sum of data */
1909static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1910{
1911 uint32_t result = 0;
1912
1913 for (; len > 1; data+=2, len-=2)
1914 {
1915 result += *(uint16_t*)data;
1916 }
1917
1918 /* add the remainder byte */
1919 if (len)
1920 {
1921 uint8_t odd[2] = {*data, 0};
1922 result += *(uint16_t*)odd;
1923 }
1924
1925 while (result>>16)
1926 result = (result & 0xffff) + (result >> 16);
1927
1928 return result;
1929}
1930
1931static uint16_t ip_checksum(void *data, size_t len)
1932{
1933 return ~ones_complement_sum((uint8_t*)data, len);
1934}
1935
a41b2ff2
PB		 1936static int rtl8139_cplus_transmit_one(RTL8139State *s)
1937{
1938 if (!rtl8139_transmitter_enabled(s))
1939 {
7cdeb319 1940 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1941 return 0;
1942 }
1943
1944 if (!rtl8139_cp_transmitter_enabled(s))
1945 {
7cdeb319 1946 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1947 return 0 ;
1948 }
1949
1950 int descriptor = s->currCPlusTxDesc;
1951
3ada003a 1952 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1953
1954 /* Normal priority ring */
1955 cplus_tx_ring_desc += 16 * descriptor;
1956
7cdeb319 1957 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1958 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1959 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1960
1961 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1962
3ada003a 1963 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1964 txdw0 = le32_to_cpu(val);
3ada003a 1965 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1966 txdw1 = le32_to_cpu(val);
3ada003a 1967 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1968 txbufLO = le32_to_cpu(val);
3ada003a 1969 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1970 txbufHI = le32_to_cpu(val);
1971
7cdeb319
BP		 1972 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1973 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1974
1975/* w0 ownership flag */
1976#define CP_TX_OWN (1<<31)
1977/* w0 end of ring flag */
1978#define CP_TX_EOR (1<<30)
1979/* first segment of received packet flag */
1980#define CP_TX_FS (1<<29)
1981/* last segment of received packet flag */
1982#define CP_TX_LS (1<<28)
1983/* large send packet flag */
1984#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1985/* large send MSS mask, bits 16...25 */
1986#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1987
a41b2ff2
PB		 1988/* IP checksum offload flag */
1989#define CP_TX_IPCS (1<<18)
1990/* UDP checksum offload flag */
1991#define CP_TX_UDPCS (1<<17)
1992/* TCP checksum offload flag */
1993#define CP_TX_TCPCS (1<<16)
1994
1995/* w0 bits 0...15 : buffer size */
1996#define CP_TX_BUFFER_SIZE (1<<16)
1997#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 1998/* w1 add tag flag */
1999#define CP_TX_TAGC (1<<17)
2000/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2001#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2002/* w2 low 32bit of Rx buffer ptr */
2003/* w3 high 32bit of Rx buffer ptr */
2004
2005/* set after transmission */
2006/* FIFO underrun flag */
2007#define CP_TX_STATUS_UNF (1<<25)
2008/* transmit error summary flag, valid if set any of three below */
2009#define CP_TX_STATUS_TES (1<<23)
2010/* out-of-window collision flag */
2011#define CP_TX_STATUS_OWC (1<<22)
2012/* link failure flag */
2013#define CP_TX_STATUS_LNKF (1<<21)
2014/* excessive collisions flag */
2015#define CP_TX_STATUS_EXC (1<<20)
2016
2017 if (!(txdw0 & CP_TX_OWN))
2018 {
7cdeb319 2019 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2020 return 0 ;
2021 }
2022
7cdeb319 2023 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2024
2025 if (txdw0 & CP_TX_FS)
2026 {
7cdeb319
BP		 2027 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2028 "descriptor\n", descriptor);
6cadb320
FB		 2029
2030 /* reset internal buffer offset */
2031 s->cplus_txbuffer_offset = 0;
2032 }
a41b2ff2
PB		 2033
2034 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 2035 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2036
6cadb320
FB		 2037 /* make sure we have enough space to assemble the packet */
2038 if (!s->cplus_txbuffer)
2039 {
2040 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2041 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2042 s->cplus_txbuffer_offset = 0;
718da2b9 2043
7cdeb319
BP		 2044 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2045 s->cplus_txbuffer_len);
6cadb320
FB		 2046 }
2047
cde31a0e 2048 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 2049 {
cde31a0e
JW		 2050 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2051 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2052 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2053 "length to %d\n", txsize);
6cadb320
FB		 2054 }
2055
2056 if (!s->cplus_txbuffer)
2057 {
2058 /* out of memory */
a41b2ff2 2059
7cdeb319
BP		 2060 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2061 s->cplus_txbuffer_len);
6cadb320
FB		 2062
2063 /* update tally counter */
2064 ++s->tally_counters.TxERR;
2065 ++s->tally_counters.TxAbt;
2066
2067 return 0;
2068 }
2069
2070 /* append more data to the packet */
2071
7cdeb319 2072 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2073 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2074 s->cplus_txbuffer_offset);
6cadb320 2075
3ada003a
EGM		 2076 pci_dma_read(&s->dev, tx_addr,
2077 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2078 s->cplus_txbuffer_offset += txsize;
2079
2080 /* seek to next Rx descriptor */
2081 if (txdw0 & CP_TX_EOR)
2082 {
2083 s->currCPlusTxDesc = 0;
2084 }
2085 else
2086 {
2087 ++s->currCPlusTxDesc;
2088 if (s->currCPlusTxDesc >= 64)
2089 s->currCPlusTxDesc = 0;
2090 }
a41b2ff2
PB		 2091
2092 /* transfer ownership to target */
2093 txdw0 &= ~CP_RX_OWN;
2094
2095 /* reset error indicator bits */
2096 txdw0 &= ~CP_TX_STATUS_UNF;
2097 txdw0 &= ~CP_TX_STATUS_TES;
2098 txdw0 &= ~CP_TX_STATUS_OWC;
2099 txdw0 &= ~CP_TX_STATUS_LNKF;
2100 txdw0 &= ~CP_TX_STATUS_EXC;
2101
2102 /* update ring data */
2103 val = cpu_to_le32(txdw0);
3ada003a 2104 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2105
6cadb320
FB		 2106 /* Now decide if descriptor being processed is holding the last segment of packet */
2107 if (txdw0 & CP_TX_LS)
a41b2ff2 2108 {
bf6b87a8
BP		 2109 uint8_t dot1q_buffer_space[VLAN_HLEN];
2110 uint16_t *dot1q_buffer;
2111
7cdeb319
BP		 2112 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2113 descriptor);
6cadb320
FB		 2114
2115 /* can transfer fully assembled packet */
2116
2117 uint8_t *saved_buffer = s->cplus_txbuffer;
2118 int saved_size = s->cplus_txbuffer_offset;
2119 int saved_buffer_len = s->cplus_txbuffer_len;
2120
bf6b87a8
BP		 2121 /* create vlan tag */
2122 if (txdw1 & CP_TX_TAGC) {
2123 /* the vlan tag is in BE byte order in the descriptor
2124 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2125 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2126 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2127
2128 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2129 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2130 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2131 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2132 } else {
2133 dot1q_buffer = NULL;
2134 }
2135
6cadb320
FB		 2136 /* reset the card space to protect from recursive call */
2137 s->cplus_txbuffer = NULL;
2138 s->cplus_txbuffer_offset = 0;
2139 s->cplus_txbuffer_len = 0;
2140
718da2b9 2141 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2142 {
7cdeb319 2143 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2144
6cadb320 2145 /* ip packet header */
660f11be 2146 ip_header *ip = NULL;
6cadb320 2147 int hlen = 0;
718da2b9
FB		 2148 uint8_t ip_protocol = 0;
2149 uint16_t ip_data_len = 0;
6cadb320 2150
660f11be 2151 uint8_t *eth_payload_data = NULL;
718da2b9 2152 size_t eth_payload_len = 0;
6cadb320 2153
718da2b9 2154 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2155 if (proto == ETH_P_IP)
2156 {
7cdeb319 2157 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2158
2159 /* not aligned */
718da2b9
FB		 2160 eth_payload_data = saved_buffer + ETH_HLEN;
2161 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2162
718da2b9 2163 ip = (ip_header*)eth_payload_data;
6cadb320 2164
718da2b9 2165 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2166 DPRINTF("+++ C+ mode packet has bad IP version %d "
2167 "expected %d\n", IP_HEADER_VERSION(ip),
2168 IP_HEADER_VERSION_4);
6cadb320
FB		 2169 ip = NULL;
2170 } else {
718da2b9
FB		 2171 hlen = IP_HEADER_LENGTH(ip);
2172 ip_protocol = ip->ip_p;
2173 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2174 }
2175 }
2176
2177 if (ip)
2178 {
2179 if (txdw0 & CP_TX_IPCS)
2180 {
7cdeb319 2181 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2182
718da2b9 2183 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2184 /* bad packet header len */
2185 /* or packet too short */
2186 }
2187 else
2188 {
2189 ip->ip_sum = 0;
718da2b9 2190 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2191 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2192 hlen, ip->ip_sum);
6cadb320
FB		 2193 }
2194 }
2195
718da2b9 2196 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2197 {
718da2b9 2198 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2199
7cdeb319
BP		 2200 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2201 "frame data %d specified MSS=%d\n", ETH_MTU,
2202 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2203
718da2b9
FB		 2204 int tcp_send_offset = 0;
2205 int send_count = 0;
6cadb320
FB		 2206
2207 /* maximum IP header length is 60 bytes */
2208 uint8_t saved_ip_header[60];
6cadb320 2209
718da2b9
FB		 2210 /* save IP header template; data area is used in tcp checksum calculation */
2211 memcpy(saved_ip_header, eth_payload_data, hlen);
2212
2213 /* a placeholder for checksum calculation routine in tcp case */
2214 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2215 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2216
2217 /* pointer to TCP header */
2218 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2219
2220 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2221
2222 /* ETH_MTU = ip header len + tcp header len + payload */
2223 int tcp_data_len = ip_data_len - tcp_hlen;
2224 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2225
7cdeb319
BP		 2226 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2227 "data len %d TCP chunk size %d\n", ip_data_len,
2228 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2229
2230 /* note the cycle below overwrites IP header data,
2231 but restores it from saved_ip_header before sending packet */
2232
2233 int is_last_frame = 0;
2234
2235 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2236 {
2237 uint16_t chunk_size = tcp_chunk_size;
2238
2239 /* check if this is the last frame */
2240 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2241 {
2242 is_last_frame = 1;
2243 chunk_size = tcp_data_len - tcp_send_offset;
2244 }
2245
7cdeb319
BP		 2246 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2247 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2248
2249 /* add 4 TCP pseudoheader fields */
2250 /* copy IP source and destination fields */
2251 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2252
7cdeb319
BP		 2253 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2254 "packet with %d bytes data\n", tcp_hlen +
2255 chunk_size);
718da2b9
FB		 2256
2257 if (tcp_send_offset)
2258 {
2259 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2260 }
2261
2262 /* keep PUSH and FIN flags only for the last frame */
2263 if (!is_last_frame)
2264 {
2265 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2266 }
6cadb320 2267
718da2b9
FB		 2268 /* recalculate TCP checksum */
2269 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2270 p_tcpip_hdr->zeros = 0;
2271 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2272 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2273
2274 p_tcp_hdr->th_sum = 0;
2275
2276 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2277 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2278 tcp_checksum);
718da2b9
FB		 2279
2280 p_tcp_hdr->th_sum = tcp_checksum;
2281
2282 /* restore IP header */
2283 memcpy(eth_payload_data, saved_ip_header, hlen);
2284
2285 /* set IP data length and recalculate IP checksum */
2286 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2287
2288 /* increment IP id for subsequent frames */
2289 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2290
2291 ip->ip_sum = 0;
2292 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2293 DPRINTF("+++ C+ mode TSO IP header len=%d "
2294 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2295
2296 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2297 DPRINTF("+++ C+ mode TSO transferring packet size "
2298 "%d\n", tso_send_size);
bf6b87a8
BP		 2299 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2300 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2301
2302 /* add transferred count to TCP sequence number */
2303 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2304 ++send_count;
2305 }
2306
2307 /* Stop sending this frame */
2308 saved_size = 0;
2309 }
2310 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2311 {
7cdeb319 2312 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2313
2314 /* maximum IP header length is 60 bytes */
2315 uint8_t saved_ip_header[60];
2316 memcpy(saved_ip_header, eth_payload_data, hlen);
2317
2318 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2319 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2320
2321 /* add 4 TCP pseudoheader fields */
2322 /* copy IP source and destination fields */
718da2b9 2323 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2324
718da2b9 2325 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2326 {
7cdeb319
BP		 2327 DPRINTF("+++ C+ mode calculating TCP checksum for "
2328 "packet with %d bytes data\n", ip_data_len);
6cadb320 2329
718da2b9
FB		 2330 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2331 p_tcpip_hdr->zeros = 0;
2332 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2333 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2334
718da2b9 2335 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2336
2337 p_tcp_hdr->th_sum = 0;
2338
718da2b9 2339 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2340 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2341 tcp_checksum);
6cadb320
FB		 2342
2343 p_tcp_hdr->th_sum = tcp_checksum;
2344 }
718da2b9 2345 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2346 {
7cdeb319
BP		 2347 DPRINTF("+++ C+ mode calculating UDP checksum for "
2348 "packet with %d bytes data\n", ip_data_len);
6cadb320 2349
718da2b9
FB		 2350 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2351 p_udpip_hdr->zeros = 0;
2352 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2353 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2354
718da2b9 2355 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2356
6cadb320
FB		 2357 p_udp_hdr->uh_sum = 0;
2358
718da2b9 2359 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2360 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2361 udp_checksum);
6cadb320 2362
6cadb320
FB		 2363 p_udp_hdr->uh_sum = udp_checksum;
2364 }
2365
2366 /* restore IP header */
718da2b9 2367 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2368 }
2369 }
2370 }
2371
2372 /* update tally counter */
2373 ++s->tally_counters.TxOk;
2374
7cdeb319 2375 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2376
bf6b87a8
BP		 2377 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2378 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2379
2380 /* restore card space if there was no recursion and reset offset */
2381 if (!s->cplus_txbuffer)
2382 {
2383 s->cplus_txbuffer = saved_buffer;
2384 s->cplus_txbuffer_len = saved_buffer_len;
2385 s->cplus_txbuffer_offset = 0;
2386 }
2387 else
2388 {
7267c094 2389 g_free(saved_buffer);
6cadb320 2390 }
a41b2ff2
PB		 2391 }
2392 else
2393 {
7cdeb319 2394 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2395 }
2396
a41b2ff2
PB		 2397 return 1;
2398}
2399
2400static void rtl8139_cplus_transmit(RTL8139State *s)
2401{
2402 int txcount = 0;
2403
2404 while (rtl8139_cplus_transmit_one(s))
2405 {
2406 ++txcount;
2407 }
2408
2409 /* Mark transfer completed */
2410 if (!txcount)
2411 {
7cdeb319
BP		 2412 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2413 s->currCPlusTxDesc);
a41b2ff2
PB		 2414 }
2415 else
2416 {
2417 /* update interrupt status */
2418 s->IntrStatus |= TxOK;
2419 rtl8139_update_irq(s);
2420 }
2421}
2422
2423static void rtl8139_transmit(RTL8139State *s)
2424{
2425 int descriptor = s->currTxDesc, txcount = 0;
2426
2427 /*while*/
2428 if (rtl8139_transmit_one(s, descriptor))
2429 {
2430 ++s->currTxDesc;
2431 s->currTxDesc %= 4;
2432 ++txcount;
2433 }
2434
2435 /* Mark transfer completed */
2436 if (!txcount)
2437 {
7cdeb319
BP		 2438 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2439 s->currTxDesc);
a41b2ff2
PB		 2440 }
2441}
2442
2443static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2444{
2445
2446 int descriptor = txRegOffset/4;
6cadb320
FB		 2447
2448 /* handle C+ transmit mode register configuration */
2449
2c3891ab 2450 if (s->cplus_enabled)
6cadb320 2451 {
7cdeb319
BP		 2452 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2453 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2454
2455 /* handle Dump Tally Counters command */
2456 s->TxStatus[descriptor] = val;
2457
2458 if (descriptor == 0 && (val & 0x8))
2459 {
c227f099 2460 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2461
2462 /* dump tally counters to specified memory location */
3ada003a 2463 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2464
2465 /* mark dump completed */
2466 s->TxStatus[0] &= ~0x8;
2467 }
2468
2469 return;
2470 }
2471
7cdeb319
BP		 2472 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2473 txRegOffset, val, descriptor);
a41b2ff2
PB		 2474
2475 /* mask only reserved bits */
2476 val &= ~0xff00c000; /* these bits are reset on write */
2477 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2478
2479 s->TxStatus[descriptor] = val;
2480
2481 /* attempt to start transmission */
2482 rtl8139_transmit(s);
2483}
2484
3e48dd4a
SH		 2485static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2486 uint32_t base, uint8_t addr,
2487 int size)
a41b2ff2 2488{
3e48dd4a 2489 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2490 uint32_t offset = addr & 0x3;
2491 uint32_t ret = 0;
2492
2493 if (addr & (size - 1)) {
3e48dd4a
SH		 2494 DPRINTF("not implemented read for TxStatus/TxAddr "
2495 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2496 return ret;
2497 }
a41b2ff2 2498
afe0a595
JW		 2499 switch (size) {
2500 case 1: /* fall through */
2501 case 2: /* fall through */
2502 case 4:
3e48dd4a
SH		 2503 ret = (regs[reg] >> offset * 8) & ((1 << (size * 8)) - 1);
2504 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2505 reg, addr, size, ret);
afe0a595
JW		 2506 break;
2507 default:
3e48dd4a 2508 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2509 break;
2510 }
a41b2ff2
PB		 2511
2512 return ret;
2513}
2514
2515static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2516{
2517 uint16_t ret = 0;
2518
2519 /* Simulate TSAD, it is read only anyway */
2520
2521 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2522 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2523 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2524 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2525
2526 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2527 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2528 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2529 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2530
a41b2ff2
PB		 2531 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2532 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2533 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2534 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2535
a41b2ff2
PB		 2536 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2537 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2538 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2539 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2540
a41b2ff2 2541
7cdeb319 2542 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2543
2544 return ret;
2545}
2546
2547static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2548{
2549 uint16_t ret = s->CSCR;
2550
7cdeb319 2551 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2552
2553 return ret;
2554}
2555
2556static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2557{
7cdeb319 2558 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2559
290a0933 2560 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2561}
2562
2563static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2564{
290a0933 2565 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2566
7cdeb319 2567 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2568
2569 return ret;
2570}
2571
2572static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2573{
7cdeb319 2574 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2575
2576 /* this value is off by 16 */
2577 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2578
7cdeb319
BP		 2579 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2580 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2581}
2582
2583static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2584{
2585 /* this value is off by 16 */
2586 uint32_t ret = s->RxBufPtr - 0x10;
2587
7cdeb319 2588 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2589
2590 return ret;
2591}
2592
2593static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2594{
2595 /* this value is NOT off by 16 */
2596 uint32_t ret = s->RxBufAddr;
2597
7cdeb319 2598 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2599
2600 return ret;
2601}
2602
2603static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2604{
7cdeb319 2605 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2606
2607 s->RxBuf = val;
2608
2609 /* may need to reset rxring here */
2610}
2611
2612static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2613{
2614 uint32_t ret = s->RxBuf;
2615
7cdeb319 2616 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2617
2618 return ret;
2619}
2620
2621static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2622{
7cdeb319 2623 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2624
ebabb67a 2625 /* mask unwritable bits */
a41b2ff2
PB		 2626 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2627
2628 s->IntrMask = val;
2629
74475455 2630 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2631 rtl8139_update_irq(s);
05447803 2632
a41b2ff2
PB		 2633}
2634
2635static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2636{
2637 uint32_t ret = s->IntrMask;
2638
7cdeb319 2639 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2640
2641 return ret;
2642}
2643
2644static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2645{
7cdeb319 2646 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2647
2648#if 0
2649
2650 /* writing to ISR has no effect */
2651
2652 return;
2653
2654#else
2655 uint16_t newStatus = s->IntrStatus & ~val;
2656
ebabb67a 2657 /* mask unwritable bits */
a41b2ff2
PB		 2658 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2659
2660 /* writing 1 to interrupt status register bit clears it */
2661 s->IntrStatus = 0;
2662 rtl8139_update_irq(s);
2663
2664 s->IntrStatus = newStatus;
05447803
FZ		 2665 /*
2666 * Computing if we miss an interrupt here is not that correct but
2667 * considered that we should have had already an interrupt
2668 * and probably emulated is slower is better to assume this resetting was
26404edc 2669 * done before testing on previous rtl8139_update_irq lead to IRQ losing
05447803 2670 */
74475455 2671 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2672 rtl8139_update_irq(s);
05447803 2673
a41b2ff2
PB		 2674#endif
2675}
2676
2677static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2678{
74475455 2679 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2680
a41b2ff2
PB		 2681 uint32_t ret = s->IntrStatus;
2682
7cdeb319 2683 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2684
2685#if 0
2686
2687 /* reading ISR clears all interrupts */
2688 s->IntrStatus = 0;
2689
2690 rtl8139_update_irq(s);
2691
2692#endif
2693
2694 return ret;
2695}
2696
2697static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2698{
7cdeb319 2699 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2700
ebabb67a 2701 /* mask unwritable bits */
a41b2ff2
PB		 2702 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2703
2704 s->MultiIntr = val;
2705}
2706
2707static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2708{
2709 uint32_t ret = s->MultiIntr;
2710
7cdeb319 2711 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2712
2713 return ret;
2714}
2715
2716static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2717{
2718 RTL8139State *s = opaque;
2719
a41b2ff2
PB		 2720 switch (addr)
2721 {
2722 case MAC0 ... MAC0+5:
2723 s->phys[addr - MAC0] = val;
2724 break;
2725 case MAC0+6 ... MAC0+7:
2726 /* reserved */
2727 break;
2728 case MAR0 ... MAR0+7:
2729 s->mult[addr - MAR0] = val;
2730 break;
2731 case ChipCmd:
2732 rtl8139_ChipCmd_write(s, val);
2733 break;
2734 case Cfg9346:
2735 rtl8139_Cfg9346_write(s, val);
2736 break;
2737 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2738 rtl8139_TxConfig_writeb(s, val);
2739 break;
2740 case Config0:
2741 rtl8139_Config0_write(s, val);
2742 break;
2743 case Config1:
2744 rtl8139_Config1_write(s, val);
2745 break;
2746 case Config3:
2747 rtl8139_Config3_write(s, val);
2748 break;
2749 case Config4:
2750 rtl8139_Config4_write(s, val);
2751 break;
2752 case Config5:
2753 rtl8139_Config5_write(s, val);
2754 break;
2755 case MediaStatus:
2756 /* ignore */
7cdeb319
BP		 2757 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2758 val);
a41b2ff2
PB		 2759 break;
2760
2761 case HltClk:
7cdeb319 2762 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2763 if (val == 'R')
2764 {
2765 s->clock_enabled = 1;
2766 }
2767 else if (val == 'H')
2768 {
2769 s->clock_enabled = 0;
2770 }
2771 break;
2772
2773 case TxThresh:
7cdeb319 2774 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2775 s->TxThresh = val;
2776 break;
2777
2778 case TxPoll:
7cdeb319 2779 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2780 if (val & (1 << 7))
2781 {
7cdeb319
BP		 2782 DPRINTF("C+ TxPoll high priority transmission (not "
2783 "implemented)\n");
a41b2ff2
PB		 2784 //rtl8139_cplus_transmit(s);
2785 }
2786 if (val & (1 << 6))
2787 {
7cdeb319 2788 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2789 rtl8139_cplus_transmit(s);
2790 }
2791
2792 break;
2793
2794 default:
7cdeb319
BP		 2795 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2796 val);
a41b2ff2
PB		 2797 break;
2798 }
2799}
2800
2801static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2802{
2803 RTL8139State *s = opaque;
2804
a41b2ff2
PB		 2805 switch (addr)
2806 {
2807 case IntrMask:
2808 rtl8139_IntrMask_write(s, val);
2809 break;
2810
2811 case IntrStatus:
2812 rtl8139_IntrStatus_write(s, val);
2813 break;
2814
2815 case MultiIntr:
2816 rtl8139_MultiIntr_write(s, val);
2817 break;
2818
2819 case RxBufPtr:
2820 rtl8139_RxBufPtr_write(s, val);
2821 break;
2822
2823 case BasicModeCtrl:
2824 rtl8139_BasicModeCtrl_write(s, val);
2825 break;
2826 case BasicModeStatus:
2827 rtl8139_BasicModeStatus_write(s, val);
2828 break;
2829 case NWayAdvert:
7cdeb319 2830 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2831 s->NWayAdvert = val;
2832 break;
2833 case NWayLPAR:
7cdeb319 2834 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2835 break;
2836 case NWayExpansion:
7cdeb319 2837 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2838 s->NWayExpansion = val;
2839 break;
2840
2841 case CpCmd:
2842 rtl8139_CpCmd_write(s, val);
2843 break;
2844
6cadb320
FB		 2845 case IntrMitigate:
2846 rtl8139_IntrMitigate_write(s, val);
2847 break;
2848
a41b2ff2 2849 default:
7cdeb319
BP		 2850 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2851 addr, val);
a41b2ff2 2852
a41b2ff2
PB		 2853 rtl8139_io_writeb(opaque, addr, val & 0xff);
2854 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2855 break;
2856 }
2857}
2858
05447803
FZ		 2859static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2860{
2861 int64_t pci_time, next_time;
2862 uint32_t low_pci;
2863
7cdeb319 2864 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2865
2866 if (s->TimerExpire && current_time >= s->TimerExpire) {
2867 s->IntrStatus |= PCSTimeout;
2868 rtl8139_update_irq(s);
2869 }
2870
2871 /* Set QEMU timer only if needed that is
2872 * - TimerInt <> 0 (we have a timer)
2873 * - mask = 1 (we want an interrupt timer)
2874 * - irq = 0 (irq is not already active)
2875 * If any of above change we need to compute timer again
2876 * Also we must check if timer is passed without QEMU timer
2877 */
2878 s->TimerExpire = 0;
2879 if (!s->TimerInt) {
2880 return;
2881 }
2882
2883 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2884 get_ticks_per_sec());
2885 low_pci = pci_time & 0xffffffff;
2886 pci_time = pci_time - low_pci + s->TimerInt;
2887 if (low_pci >= s->TimerInt) {
2888 pci_time += 0x100000000LL;
2889 }
2890 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2891 PCI_FREQUENCY);
2892 s->TimerExpire = next_time;
2893
2894 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2895 qemu_mod_timer(s->timer, next_time);
2896 }
2897}
2898
a41b2ff2
PB		 2899static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2900{
2901 RTL8139State *s = opaque;
2902
a41b2ff2
PB		 2903 switch (addr)
2904 {
2905 case RxMissed:
7cdeb319 2906 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2907 s->RxMissed = 0;
2908 break;
2909
2910 case TxConfig:
2911 rtl8139_TxConfig_write(s, val);
2912 break;
2913
2914 case RxConfig:
2915 rtl8139_RxConfig_write(s, val);
2916 break;
2917
2918 case TxStatus0 ... TxStatus0+4*4-1:
2919 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2920 break;
2921
2922 case TxAddr0 ... TxAddr0+4*4-1:
2923 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2924 break;
2925
2926 case RxBuf:
2927 rtl8139_RxBuf_write(s, val);
2928 break;
2929
2930 case RxRingAddrLO:
7cdeb319 2931 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2932 s->RxRingAddrLO = val;
2933 break;
2934
2935 case RxRingAddrHI:
7cdeb319 2936 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2937 s->RxRingAddrHI = val;
2938 break;
2939
6cadb320 2940 case Timer:
7cdeb319 2941 DPRINTF("TCTR Timer reset on write\n");
74475455 2942 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2943 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2944 break;
2945
2946 case FlashReg:
7cdeb319 2947 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2948 if (s->TimerInt != val) {
2949 s->TimerInt = val;
74475455 2950 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2951 }
6cadb320
FB		 2952 break;
2953
a41b2ff2 2954 default:
7cdeb319
BP		 2955 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2956 addr, val);
a41b2ff2
PB		 2957 rtl8139_io_writeb(opaque, addr, val & 0xff);
2958 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2959 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2960 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2961 break;
2962 }
2963}
2964
2965static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2966{
2967 RTL8139State *s = opaque;
2968 int ret;
2969
a41b2ff2
PB		 2970 switch (addr)
2971 {
2972 case MAC0 ... MAC0+5:
2973 ret = s->phys[addr - MAC0];
2974 break;
2975 case MAC0+6 ... MAC0+7:
2976 ret = 0;
2977 break;
2978 case MAR0 ... MAR0+7:
2979 ret = s->mult[addr - MAR0];
2980 break;
afe0a595 2981 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2982 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2983 addr, 1);
afe0a595 2984 break;
a41b2ff2
PB		 2985 case ChipCmd:
2986 ret = rtl8139_ChipCmd_read(s);
2987 break;
2988 case Cfg9346:
2989 ret = rtl8139_Cfg9346_read(s);
2990 break;
2991 case Config0:
2992 ret = rtl8139_Config0_read(s);
2993 break;
2994 case Config1:
2995 ret = rtl8139_Config1_read(s);
2996 break;
2997 case Config3:
2998 ret = rtl8139_Config3_read(s);
2999 break;
3000 case Config4:
3001 ret = rtl8139_Config4_read(s);
3002 break;
3003 case Config5:
3004 ret = rtl8139_Config5_read(s);
3005 break;
3006
3007 case MediaStatus:
3008 ret = 0xd0;
7cdeb319 3009 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3010 break;
3011
3012 case HltClk:
3013 ret = s->clock_enabled;
7cdeb319 3014 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3015 break;
3016
3017 case PCIRevisionID:
6cadb320 3018 ret = RTL8139_PCI_REVID;
7cdeb319 3019 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3020 break;
3021
3022 case TxThresh:
3023 ret = s->TxThresh;
7cdeb319 3024 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3025 break;
3026
3027 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3028 ret = s->TxConfig >> 24;
7cdeb319 3029 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3030 break;
3031
3032 default:
7cdeb319 3033 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3034 ret = 0;
3035 break;
3036 }
3037
3038 return ret;
3039}
3040
3041static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3042{
3043 RTL8139State *s = opaque;
3044 uint32_t ret;
3045
a41b2ff2
PB		 3046 switch (addr)
3047 {
afe0a595 3048 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 3049 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 3050 break;
a41b2ff2
PB		 3051 case IntrMask:
3052 ret = rtl8139_IntrMask_read(s);
3053 break;
3054
3055 case IntrStatus:
3056 ret = rtl8139_IntrStatus_read(s);
3057 break;
3058
3059 case MultiIntr:
3060 ret = rtl8139_MultiIntr_read(s);
3061 break;
3062
3063 case RxBufPtr:
3064 ret = rtl8139_RxBufPtr_read(s);
3065 break;
3066
6cadb320
FB		 3067 case RxBufAddr:
3068 ret = rtl8139_RxBufAddr_read(s);
3069 break;
3070
a41b2ff2
PB		 3071 case BasicModeCtrl:
3072 ret = rtl8139_BasicModeCtrl_read(s);
3073 break;
3074 case BasicModeStatus:
3075 ret = rtl8139_BasicModeStatus_read(s);
3076 break;
3077 case NWayAdvert:
3078 ret = s->NWayAdvert;
7cdeb319 3079 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3080 break;
3081 case NWayLPAR:
3082 ret = s->NWayLPAR;
7cdeb319 3083 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3084 break;
3085 case NWayExpansion:
3086 ret = s->NWayExpansion;
7cdeb319 3087 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3088 break;
3089
3090 case CpCmd:
3091 ret = rtl8139_CpCmd_read(s);
3092 break;
3093
6cadb320
FB		 3094 case IntrMitigate:
3095 ret = rtl8139_IntrMitigate_read(s);
3096 break;
3097
a41b2ff2
PB		 3098 case TxSummary:
3099 ret = rtl8139_TSAD_read(s);
3100 break;
3101
3102 case CSCR:
3103 ret = rtl8139_CSCR_read(s);
3104 break;
3105
3106 default:
7cdeb319 3107 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3108
a41b2ff2
PB		 3109 ret = rtl8139_io_readb(opaque, addr);
3110 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3111
7cdeb319 3112 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3113 break;
3114 }
3115
3116 return ret;
3117}
3118
3119static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3120{
3121 RTL8139State *s = opaque;
3122 uint32_t ret;
3123
a41b2ff2
PB		 3124 switch (addr)
3125 {
3126 case RxMissed:
3127 ret = s->RxMissed;
3128
7cdeb319 3129 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3130 break;
3131
3132 case TxConfig:
3133 ret = rtl8139_TxConfig_read(s);
3134 break;
3135
3136 case RxConfig:
3137 ret = rtl8139_RxConfig_read(s);
3138 break;
3139
3140 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3141 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3142 addr, 4);
a41b2ff2
PB		 3143 break;
3144
3145 case TxAddr0 ... TxAddr0+4*4-1:
3146 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3147 break;
3148
3149 case RxBuf:
3150 ret = rtl8139_RxBuf_read(s);
3151 break;
3152
3153 case RxRingAddrLO:
3154 ret = s->RxRingAddrLO;
7cdeb319 3155 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3156 break;
3157
3158 case RxRingAddrHI:
3159 ret = s->RxRingAddrHI;
7cdeb319 3160 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3161 break;
3162
3163 case Timer:
74475455 3164 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3165 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3166 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3167 break;
3168
3169 case FlashReg:
3170 ret = s->TimerInt;
7cdeb319 3171 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3172 break;
3173
3174 default:
7cdeb319 3175 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3176
a41b2ff2
PB		 3177 ret = rtl8139_io_readb(opaque, addr);
3178 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3179 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3180 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3181
7cdeb319 3182 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3183 break;
3184 }
3185
3186 return ret;
3187}
3188
3189/* */
3190
3191static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3192{
3193 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3194}
3195
3196static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3197{
3198 rtl8139_io_writew(opaque, addr & 0xFF, val);
3199}
3200
3201static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3202{
3203 rtl8139_io_writel(opaque, addr & 0xFF, val);
3204}
3205
3206static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3207{
3208 return rtl8139_io_readb(opaque, addr & 0xFF);
3209}
3210
3211static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3212{
3213 return rtl8139_io_readw(opaque, addr & 0xFF);
3214}
3215
3216static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3217{
3218 return rtl8139_io_readl(opaque, addr & 0xFF);
3219}
3220
3221/* */
3222
c227f099 3223static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3224{
3225 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3226}
3227
c227f099 3228static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3229{
3230 rtl8139_io_writew(opaque, addr & 0xFF, val);
3231}
3232
c227f099 3233static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3234{
3235 rtl8139_io_writel(opaque, addr & 0xFF, val);
3236}
3237
c227f099 3238static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3239{
3240 return rtl8139_io_readb(opaque, addr & 0xFF);
3241}
3242
c227f099 3243static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3244{
5fedc612 3245 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3246 return val;
a41b2ff2
PB		 3247}
3248
c227f099 3249static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3250{
5fedc612 3251 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3252 return val;
a41b2ff2
PB		 3253}
3254
060110c3 3255static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3256{
6597ebbb 3257 RTL8139State* s = opaque;
74475455 3258 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3259 if (version_id < 4) {
2c3891ab
AL		 3260 s->cplus_enabled = s->CpCmd != 0;
3261 }
3262
a41b2ff2
PB		 3263 return 0;
3264}
3265
c574ba5a
AW		 3266static bool rtl8139_hotplug_ready_needed(void *opaque)
3267{
3268 return qdev_machine_modified();
3269}
3270
3271static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3272 .name = "rtl8139/hotplug_ready",
3273 .version_id = 1,
3274 .minimum_version_id = 1,
3275 .minimum_version_id_old = 1,
3276 .fields = (VMStateField []) {
3277 VMSTATE_END_OF_LIST()
3278 }
3279};
3280
05447803
FZ		 3281static void rtl8139_pre_save(void *opaque)
3282{
3283 RTL8139State* s = opaque;
74475455 3284 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3285
3286 /* set IntrStatus correctly */
3287 rtl8139_set_next_tctr_time(s, current_time);
3288 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3289 get_ticks_per_sec());
bd80f3fc 3290 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3291}
3292
060110c3
JQ		 3293static const VMStateDescription vmstate_rtl8139 = {
3294 .name = "rtl8139",
3295 .version_id = 4,
3296 .minimum_version_id = 3,
3297 .minimum_version_id_old = 3,
3298 .post_load = rtl8139_post_load,
05447803 3299 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3300 .fields = (VMStateField []) {
3301 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3302 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3303 VMSTATE_BUFFER(mult, RTL8139State),
3304 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3305 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3306
3307 VMSTATE_UINT32(RxBuf, RTL8139State),
3308 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3309 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3310 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3311
3312 VMSTATE_UINT16(IntrStatus, RTL8139State),
3313 VMSTATE_UINT16(IntrMask, RTL8139State),
3314
3315 VMSTATE_UINT32(TxConfig, RTL8139State),
3316 VMSTATE_UINT32(RxConfig, RTL8139State),
3317 VMSTATE_UINT32(RxMissed, RTL8139State),
3318 VMSTATE_UINT16(CSCR, RTL8139State),
3319
3320 VMSTATE_UINT8(Cfg9346, RTL8139State),
3321 VMSTATE_UINT8(Config0, RTL8139State),
3322 VMSTATE_UINT8(Config1, RTL8139State),
3323 VMSTATE_UINT8(Config3, RTL8139State),
3324 VMSTATE_UINT8(Config4, RTL8139State),
3325 VMSTATE_UINT8(Config5, RTL8139State),
3326
3327 VMSTATE_UINT8(clock_enabled, RTL8139State),
3328 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3329
3330 VMSTATE_UINT16(MultiIntr, RTL8139State),
3331
3332 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3333 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3334 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3335 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3336 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3337
3338 VMSTATE_UINT16(CpCmd, RTL8139State),
3339 VMSTATE_UINT8(TxThresh, RTL8139State),
3340
3341 VMSTATE_UNUSED(4),
3342 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3343 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3344
3345 VMSTATE_UINT32(currTxDesc, RTL8139State),
3346 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3347 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3348 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3349 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3350
3351 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3352 VMSTATE_INT32(eeprom.mode, RTL8139State),
3353 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3354 VMSTATE_UINT8(eeprom.address, RTL8139State),
3355 VMSTATE_UINT16(eeprom.input, RTL8139State),
3356 VMSTATE_UINT16(eeprom.output, RTL8139State),
3357
3358 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3359 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3360 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3361 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3362
3363 VMSTATE_UINT32(TCTR, RTL8139State),
3364 VMSTATE_UINT32(TimerInt, RTL8139State),
3365 VMSTATE_INT64(TCTR_base, RTL8139State),
3366
3367 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3368 vmstate_tally_counters, RTL8139TallyCounters),
3369
3370 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3371 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3372 },
3373 .subsections = (VMStateSubsection []) {
3374 {
3375 .vmsd = &vmstate_rtl8139_hotplug_ready,
3376 .needed = rtl8139_hotplug_ready_needed,
3377 }, {
3378 /* empty */
3379 }
060110c3
JQ		 3380 }
3381};
3382
a41b2ff2
PB		 3383/***********************************************************/
3384/* PCI RTL8139 definitions */
3385
bd80f3fc
AK		 3386static const MemoryRegionPortio rtl8139_portio[] = {
3387 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3388 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3389 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3390 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3391 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3392 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3393 PORTIO_END_OF_LIST()
3394};
a41b2ff2 3395
bd80f3fc
AK		 3396static const MemoryRegionOps rtl8139_io_ops = {
3397 .old_portio = rtl8139_portio,
3398 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3399};
3400
bd80f3fc
AK		 3401static const MemoryRegionOps rtl8139_mmio_ops = {
3402 .old_mmio = {
3403 .read = {
3404 rtl8139_mmio_readb,
3405 rtl8139_mmio_readw,
3406 rtl8139_mmio_readl,
3407 },
3408 .write = {
3409 rtl8139_mmio_writeb,
3410 rtl8139_mmio_writew,
3411 rtl8139_mmio_writel,
3412 },
3413 },
3414 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3415};
3416
6cadb320
FB		 3417static void rtl8139_timer(void *opaque)
3418{
3419 RTL8139State *s = opaque;
3420
6cadb320
FB		 3421 if (!s->clock_enabled)
3422 {
7cdeb319 3423 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3424 return;
3425 }
3426
05447803
FZ		 3427 s->IntrStatus |= PCSTimeout;
3428 rtl8139_update_irq(s);
74475455 3429 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3430}
6cadb320 3431
1673ad51 3432static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3433{
1673ad51 3434 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3435
1673ad51 3436 s->nic = NULL;
254111ec
GH		 3437}
3438
3439static int pci_rtl8139_uninit(PCIDevice *dev)
3440{
3441 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3442
bd80f3fc
AK		 3443 memory_region_destroy(&s->bar_io);
3444 memory_region_destroy(&s->bar_mem);
b946a153 3445 if (s->cplus_txbuffer) {
7267c094 3446 g_free(s->cplus_txbuffer);
b946a153
AL		 3447 s->cplus_txbuffer = NULL;
3448 }
b946a153
AL		 3449 qemu_del_timer(s->timer);
3450 qemu_free_timer(s->timer);
1673ad51 3451 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3452 return 0;
3453}
3454
1673ad51
MM		 3455static NetClientInfo net_rtl8139_info = {
3456 .type = NET_CLIENT_TYPE_NIC,
3457 .size = sizeof(NICState),
3458 .can_receive = rtl8139_can_receive,
3459 .receive = rtl8139_receive,
3460 .cleanup = rtl8139_cleanup,
3461};
3462
81a322d4 3463static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3464{
efd6dd45 3465 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3466 uint8_t *pci_conf;
3b46e624 3467
efd6dd45 3468 pci_conf = s->dev.config;
817e0b6f 3469 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3470 /* TODO: start of capability list, but no capability
3471 * list bit in status register, and offset 0xdc seems unused. */
3472 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3473
bd80f3fc
AK		 3474 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3475 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
e824b2cc
AK		 3476 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3477 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3478
254111ec 3479 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3480
7165448a
WD		 3481 /* prepare eeprom */
3482 s->eeprom.contents[0] = 0x8129;
3483#if 1
3484 /* PCI vendor and device ID should be mirrored here */
3485 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3486 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3487#endif
3488 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3489 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3490 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3491
1673ad51 3492 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
f79f2bfc 3493 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
1673ad51 3494 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3495
3496 s->cplus_txbuffer = NULL;
3497 s->cplus_txbuffer_len = 0;
3498 s->cplus_txbuffer_offset = 0;
3b46e624 3499
05447803 3500 s->TimerExpire = 0;
74475455
PB		 3501 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3502 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3503
3504 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3505
81a322d4 3506 return 0;
a41b2ff2 3507}
9d07d757 3508
40021f08
AL		 3509static Property rtl8139_properties[] = {
3510 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3511 DEFINE_PROP_END_OF_LIST(),
3512};
3513
3514static void rtl8139_class_init(ObjectClass *klass, void *data)
3515{
39bffca2 3516 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3517 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3518
3519 k->init = pci_rtl8139_init;
3520 k->exit = pci_rtl8139_uninit;
3521 k->romfile = "pxe-rtl8139.rom";
3522 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3523 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3524 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3525 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3526 dc->reset = rtl8139_reset;
3527 dc->vmsd = &vmstate_rtl8139;
3528 dc->props = rtl8139_properties;
40021f08
AL		 3529}
3530
39bffca2
AL		 3531static TypeInfo rtl8139_info = {
3532 .name = "rtl8139",
3533 .parent = TYPE_PCI_DEVICE,
3534 .instance_size = sizeof(RTL8139State),
3535 .class_init = rtl8139_class_init,
0aab0d3a
GH		 3536};
3537
83f7d43a 3538static void rtl8139_register_types(void)
9d07d757 3539{
39bffca2 3540 type_register_static(&rtl8139_info);
9d07d757
PB		 3541}
3542
83f7d43a 3543type_init(rtl8139_register_types)
Empty description
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