[qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysemu.h"
#include "sysbus.h"
#include "trace.h"

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

typedef struct MiscState {
    SysBusDevice busdev;
    qemu_irq irq;
    qemu_irq fdc_tc;
    uint32_t dummy;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint8_t sysctrl;
    uint16_t leds;
} MiscState;

typedef struct APCState {
    SysBusDevice busdev;
    qemu_irq cpu_halt;
} APCState;

#define MISC_SIZE 1
#define SYSCTRL_SIZE 4

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        trace_slavio_misc_update_irq_raise();
        qemu_irq_raise(s->irq);
    } else {
        trace_slavio_misc_update_irq_lower();
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(DeviceState *d)
{
    MiscState *s = container_of(d, MiscState, busdev.qdev);

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
{
    MiscState *s = opaque;

    trace_slavio_set_power_fail(power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_cfg_mem_writeb(val & 0xff);
    s->config = val & 0xff;
    slavio_misc_update_irq(s);
}

static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->config;
    trace_slavio_cfg_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
    slavio_cfg_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
    slavio_cfg_mem_writeb,
    NULL,
    NULL,
};

static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_diag_mem_writeb(val & 0xff);
    s->diag = val & 0xff;
}

static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->diag;
    trace_slavio_diag_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
    slavio_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
    slavio_diag_mem_writeb,
    NULL,
    NULL,
};

static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_mdm_mem_writeb(val & 0xff);
    s->mctrl = val & 0xff;
}

static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->mctrl;
    trace_slavio_mdm_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
    slavio_mdm_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
    slavio_mdm_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_aux1_mem_writeb(val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    trace_slavio_aux1_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    trace_slavio_aux2_mem_writeb(val & 0xff);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    trace_slavio_aux2_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    APCState *s = opaque;

    trace_apc_mem_writeb(val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    uint32_t ret = 0;

    trace_apc_mem_readb(ret);
    return ret;
}

static CPUReadMemoryFunc * const apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    trace_slavio_sysctrl_mem_readl(ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_sysctrl_mem_writel(val);
    switch (addr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    trace_slavio_led_mem_readw(ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    trace_slavio_led_mem_readw(val & 0xffff);
    switch (addr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static const VMStateDescription vmstate_misc = {
    .name ="slavio_misc",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(dummy, MiscState),
        VMSTATE_UINT8(config, MiscState),
        VMSTATE_UINT8(aux1, MiscState),
        VMSTATE_UINT8(aux2, MiscState),
        VMSTATE_UINT8(diag, MiscState),
        VMSTATE_UINT8(mctrl, MiscState),
        VMSTATE_UINT8(sysctrl, MiscState),
        VMSTATE_END_OF_LIST()
    }
};

static int apc_init1(SysBusDevice *dev)
{
    APCState *s = FROM_SYSBUS(APCState, dev);
    int io;

    sysbus_init_irq(dev, &s->cpu_halt);

    /* Power management (APC) XXX: not a Slavio device */
    io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);
    return 0;
}

static int slavio_misc_init1(SysBusDevice *dev)
{
    MiscState *s = FROM_SYSBUS(MiscState, dev);
    int io;

    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fdc_tc);

    /* 8 bit registers */
    /* Slavio control */
    io = cpu_register_io_memory(slavio_cfg_mem_read,
                                slavio_cfg_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Diagnostics */
    io = cpu_register_io_memory(slavio_diag_mem_read,
                                slavio_diag_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Modem control */
    io = cpu_register_io_memory(slavio_mdm_mem_read,
                                slavio_mdm_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 16 bit registers */
    /* ss600mp diag LEDs */
    io = cpu_register_io_memory(slavio_led_mem_read,
                                slavio_led_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 32 bit registers */
    /* System control */
    io = cpu_register_io_memory(slavio_sysctrl_mem_read,
                                slavio_sysctrl_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, SYSCTRL_SIZE, io);

    /* AUX 1 (Misc System Functions) */
    io = cpu_register_io_memory(slavio_aux1_mem_read,
                                slavio_aux1_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* AUX 2 (Software Powerdown Control) */
    io = cpu_register_io_memory(slavio_aux2_mem_read,
                                slavio_aux2_mem_write, s,
                                DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);

    return 0;
}

static SysBusDeviceInfo slavio_misc_info = {
    .init = slavio_misc_init1,
    .qdev.name  = "slavio_misc",
    .qdev.size  = sizeof(MiscState),
    .qdev.vmsd  = &vmstate_misc,
    .qdev.reset  = slavio_misc_reset,
};

static SysBusDeviceInfo apc_info = {
    .init = apc_init1,
    .qdev.name  = "apc",
    .qdev.size  = sizeof(MiscState),
};

static void slavio_misc_register_devices(void)
{
    sysbus_register_withprop(&slavio_misc_info);
    sysbus_register_withprop(&apc_info);
}

device_init(slavio_misc_register_devices)
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
2582cfa0	24
87ecb68b	25	#include "sysemu.h"
2582cfa0	26	#include "sysbus.h"
97bf4851	27	#include "trace.h"
3475187d FB	28
	29	/*
	30	* This is the auxio port, chip control and system control part of
	31	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	32	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	33	*
	34	* This also includes the PMC CPU idle controller.
	35	*/
	36
3475187d	37	typedef struct MiscState {
2582cfa0	38	SysBusDevice busdev;
d537cf6c	39	qemu_irq irq;
97bbb109	40	qemu_irq fdc_tc;
d37adb09	41	uint32_t dummy;
3475187d FB	42	uint8_t config;
3475187d FB	43	uint8_t aux1, aux2;
bfa30a38	44	uint8_t diag, mctrl;
d37adb09	45	uint8_t sysctrl;
6a3b9cc9	46	uint16_t leds;
3475187d FB	47	} MiscState;
3475187d FB	48
2582cfa0 BS	49	typedef struct APCState {
	50	SysBusDevice busdev;
	51	qemu_irq cpu_halt;
	52	} APCState;
	53
5aca8c3b	54	#define MISC_SIZE 1
a8f48dcc	55	#define SYSCTRL_SIZE 4
3475187d	56
2be17ebd BS	57	#define AUX1_TC 0x02
2be17ebd BS	58
7debeb82 BS	59	#define AUX2_PWROFF 0x01
	60	#define AUX2_PWRINTCLR 0x02
	61	#define AUX2_PWRFAIL 0x20
	62
	63	#define CFG_PWRINTEN 0x08
	64
	65	#define SYS_RESET 0x01
	66	#define SYS_RESETSTAT 0x02
	67
3475187d FB	68	static void slavio_misc_update_irq(void *opaque)
	69	{
	70	MiscState *s = opaque;
	71
7debeb82	72	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
97bf4851	73	trace_slavio_misc_update_irq_raise();
d537cf6c	74	qemu_irq_raise(s->irq);
3475187d	75	} else {
97bf4851	76	trace_slavio_misc_update_irq_lower();
d537cf6c	77	qemu_irq_lower(s->irq);
3475187d FB	78	}
	79	}
	80
1795057a	81	static void slavio_misc_reset(DeviceState *d)
3475187d	82	{
1795057a	83	MiscState *s = container_of(d, MiscState, busdev.qdev);
3475187d	84
4e3b1ea1	85	// Diagnostic and system control registers not cleared in reset
3475187d FB	86	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	87	}
	88
b2b6f6ec	89	static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
3475187d FB	90	{
	91	MiscState *s = opaque;
	92
97bf4851	93	trace_slavio_set_power_fail(power_failing, s->config);
7debeb82 BS	94	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	95	s->aux2 \|= AUX2_PWRFAIL;
3475187d	96	} else {
7debeb82	97	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	98	}
	99	slavio_misc_update_irq(s);
	100	}
	101
c227f099	102	static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
a8f48dcc BS	103	uint32_t val)
	104	{
	105	MiscState *s = opaque;
	106
97bf4851	107	trace_slavio_cfg_mem_writeb(val & 0xff);
a8f48dcc BS	108	s->config = val & 0xff;
	109	slavio_misc_update_irq(s);
	110	}
	111
c227f099	112	static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
a8f48dcc BS	113	{
	114	MiscState *s = opaque;
	115	uint32_t ret = 0;
	116
	117	ret = s->config;
97bf4851	118	trace_slavio_cfg_mem_readb(ret);
a8f48dcc BS	119	return ret;
	120	}
	121
d60efc6b	122	static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
a8f48dcc BS	123	slavio_cfg_mem_readb,
	124	NULL,
	125	NULL,
	126	};
	127
d60efc6b	128	static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
a8f48dcc BS	129	slavio_cfg_mem_writeb,
	130	NULL,
	131	NULL,
	132	};
	133
c227f099	134	static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38	135	uint32_t val)
3475187d FB	136	{
	137	MiscState *s = opaque;
	138
97bf4851	139	trace_slavio_diag_mem_writeb(val & 0xff);
a8f48dcc	140	s->diag = val & 0xff;
3475187d FB	141	}
3475187d FB	142
c227f099	143	static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
3475187d FB	144	{
	145	MiscState *s = opaque;
	146	uint32_t ret = 0;
	147
a8f48dcc	148	ret = s->diag;
97bf4851	149	trace_slavio_diag_mem_readb(ret);
a8f48dcc BS	150	return ret;
	151	}
	152
d60efc6b	153	static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
a8f48dcc BS	154	slavio_diag_mem_readb,
	155	NULL,
	156	NULL,
	157	};
	158
d60efc6b	159	static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
a8f48dcc BS	160	slavio_diag_mem_writeb,
	161	NULL,
	162	NULL,
	163	};
	164
c227f099	165	static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
a8f48dcc BS	166	uint32_t val)
	167	{
	168	MiscState *s = opaque;
	169
97bf4851	170	trace_slavio_mdm_mem_writeb(val & 0xff);
a8f48dcc BS	171	s->mctrl = val & 0xff;
	172	}
	173
c227f099	174	static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
a8f48dcc BS	175	{
	176	MiscState *s = opaque;
	177	uint32_t ret = 0;
	178
	179	ret = s->mctrl;
97bf4851	180	trace_slavio_mdm_mem_readb(ret);
3475187d FB	181	return ret;
	182	}
	183
d60efc6b	184	static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
a8f48dcc	185	slavio_mdm_mem_readb,
7c560456 BS	186	NULL,
7c560456 BS	187	NULL,
3475187d FB	188	};
3475187d FB	189
d60efc6b	190	static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
a8f48dcc	191	slavio_mdm_mem_writeb,
7c560456 BS	192	NULL,
7c560456 BS	193	NULL,
3475187d FB	194	};
3475187d FB	195
c227f099	196	static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
0019ad53 BS	197	uint32_t val)
	198	{
	199	MiscState *s = opaque;
	200
97bf4851	201	trace_slavio_aux1_mem_writeb(val & 0xff);
2be17ebd BS	202	if (val & AUX1_TC) {
	203	// Send a pulse to floppy terminal count line
	204	if (s->fdc_tc) {
	205	qemu_irq_raise(s->fdc_tc);
	206	qemu_irq_lower(s->fdc_tc);
	207	}
	208	val &= ~AUX1_TC;
	209	}
0019ad53 BS	210	s->aux1 = val & 0xff;
	211	}
	212
c227f099	213	static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
0019ad53 BS	214	{
	215	MiscState *s = opaque;
	216	uint32_t ret = 0;
	217
	218	ret = s->aux1;
97bf4851	219	trace_slavio_aux1_mem_readb(ret);
0019ad53 BS	220	return ret;
	221	}
	222
d60efc6b	223	static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
0019ad53 BS	224	slavio_aux1_mem_readb,
	225	NULL,
	226	NULL,
	227	};
	228
d60efc6b	229	static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
0019ad53 BS	230	slavio_aux1_mem_writeb,
	231	NULL,
	232	NULL,
	233	};
	234
c227f099	235	static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
0019ad53 BS	236	uint32_t val)
	237	{
	238	MiscState *s = opaque;
	239
	240	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
97bf4851	241	trace_slavio_aux2_mem_writeb(val & 0xff);
0019ad53 BS	242	val \|= s->aux2 & AUX2_PWRFAIL;
	243	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	244	val &= AUX2_PWROFF;
	245	s->aux2 = val;
	246	if (val & AUX2_PWROFF)
	247	qemu_system_shutdown_request();
	248	slavio_misc_update_irq(s);
	249	}
	250
c227f099	251	static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
0019ad53 BS	252	{
	253	MiscState *s = opaque;
	254	uint32_t ret = 0;
	255
	256	ret = s->aux2;
97bf4851	257	trace_slavio_aux2_mem_readb(ret);
0019ad53 BS	258	return ret;
	259	}
	260
d60efc6b	261	static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
0019ad53 BS	262	slavio_aux2_mem_readb,
	263	NULL,
	264	NULL,
	265	};
	266
d60efc6b	267	static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
0019ad53 BS	268	slavio_aux2_mem_writeb,
	269	NULL,
	270	NULL,
	271	};
	272
c227f099	273	static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
0019ad53	274	{
2582cfa0	275	APCState *s = opaque;
0019ad53	276
97bf4851	277	trace_apc_mem_writeb(val & 0xff);
6d0c293d	278	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	279	}
0019ad53 BS	280
c227f099	281	static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
0019ad53 BS	282	{
	283	uint32_t ret = 0;
	284
97bf4851	285	trace_apc_mem_readb(ret);
0019ad53 BS	286	return ret;
	287	}
	288
d60efc6b	289	static CPUReadMemoryFunc * const apc_mem_read[3] = {
0019ad53 BS	290	apc_mem_readb,
	291	NULL,
	292	NULL,
	293	};
	294
d60efc6b	295	static CPUWriteMemoryFunc * const apc_mem_write[3] = {
0019ad53 BS	296	apc_mem_writeb,
	297	NULL,
	298	NULL,
	299	};
	300
c227f099	301	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
bfa30a38 BS	302	{
bfa30a38 BS	303	MiscState *s = opaque;
a8f48dcc	304	uint32_t ret = 0;
bfa30a38	305
a8f48dcc	306	switch (addr) {
bfa30a38 BS	307	case 0:
	308	ret = s->sysctrl;
	309	break;
	310	default:
	311	break;
	312	}
97bf4851	313	trace_slavio_sysctrl_mem_readl(ret);
bfa30a38 BS	314	return ret;
	315	}
	316
c227f099	317	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
bfa30a38 BS	318	uint32_t val)
	319	{
	320	MiscState *s = opaque;
bfa30a38	321
97bf4851	322	trace_slavio_sysctrl_mem_writel(val);
a8f48dcc	323	switch (addr) {
bfa30a38	324	case 0:
7debeb82 BS	325	if (val & SYS_RESET) {
7debeb82 BS	326	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	327	qemu_system_reset_request();
	328	}
	329	break;
	330	default:
	331	break;
	332	}
	333	}
	334
d60efc6b	335	static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
7c560456 BS	336	NULL,
7c560456 BS	337	NULL,
bfa30a38 BS	338	slavio_sysctrl_mem_readl,
	339	};
	340
d60efc6b	341	static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
7c560456 BS	342	NULL,
7c560456 BS	343	NULL,
bfa30a38 BS	344	slavio_sysctrl_mem_writel,
	345	};
	346
c227f099	347	static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
6a3b9cc9 BS	348	{
6a3b9cc9 BS	349	MiscState *s = opaque;
a8f48dcc	350	uint32_t ret = 0;
6a3b9cc9	351
a8f48dcc	352	switch (addr) {
6a3b9cc9 BS	353	case 0:
	354	ret = s->leds;
	355	break;
	356	default:
	357	break;
	358	}
97bf4851	359	trace_slavio_led_mem_readw(ret);
6a3b9cc9 BS	360	return ret;
	361	}
	362
c227f099	363	static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
6a3b9cc9 BS	364	uint32_t val)
	365	{
	366	MiscState *s = opaque;
6a3b9cc9	367
97bf4851	368	trace_slavio_led_mem_readw(val & 0xffff);
a8f48dcc	369	switch (addr) {
6a3b9cc9	370	case 0:
d5296cb5	371	s->leds = val;
6a3b9cc9 BS	372	break;
	373	default:
	374	break;
	375	}
	376	}
	377
d60efc6b	378	static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
7c560456 BS	379	NULL,
	380	slavio_led_mem_readw,
	381	NULL,
6a3b9cc9 BS	382	};
6a3b9cc9 BS	383
d60efc6b	384	static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
7c560456 BS	385	NULL,
	386	slavio_led_mem_writew,
	387	NULL,
6a3b9cc9 BS	388	};
6a3b9cc9 BS	389
d37adb09 BS	390	static const VMStateDescription vmstate_misc = {
	391	.name ="slavio_misc",
	392	.version_id = 1,
	393	.minimum_version_id = 1,
	394	.minimum_version_id_old = 1,
	395	.fields = (VMStateField []) {
	396	VMSTATE_UINT32(dummy, MiscState),
	397	VMSTATE_UINT8(config, MiscState),
	398	VMSTATE_UINT8(aux1, MiscState),
	399	VMSTATE_UINT8(aux2, MiscState),
	400	VMSTATE_UINT8(diag, MiscState),
	401	VMSTATE_UINT8(mctrl, MiscState),
	402	VMSTATE_UINT8(sysctrl, MiscState),
	403	VMSTATE_END_OF_LIST()
	404	}
	405	};
3475187d	406
81a322d4	407	static int apc_init1(SysBusDevice *dev)
2582cfa0 BS	408	{
	409	APCState *s = FROM_SYSBUS(APCState, dev);
	410	int io;
3475187d	411
2582cfa0 BS	412	sysbus_init_irq(dev, &s->cpu_halt);
	413
	414	/* Power management (APC) XXX: not a Slavio device */
2507c12a AG	415	io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
2507c12a AG	416	DEVICE_NATIVE_ENDIAN);
2582cfa0	417	sysbus_init_mmio(dev, MISC_SIZE, io);
81a322d4	418	return 0;
2582cfa0 BS	419	}
2582cfa0 BS	420
81a322d4	421	static int slavio_misc_init1(SysBusDevice *dev)
2582cfa0 BS	422	{
	423	MiscState *s = FROM_SYSBUS(MiscState, dev);
	424	int io;
	425
	426	sysbus_init_irq(dev, &s->irq);
	427	sysbus_init_irq(dev, &s->fdc_tc);
	428
	429	/* 8 bit registers */
	430	/* Slavio control */
	431	io = cpu_register_io_memory(slavio_cfg_mem_read,
2507c12a AG	432	slavio_cfg_mem_write, s,
2507c12a AG	433	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	434	sysbus_init_mmio(dev, MISC_SIZE, io);
	435
	436	/* Diagnostics */
	437	io = cpu_register_io_memory(slavio_diag_mem_read,
2507c12a AG	438	slavio_diag_mem_write, s,
2507c12a AG	439	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	440	sysbus_init_mmio(dev, MISC_SIZE, io);
	441
	442	/* Modem control */
	443	io = cpu_register_io_memory(slavio_mdm_mem_read,
2507c12a AG	444	slavio_mdm_mem_write, s,
2507c12a AG	445	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	446	sysbus_init_mmio(dev, MISC_SIZE, io);
	447
	448	/* 16 bit registers */
	449	/* ss600mp diag LEDs */
	450	io = cpu_register_io_memory(slavio_led_mem_read,
2507c12a AG	451	slavio_led_mem_write, s,
2507c12a AG	452	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	453	sysbus_init_mmio(dev, MISC_SIZE, io);
	454
	455	/* 32 bit registers */
	456	/* System control */
	457	io = cpu_register_io_memory(slavio_sysctrl_mem_read,
2507c12a AG	458	slavio_sysctrl_mem_write, s,
2507c12a AG	459	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	460	sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
	461
	462	/* AUX 1 (Misc System Functions) */
	463	io = cpu_register_io_memory(slavio_aux1_mem_read,
2507c12a AG	464	slavio_aux1_mem_write, s,
2507c12a AG	465	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	466	sysbus_init_mmio(dev, MISC_SIZE, io);
	467
	468	/* AUX 2 (Software Powerdown Control) */
	469	io = cpu_register_io_memory(slavio_aux2_mem_read,
2507c12a AG	470	slavio_aux2_mem_write, s,
2507c12a AG	471	DEVICE_NATIVE_ENDIAN);
2582cfa0 BS	472	sysbus_init_mmio(dev, MISC_SIZE, io);
2582cfa0 BS	473
b2b6f6ec BS	474	qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
b2b6f6ec BS	475
81a322d4	476	return 0;
2582cfa0	477	}
0019ad53	478
2582cfa0 BS	479	static SysBusDeviceInfo slavio_misc_info = {
	480	.init = slavio_misc_init1,
	481	.qdev.name = "slavio_misc",
	482	.qdev.size = sizeof(MiscState),
1795057a BS	483	.qdev.vmsd = &vmstate_misc,
1795057a BS	484	.qdev.reset = slavio_misc_reset,
2582cfa0 BS	485	};
	486
	487	static SysBusDeviceInfo apc_info = {
	488	.init = apc_init1,
	489	.qdev.name = "apc",
	490	.qdev.size = sizeof(MiscState),
2582cfa0 BS	491	};
	492
	493	static void slavio_misc_register_devices(void)
	494	{
	495	sysbus_register_withprop(&slavio_misc_info);
	496	sysbus_register_withprop(&apc_info);
3475187d	497	}
2582cfa0 BS	498
2582cfa0 BS	499	device_init(slavio_misc_register_devices)