[qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "sysemu.h"
#include "sysbus.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, ...)                                  \
    do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
#else
#define MISC_DPRINTF(fmt, ...)
#endif

typedef struct MiscState {
    SysBusDevice busdev;
    qemu_irq irq;
    uint32_t dummy;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint8_t sysctrl;
    uint16_t leds;
    qemu_irq fdc_tc;
} MiscState;

typedef struct APCState {
    SysBusDevice busdev;
    qemu_irq cpu_halt;
} APCState;

#define MISC_SIZE 1
#define SYSCTRL_SIZE 4

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_cfg_mem_writeb(void *opaque, a_target_phys_addr addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
    s->config = val & 0xff;
    slavio_misc_update_irq(s);
}

static uint32_t slavio_cfg_mem_readb(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->config;
    MISC_DPRINTF("Read config %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
    slavio_cfg_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
    slavio_cfg_mem_writeb,
    NULL,
    NULL,
};

static void slavio_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
    s->diag = val & 0xff;
}

static uint32_t slavio_diag_mem_readb(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->diag;
    MISC_DPRINTF("Read diag %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
    slavio_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
    slavio_diag_mem_writeb,
    NULL,
    NULL,
};

static void slavio_mdm_mem_writeb(void *opaque, a_target_phys_addr addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
    s->mctrl = val & 0xff;
}

static uint32_t slavio_mdm_mem_readb(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->mctrl;
    MISC_DPRINTF("Read modem control %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
    slavio_mdm_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
    slavio_mdm_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, a_target_phys_addr addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    MISC_DPRINTF("Read aux1 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, a_target_phys_addr addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    MISC_DPRINTF("Write aux2 %2.2x\n", val);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    MISC_DPRINTF("Read aux2 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
{
    APCState *s = opaque;

    MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, a_target_phys_addr addr)
{
    uint32_t ret = 0;

    MISC_DPRINTF("Read power management %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc * const apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control %08x\n", ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, a_target_phys_addr addr,
                                      uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write system control %08x\n", val);
    switch (addr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, a_target_phys_addr addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, a_target_phys_addr addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
    switch (addr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static const VMStateDescription vmstate_misc = {
    .name ="slavio_misc",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(dummy, MiscState),
        VMSTATE_UINT8(config, MiscState),
        VMSTATE_UINT8(aux1, MiscState),
        VMSTATE_UINT8(aux2, MiscState),
        VMSTATE_UINT8(diag, MiscState),
        VMSTATE_UINT8(mctrl, MiscState),
        VMSTATE_UINT8(sysctrl, MiscState),
        VMSTATE_END_OF_LIST()
    }
};

static int apc_init1(SysBusDevice *dev)
{
    APCState *s = FROM_SYSBUS(APCState, dev);
    int io;

    sysbus_init_irq(dev, &s->cpu_halt);

    /* Power management (APC) XXX: not a Slavio device */
    io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);
    return 0;
}

static int slavio_misc_init1(SysBusDevice *dev)
{
    MiscState *s = FROM_SYSBUS(MiscState, dev);
    int io;

    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fdc_tc);

    /* 8 bit registers */
    /* Slavio control */
    io = cpu_register_io_memory(slavio_cfg_mem_read,
                                slavio_cfg_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Diagnostics */
    io = cpu_register_io_memory(slavio_diag_mem_read,
                                slavio_diag_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* Modem control */
    io = cpu_register_io_memory(slavio_mdm_mem_read,
                                slavio_mdm_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 16 bit registers */
    /* ss600mp diag LEDs */
    io = cpu_register_io_memory(slavio_led_mem_read,
                                slavio_led_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* 32 bit registers */
    /* System control */
    io = cpu_register_io_memory(slavio_sysctrl_mem_read,
                                slavio_sysctrl_mem_write, s);
    sysbus_init_mmio(dev, SYSCTRL_SIZE, io);

    /* AUX 1 (Misc System Functions) */
    io = cpu_register_io_memory(slavio_aux1_mem_read,
                                slavio_aux1_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    /* AUX 2 (Software Powerdown Control) */
    io = cpu_register_io_memory(slavio_aux2_mem_read,
                                slavio_aux2_mem_write, s);
    sysbus_init_mmio(dev, MISC_SIZE, io);

    qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);

    vmstate_register(-1, &vmstate_misc, s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);
    return 0;
}

static SysBusDeviceInfo slavio_misc_info = {
    .init = slavio_misc_init1,
    .qdev.name  = "slavio_misc",
    .qdev.size  = sizeof(MiscState),
};

static SysBusDeviceInfo apc_info = {
    .init = apc_init1,
    .qdev.name  = "apc",
    .qdev.size  = sizeof(MiscState),
};

static void slavio_misc_register_devices(void)
{
    sysbus_register_withprop(&slavio_misc_info);
    sysbus_register_withprop(&apc_info);
}

device_init(slavio_misc_register_devices)
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
2582cfa0	24
87ecb68b PB	25	#include "sun4m.h"
87ecb68b PB	26	#include "sysemu.h"
2582cfa0	27	#include "sysbus.h"
87ecb68b	28
3475187d FB	29	/* debug misc */
	30	//#define DEBUG_MISC
	31
	32	/*
	33	* This is the auxio port, chip control and system control part of
	34	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	35	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	36	*
	37	* This also includes the PMC CPU idle controller.
	38	*/
	39
	40	#ifdef DEBUG_MISC
001faf32 BS	41	#define MISC_DPRINTF(fmt, ...) \
001faf32 BS	42	do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
3475187d	43	#else
001faf32	44	#define MISC_DPRINTF(fmt, ...)
3475187d FB	45	#endif
	46
	47	typedef struct MiscState {
2582cfa0	48	SysBusDevice busdev;
d537cf6c	49	qemu_irq irq;
d37adb09	50	uint32_t dummy;
3475187d FB	51	uint8_t config;
3475187d FB	52	uint8_t aux1, aux2;
bfa30a38	53	uint8_t diag, mctrl;
d37adb09	54	uint8_t sysctrl;
6a3b9cc9	55	uint16_t leds;
2be17ebd	56	qemu_irq fdc_tc;
3475187d FB	57	} MiscState;
3475187d FB	58
2582cfa0 BS	59	typedef struct APCState {
	60	SysBusDevice busdev;
	61	qemu_irq cpu_halt;
	62	} APCState;
	63
5aca8c3b	64	#define MISC_SIZE 1
a8f48dcc	65	#define SYSCTRL_SIZE 4
3475187d	66
2be17ebd BS	67	#define AUX1_TC 0x02
2be17ebd BS	68
7debeb82 BS	69	#define AUX2_PWROFF 0x01
	70	#define AUX2_PWRINTCLR 0x02
	71	#define AUX2_PWRFAIL 0x20
	72
	73	#define CFG_PWRINTEN 0x08
	74
	75	#define SYS_RESET 0x01
	76	#define SYS_RESETSTAT 0x02
	77
3475187d FB	78	static void slavio_misc_update_irq(void *opaque)
	79	{
	80	MiscState *s = opaque;
	81
7debeb82	82	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	83	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	84	qemu_irq_raise(s->irq);
3475187d	85	} else {
d537cf6c PB	86	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	87	qemu_irq_lower(s->irq);
3475187d FB	88	}
	89	}
	90
	91	static void slavio_misc_reset(void *opaque)
	92	{
	93	MiscState *s = opaque;
	94
4e3b1ea1	95	// Diagnostic and system control registers not cleared in reset
3475187d FB	96	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	97	}
	98
b2b6f6ec	99	static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
3475187d FB	100	{
	101	MiscState *s = opaque;
	102
	103	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	104	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	105	s->aux2 \|= AUX2_PWRFAIL;
3475187d	106	} else {
7debeb82	107	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	108	}
	109	slavio_misc_update_irq(s);
	110	}
	111
99a0949b	112	static void slavio_cfg_mem_writeb(void *opaque, a_target_phys_addr addr,
a8f48dcc BS	113	uint32_t val)
	114	{
	115	MiscState *s = opaque;
	116
	117	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	118	s->config = val & 0xff;
	119	slavio_misc_update_irq(s);
	120	}
	121
99a0949b	122	static uint32_t slavio_cfg_mem_readb(void *opaque, a_target_phys_addr addr)
a8f48dcc BS	123	{
	124	MiscState *s = opaque;
	125	uint32_t ret = 0;
	126
	127	ret = s->config;
	128	MISC_DPRINTF("Read config %2.2x\n", ret);
	129	return ret;
	130	}
	131
d60efc6b	132	static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
a8f48dcc BS	133	slavio_cfg_mem_readb,
	134	NULL,
	135	NULL,
	136	};
	137
d60efc6b	138	static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
a8f48dcc BS	139	slavio_cfg_mem_writeb,
	140	NULL,
	141	NULL,
	142	};
	143
99a0949b	144	static void slavio_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
bfa30a38	145	uint32_t val)
3475187d FB	146	{
	147	MiscState *s = opaque;
	148
a8f48dcc BS	149	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
a8f48dcc BS	150	s->diag = val & 0xff;
3475187d FB	151	}
3475187d FB	152
99a0949b	153	static uint32_t slavio_diag_mem_readb(void *opaque, a_target_phys_addr addr)
3475187d FB	154	{
	155	MiscState *s = opaque;
	156	uint32_t ret = 0;
	157
a8f48dcc BS	158	ret = s->diag;
	159	MISC_DPRINTF("Read diag %2.2x\n", ret);
	160	return ret;
	161	}
	162
d60efc6b	163	static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
a8f48dcc BS	164	slavio_diag_mem_readb,
	165	NULL,
	166	NULL,
	167	};
	168
d60efc6b	169	static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
a8f48dcc BS	170	slavio_diag_mem_writeb,
	171	NULL,
	172	NULL,
	173	};
	174
99a0949b	175	static void slavio_mdm_mem_writeb(void *opaque, a_target_phys_addr addr,
a8f48dcc BS	176	uint32_t val)
	177	{
	178	MiscState *s = opaque;
	179
	180	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	181	s->mctrl = val & 0xff;
	182	}
	183
99a0949b	184	static uint32_t slavio_mdm_mem_readb(void *opaque, a_target_phys_addr addr)
a8f48dcc BS	185	{
	186	MiscState *s = opaque;
	187	uint32_t ret = 0;
	188
	189	ret = s->mctrl;
	190	MISC_DPRINTF("Read modem control %2.2x\n", ret);
3475187d FB	191	return ret;
	192	}
	193
d60efc6b	194	static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
a8f48dcc	195	slavio_mdm_mem_readb,
7c560456 BS	196	NULL,
7c560456 BS	197	NULL,
3475187d FB	198	};
3475187d FB	199
d60efc6b	200	static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
a8f48dcc	201	slavio_mdm_mem_writeb,
7c560456 BS	202	NULL,
7c560456 BS	203	NULL,
3475187d FB	204	};
3475187d FB	205
99a0949b	206	static void slavio_aux1_mem_writeb(void *opaque, a_target_phys_addr addr,
0019ad53 BS	207	uint32_t val)
	208	{
	209	MiscState *s = opaque;
	210
	211	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
2be17ebd BS	212	if (val & AUX1_TC) {
	213	// Send a pulse to floppy terminal count line
	214	if (s->fdc_tc) {
	215	qemu_irq_raise(s->fdc_tc);
	216	qemu_irq_lower(s->fdc_tc);
	217	}
	218	val &= ~AUX1_TC;
	219	}
0019ad53 BS	220	s->aux1 = val & 0xff;
	221	}
	222
99a0949b	223	static uint32_t slavio_aux1_mem_readb(void *opaque, a_target_phys_addr addr)
0019ad53 BS	224	{
	225	MiscState *s = opaque;
	226	uint32_t ret = 0;
	227
	228	ret = s->aux1;
	229	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	230
	231	return ret;
	232	}
	233
d60efc6b	234	static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
0019ad53 BS	235	slavio_aux1_mem_readb,
	236	NULL,
	237	NULL,
	238	};
	239
d60efc6b	240	static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
0019ad53 BS	241	slavio_aux1_mem_writeb,
	242	NULL,
	243	NULL,
	244	};
	245
99a0949b	246	static void slavio_aux2_mem_writeb(void *opaque, a_target_phys_addr addr,
0019ad53 BS	247	uint32_t val)
	248	{
	249	MiscState *s = opaque;
	250
	251	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
	252	MISC_DPRINTF("Write aux2 %2.2x\n", val);
	253	val \|= s->aux2 & AUX2_PWRFAIL;
	254	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	255	val &= AUX2_PWROFF;
	256	s->aux2 = val;
	257	if (val & AUX2_PWROFF)
	258	qemu_system_shutdown_request();
	259	slavio_misc_update_irq(s);
	260	}
	261
99a0949b	262	static uint32_t slavio_aux2_mem_readb(void *opaque, a_target_phys_addr addr)
0019ad53 BS	263	{
	264	MiscState *s = opaque;
	265	uint32_t ret = 0;
	266
	267	ret = s->aux2;
	268	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	269
	270	return ret;
	271	}
	272
d60efc6b	273	static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
0019ad53 BS	274	slavio_aux2_mem_readb,
	275	NULL,
	276	NULL,
	277	};
	278
d60efc6b	279	static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
0019ad53 BS	280	slavio_aux2_mem_writeb,
	281	NULL,
	282	NULL,
	283	};
	284
99a0949b	285	static void apc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
0019ad53	286	{
2582cfa0	287	APCState *s = opaque;
0019ad53 BS	288
0019ad53 BS	289	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
6d0c293d	290	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	291	}
0019ad53 BS	292
99a0949b	293	static uint32_t apc_mem_readb(void *opaque, a_target_phys_addr addr)
0019ad53 BS	294	{
	295	uint32_t ret = 0;
	296
	297	MISC_DPRINTF("Read power management %2.2x\n", ret);
	298	return ret;
	299	}
	300
d60efc6b	301	static CPUReadMemoryFunc * const apc_mem_read[3] = {
0019ad53 BS	302	apc_mem_readb,
	303	NULL,
	304	NULL,
	305	};
	306
d60efc6b	307	static CPUWriteMemoryFunc * const apc_mem_write[3] = {
0019ad53 BS	308	apc_mem_writeb,
	309	NULL,
	310	NULL,
	311	};
	312
99a0949b	313	static uint32_t slavio_sysctrl_mem_readl(void *opaque, a_target_phys_addr addr)
bfa30a38 BS	314	{
bfa30a38 BS	315	MiscState *s = opaque;
a8f48dcc	316	uint32_t ret = 0;
bfa30a38	317
a8f48dcc	318	switch (addr) {
bfa30a38 BS	319	case 0:
	320	ret = s->sysctrl;
	321	break;
	322	default:
	323	break;
	324	}
5626b017	325	MISC_DPRINTF("Read system control %08x\n", ret);
bfa30a38 BS	326	return ret;
	327	}
	328
99a0949b	329	static void slavio_sysctrl_mem_writel(void *opaque, a_target_phys_addr addr,
bfa30a38 BS	330	uint32_t val)
	331	{
	332	MiscState *s = opaque;
bfa30a38	333
5626b017	334	MISC_DPRINTF("Write system control %08x\n", val);
a8f48dcc	335	switch (addr) {
bfa30a38	336	case 0:
7debeb82 BS	337	if (val & SYS_RESET) {
7debeb82 BS	338	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	339	qemu_system_reset_request();
	340	}
	341	break;
	342	default:
	343	break;
	344	}
	345	}
	346
d60efc6b	347	static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
7c560456 BS	348	NULL,
7c560456 BS	349	NULL,
bfa30a38 BS	350	slavio_sysctrl_mem_readl,
	351	};
	352
d60efc6b	353	static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
7c560456 BS	354	NULL,
7c560456 BS	355	NULL,
bfa30a38 BS	356	slavio_sysctrl_mem_writel,
	357	};
	358
99a0949b	359	static uint32_t slavio_led_mem_readw(void *opaque, a_target_phys_addr addr)
6a3b9cc9 BS	360	{
6a3b9cc9 BS	361	MiscState *s = opaque;
a8f48dcc	362	uint32_t ret = 0;
6a3b9cc9	363
a8f48dcc	364	switch (addr) {
6a3b9cc9 BS	365	case 0:
	366	ret = s->leds;
	367	break;
	368	default:
	369	break;
	370	}
5626b017	371	MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
6a3b9cc9 BS	372	return ret;
	373	}
	374
99a0949b	375	static void slavio_led_mem_writew(void *opaque, a_target_phys_addr addr,
6a3b9cc9 BS	376	uint32_t val)
	377	{
	378	MiscState *s = opaque;
6a3b9cc9	379
5626b017	380	MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
a8f48dcc	381	switch (addr) {
6a3b9cc9	382	case 0:
d5296cb5	383	s->leds = val;
6a3b9cc9 BS	384	break;
	385	default:
	386	break;
	387	}
	388	}
	389
d60efc6b	390	static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
7c560456 BS	391	NULL,
	392	slavio_led_mem_readw,
	393	NULL,
6a3b9cc9 BS	394	};
6a3b9cc9 BS	395
d60efc6b	396	static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
7c560456 BS	397	NULL,
	398	slavio_led_mem_writew,
	399	NULL,
6a3b9cc9 BS	400	};
6a3b9cc9 BS	401
d37adb09 BS	402	static const VMStateDescription vmstate_misc = {
	403	.name ="slavio_misc",
	404	.version_id = 1,
	405	.minimum_version_id = 1,
	406	.minimum_version_id_old = 1,
	407	.fields = (VMStateField []) {
	408	VMSTATE_UINT32(dummy, MiscState),
	409	VMSTATE_UINT8(config, MiscState),
	410	VMSTATE_UINT8(aux1, MiscState),
	411	VMSTATE_UINT8(aux2, MiscState),
	412	VMSTATE_UINT8(diag, MiscState),
	413	VMSTATE_UINT8(mctrl, MiscState),
	414	VMSTATE_UINT8(sysctrl, MiscState),
	415	VMSTATE_END_OF_LIST()
	416	}
	417	};
3475187d	418
81a322d4	419	static int apc_init1(SysBusDevice *dev)
2582cfa0 BS	420	{
	421	APCState *s = FROM_SYSBUS(APCState, dev);
	422	int io;
3475187d	423
2582cfa0 BS	424	sysbus_init_irq(dev, &s->cpu_halt);
	425
	426	/* Power management (APC) XXX: not a Slavio device */
	427	io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
	428	sysbus_init_mmio(dev, MISC_SIZE, io);
81a322d4	429	return 0;
2582cfa0 BS	430	}
2582cfa0 BS	431
81a322d4	432	static int slavio_misc_init1(SysBusDevice *dev)
2582cfa0 BS	433	{
	434	MiscState *s = FROM_SYSBUS(MiscState, dev);
	435	int io;
	436
	437	sysbus_init_irq(dev, &s->irq);
	438	sysbus_init_irq(dev, &s->fdc_tc);
	439
	440	/* 8 bit registers */
	441	/* Slavio control */
	442	io = cpu_register_io_memory(slavio_cfg_mem_read,
	443	slavio_cfg_mem_write, s);
	444	sysbus_init_mmio(dev, MISC_SIZE, io);
	445
	446	/* Diagnostics */
	447	io = cpu_register_io_memory(slavio_diag_mem_read,
	448	slavio_diag_mem_write, s);
	449	sysbus_init_mmio(dev, MISC_SIZE, io);
	450
	451	/* Modem control */
	452	io = cpu_register_io_memory(slavio_mdm_mem_read,
	453	slavio_mdm_mem_write, s);
	454	sysbus_init_mmio(dev, MISC_SIZE, io);
	455
	456	/* 16 bit registers */
	457	/* ss600mp diag LEDs */
	458	io = cpu_register_io_memory(slavio_led_mem_read,
	459	slavio_led_mem_write, s);
	460	sysbus_init_mmio(dev, MISC_SIZE, io);
	461
	462	/* 32 bit registers */
	463	/* System control */
	464	io = cpu_register_io_memory(slavio_sysctrl_mem_read,
	465	slavio_sysctrl_mem_write, s);
	466	sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
	467
	468	/* AUX 1 (Misc System Functions) */
	469	io = cpu_register_io_memory(slavio_aux1_mem_read,
	470	slavio_aux1_mem_write, s);
	471	sysbus_init_mmio(dev, MISC_SIZE, io);
	472
	473	/* AUX 2 (Software Powerdown Control) */
	474	io = cpu_register_io_memory(slavio_aux2_mem_read,
	475	slavio_aux2_mem_write, s);
	476	sysbus_init_mmio(dev, MISC_SIZE, io);
	477
b2b6f6ec BS	478	qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
b2b6f6ec BS	479
d37adb09	480	vmstate_register(-1, &vmstate_misc, s);
a08d4367	481	qemu_register_reset(slavio_misc_reset, s);
3475187d	482	slavio_misc_reset(s);
81a322d4	483	return 0;
2582cfa0	484	}
0019ad53	485
2582cfa0 BS	486	static SysBusDeviceInfo slavio_misc_info = {
	487	.init = slavio_misc_init1,
	488	.qdev.name = "slavio_misc",
	489	.qdev.size = sizeof(MiscState),
2582cfa0 BS	490	};
	491
	492	static SysBusDeviceInfo apc_info = {
	493	.init = apc_init1,
	494	.qdev.name = "apc",
	495	.qdev.size = sizeof(MiscState),
2582cfa0 BS	496	};
	497
	498	static void slavio_misc_register_devices(void)
	499	{
	500	sysbus_register_withprop(&slavio_misc_info);
	501	sysbus_register_withprop(&apc_info);
3475187d	502	}
2582cfa0 BS	503
2582cfa0 BS	504	device_init(slavio_misc_register_devices)