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usb-musb: Take a DeviceState* in init function
[qemu.git] / hw / usb-musb.c
CommitLineData
942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "usb.h"
26#include "irq.h"
384dce1e 27#include "hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
618c169b
GH		 262static void musb_attach(USBPort *port);
263static void musb_detach(USBPort *port);
4706ab6c 264static void musb_child_detach(USBPort *port, USBDevice *child);
d47e59b8 265static void musb_schedule_cb(USBPort *port, USBPacket *p);
4706ab6c 266static void musb_async_cancel_device(MUSBState *s, USBDevice *dev);
942ac052 267
0d86d2be
GH		 268static USBPortOps musb_port_ops = {
269 .attach = musb_attach,
618c169b 270 .detach = musb_detach,
4706ab6c 271 .child_detach = musb_child_detach,
13a9a0d3 272 .complete = musb_schedule_cb,
0d86d2be
GH		 273};
274
07771f6f 275static USBBusOps musb_bus_ops = {
07771f6f
GH		 276};
277
5dc1672b
GH		 278typedef struct MUSBPacket MUSBPacket;
279typedef struct MUSBEndPoint MUSBEndPoint;
280
281struct MUSBPacket {
282 USBPacket p;
283 MUSBEndPoint *ep;
284 int dir;
285};
286
287struct MUSBEndPoint {
bc24a225
PB		 288 uint16_t faddr[2];
289 uint8_t haddr[2];
290 uint8_t hport[2];
291 uint16_t csr[2];
292 uint16_t maxp[2];
293 uint16_t rxcount;
294 uint8_t type[2];
295 uint8_t interval[2];
296 uint8_t config;
297 uint8_t fifosize;
298 int timeout[2]; /* Always in microframes */
299
384dce1e 300 uint8_t *buf[2];
bc24a225
PB		 301 int fifolen[2];
302 int fifostart[2];
303 int fifoaddr[2];
5dc1672b 304 MUSBPacket packey[2];
bc24a225
PB		 305 int status[2];
306 int ext_size[2];
307
308 /* For callbacks' use */
309 int epnum;
310 int interrupt[2];
311 MUSBState *musb;
312 USBCallback *delayed_cb[2];
313 QEMUTimer *intv_timer[2];
5dc1672b 314};
bc24a225
PB		 315
316struct MUSBState {
406c2075 317 qemu_irq irqs[musb_irq_max];
b2317837 318 USBBus bus;
942ac052
AZ		 319 USBPort port;
320
321 int idx;
322 uint8_t devctl;
323 uint8_t power;
324 uint8_t faddr;
325
326 uint8_t intr;
327 uint8_t mask;
328 uint16_t tx_intr;
329 uint16_t tx_mask;
330 uint16_t rx_intr;
331 uint16_t rx_mask;
332
333 int setup_len;
334 int session;
335
384dce1e 336 uint8_t buf[0x8000];
942ac052 337
942ac052
AZ		 338 /* Duplicating the world since 2008!... probably we should have 32
339 * logical, single endpoints instead. */
bc24a225 340 MUSBEndPoint ep[16];
5dc1672b
GH		 341};
342
406c2075 343struct MUSBState *musb_init(DeviceState *parent_device, int gpio_base)
942ac052 344{
7267c094 345 MUSBState *s = g_malloc0(sizeof(*s));
942ac052
AZ		 346 int i;
347
406c2075
PM		 348 for (i = 0; i < musb_irq_max; i++) {
349 s->irqs[i] = qdev_get_gpio_in(parent_device, gpio_base + i);
350 }
942ac052
AZ		 351
352 s->faddr = 0x00;
353 s->power = MGC_M_POWER_HSENAB;
354 s->tx_intr = 0x0000;
355 s->rx_intr = 0x0000;
356 s->tx_mask = 0xffff;
357 s->rx_mask = 0xffff;
358 s->intr = 0x00;
359 s->mask = 0x06;
360 s->idx = 0;
361
362 /* TODO: _DW */
363 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
364 for (i = 0; i < 16; i ++) {
365 s->ep[i].fifosize = 64;
366 s->ep[i].maxp[0] = 0x40;
367 s->ep[i].maxp[1] = 0x40;
368 s->ep[i].musb = s;
369 s->ep[i].epnum = i;
4f4321c1
GH		 370 usb_packet_init(&s->ep[i].packey[0].p);
371 usb_packet_init(&s->ep[i].packey[1].p);
942ac052
AZ		 372 }
373
406c2075 374 usb_bus_new(&s->bus, &musb_bus_ops, parent_device);
ace1318b 375 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
843d4e0c 376 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
942ac052
AZ		 377
378 return s;
379}
380
bc24a225 381static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 382{
383 if (level)
384 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
385 else
386 s->devctl &= ~MGC_M_DEVCTL_VBUS;
387
388 qemu_set_irq(s->irqs[musb_set_vbus], level);
389}
390
bc24a225 391static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 392{
393 if (!level) {
394 s->intr &= ~(1 << line);
395 qemu_irq_lower(s->irqs[line]);
396 } else if (s->mask & (1 << line)) {
397 s->intr |= 1 << line;
398 qemu_irq_raise(s->irqs[line]);
399 }
400}
401
bc24a225 402static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 403{
404 if (!level) {
405 s->tx_intr &= ~(1 << line);
406 if (!s->tx_intr)
407 qemu_irq_lower(s->irqs[musb_irq_tx]);
408 } else if (s->tx_mask & (1 << line)) {
409 s->tx_intr |= 1 << line;
410 qemu_irq_raise(s->irqs[musb_irq_tx]);
411 }
412}
413
bc24a225 414static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 415{
416 if (line) {
417 if (!level) {
418 s->rx_intr &= ~(1 << line);
419 if (!s->rx_intr)
420 qemu_irq_lower(s->irqs[musb_irq_rx]);
421 } else if (s->rx_mask & (1 << line)) {
422 s->rx_intr |= 1 << line;
423 qemu_irq_raise(s->irqs[musb_irq_rx]);
424 }
425 } else
426 musb_tx_intr_set(s, line, level);
427}
428
bc24a225 429uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 430{
431 return (s->rx_intr << 15) | s->tx_intr;
432}
433
bc24a225 434void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 435{
436 if (s->rx_intr) {
437 s->rx_intr &= mask >> 15;
438 if (!s->rx_intr)
439 qemu_irq_lower(s->irqs[musb_irq_rx]);
440 }
441
442 if (s->tx_intr) {
443 s->tx_intr &= mask & 0xffff;
444 if (!s->tx_intr)
445 qemu_irq_lower(s->irqs[musb_irq_tx]);
446 }
447}
448
bc24a225 449void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 450{
451 s->ep[epnum].ext_size[!is_tx] = size;
452 s->ep[epnum].fifostart[0] = 0;
453 s->ep[epnum].fifostart[1] = 0;
454 s->ep[epnum].fifolen[0] = 0;
455 s->ep[epnum].fifolen[1] = 0;
456}
457
bc24a225 458static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 459{
460 int detect_prev = prev_dev && prev_sess;
461 int detect = !!s->port.dev && s->session;
462
463 if (detect && !detect_prev) {
464 /* Let's skip the ID pin sense and VBUS sense formalities and
465 * and signal a successful SRP directly. This should work at least
466 * for the Linux driver stack. */
467 musb_intr_set(s, musb_irq_connect, 1);
468
469 if (s->port.dev->speed == USB_SPEED_LOW) {
470 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
471 s->devctl |= MGC_M_DEVCTL_LSDEV;
472 } else {
473 s->devctl |= MGC_M_DEVCTL_FSDEV;
474 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
475 }
476
477 /* A-mode? */
478 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
479
480 /* Host-mode bit? */
481 s->devctl |= MGC_M_DEVCTL_HM;
482#if 1
483 musb_vbus_set(s, 1);
484#endif
485 } else if (!detect && detect_prev) {
486#if 1
487 musb_vbus_set(s, 0);
488#endif
489 }
490}
491
492/* Attach or detach a device on our only port. */
618c169b 493static void musb_attach(USBPort *port)
942ac052 494{
bc24a225 495 MUSBState *s = (MUSBState *) port->opaque;
942ac052 496
618c169b
GH		 497 musb_intr_set(s, musb_irq_vbus_request, 1);
498 musb_session_update(s, 0, s->session);
499}
942ac052 500
618c169b
GH		 501static void musb_detach(USBPort *port)
502{
503 MUSBState *s = (MUSBState *) port->opaque;
942ac052 504
4706ab6c
HG		 505 musb_async_cancel_device(s, port->dev);
506
618c169b
GH		 507 musb_intr_set(s, musb_irq_disconnect, 1);
508 musb_session_update(s, 1, s->session);
942ac052
AZ		 509}
510
4706ab6c
HG		 511static void musb_child_detach(USBPort *port, USBDevice *child)
512{
513 MUSBState *s = (MUSBState *) port->opaque;
514
515 musb_async_cancel_device(s, child);
516}
517
b3e5759e 518static void musb_cb_tick0(void *opaque)
942ac052 519{
bc24a225 520 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 521
5dc1672b 522 ep->delayed_cb[0](&ep->packey[0].p, opaque);
942ac052
AZ		 523}
524
b3e5759e 525static void musb_cb_tick1(void *opaque)
942ac052 526{
bc24a225 527 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 528
5dc1672b 529 ep->delayed_cb[1](&ep->packey[1].p, opaque);
942ac052
AZ		 530}
531
532#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
533
d47e59b8 534static void musb_schedule_cb(USBPort *port, USBPacket *packey)
942ac052 535{
13a9a0d3
GH		 536 MUSBPacket *p = container_of(packey, MUSBPacket, p);
537 MUSBEndPoint *ep = p->ep;
538 int dir = p->dir;
942ac052
AZ		 539 int timeout = 0;
540
541 if (ep->status[dir] == USB_RET_NAK)
542 timeout = ep->timeout[dir];
543 else if (ep->interrupt[dir])
544 timeout = 8;
545 else
13a9a0d3 546 return musb_cb_tick(ep);
942ac052
AZ		 547
548 if (!ep->intv_timer[dir])
13a9a0d3 549 ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, ep);
942ac052 550
74475455 551 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
6ee093c9 552 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 553}
554
942ac052
AZ		 555static int musb_timeout(int ttype, int speed, int val)
556{
557#if 1
558 return val << 3;
559#endif
560
561 switch (ttype) {
562 case USB_ENDPOINT_XFER_CONTROL:
563 if (val < 2)
564 return 0;
565 else if (speed == USB_SPEED_HIGH)
566 return 1 << (val - 1);
567 else
568 return 8 << (val - 1);
569
570 case USB_ENDPOINT_XFER_INT:
571 if (speed == USB_SPEED_HIGH)
572 if (val < 2)
573 return 0;
574 else
575 return 1 << (val - 1);
576 else
577 return val << 3;
578
579 case USB_ENDPOINT_XFER_BULK:
580 case USB_ENDPOINT_XFER_ISOC:
581 if (val < 2)
582 return 0;
583 else if (speed == USB_SPEED_HIGH)
584 return 1 << (val - 1);
585 else
586 return 8 << (val - 1);
587 /* TODO: what with low-speed Bulk and Isochronous? */
588 }
589
2ac71179 590 hw_error("bad interval\n");
942ac052
AZ		 591}
592
b3e5759e 593static void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 594 int epnum, int pid, int len, USBCallback cb, int dir)
595{
596 int ret;
597 int idx = epnum && dir;
598 int ttype;
599
600 /* ep->type[0,1] contains:
601 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
602 * in bits 5:4 the transfer type (BULK / INT)
603 * in bits 3:0 the EP num
604 */
605 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
606
607 ep->timeout[dir] = musb_timeout(ttype,
608 ep->type[idx] >> 6, ep->interval[idx]);
609 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
610 ep->delayed_cb[dir] = cb;
942ac052 611
942ac052 612 /* A wild guess on the FADDR semantics... */
4f4321c1
GH		 613 usb_packet_setup(&ep->packey[dir].p, pid, ep->faddr[idx],
614 ep->type[idx] & 0xf);
615 usb_packet_addbuf(&ep->packey[dir].p, ep->buf[idx], len);
5dc1672b
GH		 616 ep->packey[dir].ep = ep;
617 ep->packey[dir].dir = dir;
942ac052
AZ		 618
619 if (s->port.dev)
53aa8c0e 620 ret = usb_handle_packet(s->port.dev, &ep->packey[dir].p);
942ac052
AZ		 621 else
622 ret = USB_RET_NODEV;
623
624 if (ret == USB_RET_ASYNC) {
625 ep->status[dir] = len;
626 return;
627 }
628
629 ep->status[dir] = ret;
d47e59b8 630 musb_schedule_cb(&s->port, &ep->packey[dir].p);
942ac052
AZ		 631}
632
633static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
634{
635 /* Unfortunately we can't use packey->devep because that's the remote
636 * endpoint number and may be different than our local. */
bc24a225 637 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 638 int epnum = ep->epnum;
bc24a225 639 MUSBState *s = ep->musb;
942ac052
AZ		 640
641 ep->fifostart[0] = 0;
642 ep->fifolen[0] = 0;
643#ifdef CLEAR_NAK
644 if (ep->status[0] != USB_RET_NAK) {
645#endif
646 if (epnum)
647 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
648 else
649 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
650#ifdef CLEAR_NAK
651 }
652#endif
653
654 /* Clear all of the error bits first */
655 if (epnum)
656 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
657 MGC_M_TXCSR_H_NAKTIMEOUT);
658 else
659 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
660 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
661
662 if (ep->status[0] == USB_RET_STALL) {
663 /* Command not supported by target! */
664 ep->status[0] = 0;
665
666 if (epnum)
667 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
668 else
669 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
670 }
671
672 if (ep->status[0] == USB_RET_NAK) {
673 ep->status[0] = 0;
674
675 /* NAK timeouts are only generated in Bulk transfers and
676 * Data-errors in Isochronous. */
677 if (ep->interrupt[0]) {
678 return;
679 }
680
681 if (epnum)
682 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
683 else
684 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
685 }
686
687 if (ep->status[0] < 0) {
688 if (ep->status[0] == USB_RET_BABBLE)
689 musb_intr_set(s, musb_irq_rst_babble, 1);
690
691 /* Pretend we've tried three times already and failed (in
692 * case of USB_TOKEN_SETUP). */
693 if (epnum)
694 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
695 else
696 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
697
698 musb_tx_intr_set(s, epnum, 1);
699 return;
700 }
701 /* TODO: check len for over/underruns of an OUT packet? */
702
703#ifdef SETUPLEN_HACK
704 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
705 s->setup_len = ep->packey[0].data[6];
706#endif
707
708 /* In DMA mode: if no error, assert DMA request for this EP,
709 * and skip the interrupt. */
710 musb_tx_intr_set(s, epnum, 1);
711}
712
713static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
714{
715 /* Unfortunately we can't use packey->devep because that's the remote
716 * endpoint number and may be different than our local. */
bc24a225 717 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 718 int epnum = ep->epnum;
bc24a225 719 MUSBState *s = ep->musb;
942ac052
AZ		 720
721 ep->fifostart[1] = 0;
722 ep->fifolen[1] = 0;
723
724#ifdef CLEAR_NAK
725 if (ep->status[1] != USB_RET_NAK) {
726#endif
727 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
728 if (!epnum)
729 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
730#ifdef CLEAR_NAK
731 }
732#endif
733
734 /* Clear all of the imaginable error bits first */
735 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
736 MGC_M_RXCSR_DATAERROR);
737 if (!epnum)
738 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
739 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
740
741 if (ep->status[1] == USB_RET_STALL) {
742 ep->status[1] = 0;
4f4321c1 743 packey->result = 0;
942ac052
AZ		 744
745 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
746 if (!epnum)
747 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
748 }
749
750 if (ep->status[1] == USB_RET_NAK) {
751 ep->status[1] = 0;
752
753 /* NAK timeouts are only generated in Bulk transfers and
754 * Data-errors in Isochronous. */
755 if (ep->interrupt[1])
756 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
4f4321c1 757 packey->iov.size, musb_rx_packet_complete, 1);
942ac052
AZ		 758
759 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
760 if (!epnum)
761 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
762 }
763
764 if (ep->status[1] < 0) {
765 if (ep->status[1] == USB_RET_BABBLE) {
766 musb_intr_set(s, musb_irq_rst_babble, 1);
767 return;
768 }
769
770 /* Pretend we've tried three times already and failed (in
771 * case of a control transfer). */
772 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
773 if (!epnum)
774 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
775
776 musb_rx_intr_set(s, epnum, 1);
777 return;
778 }
779 /* TODO: check len for over/underruns of an OUT packet? */
780 /* TODO: perhaps make use of e->ext_size[1] here. */
781
4f4321c1 782 packey->result = ep->status[1];
942ac052
AZ		 783
784 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
785 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
786 if (!epnum)
787 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
788
4f4321c1 789 ep->rxcount = packey->result; /* XXX: MIN(packey->len, ep->maxp[1]); */
942ac052
AZ		 790 /* In DMA mode: assert DMA request for this EP */
791 }
792
793 /* Only if DMA has not been asserted */
794 musb_rx_intr_set(s, epnum, 1);
795}
796
4706ab6c 797static void musb_async_cancel_device(MUSBState *s, USBDevice *dev)
07771f6f 798{
07771f6f
GH		 799 int ep, dir;
800
801 for (ep = 0; ep < 16; ep++) {
802 for (dir = 0; dir < 2; dir++) {
803 if (s->ep[ep].packey[dir].p.owner != dev) {
804 continue;
805 }
806 usb_cancel_packet(&s->ep[ep].packey[dir].p);
807 /* status updates needed here? */
808 }
809 }
810}
811
bc24a225 812static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 813{
bc24a225 814 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 815 int pid;
816 int total, valid = 0;
384dce1e 817 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 818 ep->fifostart[0] += ep->fifolen[0];
819 ep->fifolen[0] = 0;
820
821 /* XXX: how's the total size of the packet retrieved exactly in
822 * the generic case? */
823 total = ep->maxp[0] & 0x3ff;
824
825 if (ep->ext_size[0]) {
826 total = ep->ext_size[0];
827 ep->ext_size[0] = 0;
828 valid = 1;
829 }
830
831 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 832 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 833 return;
834
835 if (!valid)
384dce1e 836 total = ep->fifostart[0];
942ac052
AZ		 837
838 pid = USB_TOKEN_OUT;
839 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
840 pid = USB_TOKEN_SETUP;
384dce1e
RV		 841 if (total != 8) {
842 TRACE("illegal SETUPPKT length of %i bytes", total);
843 }
942ac052
AZ		 844 /* Controller should retry SETUP packets three times on errors
845 * but it doesn't make sense for us to do that. */
846 }
847
848 return musb_packet(s, ep, epnum, pid,
849 total, musb_tx_packet_complete, 0);
850}
851
bc24a225 852static void musb_rx_req(MUSBState *s, int epnum)
942ac052 853{
bc24a225 854 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 855 int total;
856
857 /* If we already have a packet, which didn't fit into the
858 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
5dc1672b 859 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 860 (ep->fifostart[1]) + ep->rxcount <
4f4321c1 861 ep->packey[1].p.iov.size) {
384dce1e
RV		 862 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
863 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 864 ep->fifolen[1] = 0;
865
4f4321c1 866 ep->rxcount = MIN(ep->packey[0].p.iov.size - (ep->fifostart[1]),
942ac052
AZ		 867 ep->maxp[1]);
868
869 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
870 if (!epnum)
871 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
872
873 /* Clear all of the error bits first */
874 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
875 MGC_M_RXCSR_DATAERROR);
876 if (!epnum)
877 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
878 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
879
880 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
881 if (!epnum)
882 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
883 musb_rx_intr_set(s, epnum, 1);
884 return;
885 }
886
887 /* The driver sets maxp[1] to 64 or less because it knows the hardware
888 * FIFO is this deep. Bigger packets get split in
889 * usb_generic_handle_packet but we can also do the splitting locally
890 * for performance. It turns out we can also have a bigger FIFO and
891 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
892 * OK with single packets of even 32KB and we avoid splitting, however
893 * usb_msd.c sometimes sends a packet bigger than what Linux expects
894 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
895 * hides this overrun from Linux. Up to 4096 everything is fine
896 * though. Currently this is disabled.
897 *
898 * XXX: mind ep->fifosize. */
899 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
900
901#ifdef SETUPLEN_HACK
902 /* Why should *we* do that instead of Linux? */
903 if (!epnum) {
5dc1672b 904 if (ep->packey[0].p.devaddr == 2) {
942ac052 905 total = MIN(s->setup_len, 8);
5dc1672b 906 } else {
942ac052 907 total = MIN(s->setup_len, 64);
5dc1672b 908 }
942ac052
AZ		 909 s->setup_len -= total;
910 }
911#endif
912
913 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
914 total, musb_rx_packet_complete, 1);
915}
916
384dce1e
RV		 917static uint8_t musb_read_fifo(MUSBEndPoint *ep)
918{
919 uint8_t value;
920 if (ep->fifolen[1] >= 64) {
921 /* We have a FIFO underrun */
922 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
923 return 0x00000000;
924 }
925 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
926 * (if AUTOREQ is set) */
927
928 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
929 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
930 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
931 return value;
932}
933
934static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
935{
936 TRACE("EP%d = %02x", ep->epnum, value);
937 if (ep->fifolen[0] >= 64) {
938 /* We have a FIFO overrun */
939 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
940 return;
941 }
942
943 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
944 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
945}
946
bc24a225 947static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 948{
949 if (ep->intv_timer[dir])
950 qemu_del_timer(ep->intv_timer[dir]);
951}
952
953/* Bus control */
954static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
955{
bc24a225 956 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 957
958 switch (addr) {
959 /* For USB2.0 HS hubs only */
960 case MUSB_HDRC_TXHUBADDR:
961 return s->ep[ep].haddr[0];
962 case MUSB_HDRC_TXHUBPORT:
963 return s->ep[ep].hport[0];
964 case MUSB_HDRC_RXHUBADDR:
965 return s->ep[ep].haddr[1];
966 case MUSB_HDRC_RXHUBPORT:
967 return s->ep[ep].hport[1];
968
969 default:
384dce1e 970 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 971 return 0x00;
972 };
973}
974
975static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
976{
bc24a225 977 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 978
979 switch (addr) {
384dce1e
RV		 980 case MUSB_HDRC_TXFUNCADDR:
981 s->ep[ep].faddr[0] = value;
982 break;
983 case MUSB_HDRC_RXFUNCADDR:
984 s->ep[ep].faddr[1] = value;
985 break;
942ac052
AZ		 986 case MUSB_HDRC_TXHUBADDR:
987 s->ep[ep].haddr[0] = value;
988 break;
989 case MUSB_HDRC_TXHUBPORT:
990 s->ep[ep].hport[0] = value;
991 break;
992 case MUSB_HDRC_RXHUBADDR:
993 s->ep[ep].haddr[1] = value;
994 break;
995 case MUSB_HDRC_RXHUBPORT:
996 s->ep[ep].hport[1] = value;
997 break;
998
999 default:
384dce1e
RV		 1000 TRACE("unknown register 0x%02x", addr);
1001 break;
942ac052
AZ		 1002 };
1003}
1004
1005static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
1006{
bc24a225 1007 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1008
1009 switch (addr) {
1010 case MUSB_HDRC_TXFUNCADDR:
1011 return s->ep[ep].faddr[0];
1012 case MUSB_HDRC_RXFUNCADDR:
1013 return s->ep[ep].faddr[1];
1014
1015 default:
1016 return musb_busctl_readb(s, ep, addr) |
1017 (musb_busctl_readb(s, ep, addr | 1) << 8);
1018 };
1019}
1020
1021static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
1022{
bc24a225 1023 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1024
1025 switch (addr) {
1026 case MUSB_HDRC_TXFUNCADDR:
1027 s->ep[ep].faddr[0] = value;
1028 break;
1029 case MUSB_HDRC_RXFUNCADDR:
1030 s->ep[ep].faddr[1] = value;
1031 break;
1032
1033 default:
1034 musb_busctl_writeb(s, ep, addr, value & 0xff);
1035 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1036 };
1037}
1038
1039/* Endpoint control */
1040static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1041{
bc24a225 1042 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1043
1044 switch (addr) {
1045 case MUSB_HDRC_TXTYPE:
1046 return s->ep[ep].type[0];
1047 case MUSB_HDRC_TXINTERVAL:
1048 return s->ep[ep].interval[0];
1049 case MUSB_HDRC_RXTYPE:
1050 return s->ep[ep].type[1];
1051 case MUSB_HDRC_RXINTERVAL:
1052 return s->ep[ep].interval[1];
1053 case (MUSB_HDRC_FIFOSIZE & ~1):
1054 return 0x00;
1055 case MUSB_HDRC_FIFOSIZE:
1056 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1057 case MUSB_HDRC_RXCOUNT:
1058 return s->ep[ep].rxcount;
942ac052
AZ		 1059
1060 default:
384dce1e 1061 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1062 return 0x00;
1063 };
1064}
1065
1066static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1067{
bc24a225 1068 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1069
1070 switch (addr) {
1071 case MUSB_HDRC_TXTYPE:
1072 s->ep[ep].type[0] = value;
1073 break;
1074 case MUSB_HDRC_TXINTERVAL:
1075 s->ep[ep].interval[0] = value;
1076 musb_ep_frame_cancel(&s->ep[ep], 0);
1077 break;
1078 case MUSB_HDRC_RXTYPE:
1079 s->ep[ep].type[1] = value;
1080 break;
1081 case MUSB_HDRC_RXINTERVAL:
1082 s->ep[ep].interval[1] = value;
1083 musb_ep_frame_cancel(&s->ep[ep], 1);
1084 break;
1085 case (MUSB_HDRC_FIFOSIZE & ~1):
1086 break;
1087 case MUSB_HDRC_FIFOSIZE:
384dce1e 1088 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1089 s->ep[ep].fifosize = value;
1090 break;
942ac052 1091 default:
384dce1e
RV		 1092 TRACE("unknown register 0x%02x", addr);
1093 break;
942ac052
AZ		 1094 };
1095}
1096
1097static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1098{
bc24a225 1099 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1100 uint16_t ret;
1101
1102 switch (addr) {
1103 case MUSB_HDRC_TXMAXP:
1104 return s->ep[ep].maxp[0];
1105 case MUSB_HDRC_TXCSR:
1106 return s->ep[ep].csr[0];
1107 case MUSB_HDRC_RXMAXP:
1108 return s->ep[ep].maxp[1];
1109 case MUSB_HDRC_RXCSR:
1110 ret = s->ep[ep].csr[1];
1111
1112 /* TODO: This and other bits probably depend on
1113 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1114 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1115 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1116
1117 return ret;
1118 case MUSB_HDRC_RXCOUNT:
1119 return s->ep[ep].rxcount;
1120
1121 default:
1122 return musb_ep_readb(s, ep, addr) |
1123 (musb_ep_readb(s, ep, addr | 1) << 8);
1124 };
1125}
1126
1127static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1128{
bc24a225 1129 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1130
1131 switch (addr) {
1132 case MUSB_HDRC_TXMAXP:
1133 s->ep[ep].maxp[0] = value;
1134 break;
1135 case MUSB_HDRC_TXCSR:
1136 if (ep) {
1137 s->ep[ep].csr[0] &= value & 0xa6;
1138 s->ep[ep].csr[0] |= value & 0xff59;
1139 } else {
1140 s->ep[ep].csr[0] &= value & 0x85;
1141 s->ep[ep].csr[0] |= value & 0xf7a;
1142 }
1143
1144 musb_ep_frame_cancel(&s->ep[ep], 0);
1145
1146 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1147 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1148 s->ep[ep].fifolen[0] = 0;
1149 s->ep[ep].fifostart[0] = 0;
1150 if (ep)
1151 s->ep[ep].csr[0] &=
1152 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1153 else
1154 s->ep[ep].csr[0] &=
1155 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1156 }
1157 if (
1158 (ep &&
1159#ifdef CLEAR_NAK
1160 (value & MGC_M_TXCSR_TXPKTRDY) &&
1161 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1162#else
1163 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1164#endif
1165 (!ep &&
1166#ifdef CLEAR_NAK
1167 (value & MGC_M_CSR0_TXPKTRDY) &&
1168 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1169#else
1170 (value & MGC_M_CSR0_TXPKTRDY)))
1171#endif
1172 musb_tx_rdy(s, ep);
1173 if (!ep &&
1174 (value & MGC_M_CSR0_H_REQPKT) &&
1175#ifdef CLEAR_NAK
1176 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1177 MGC_M_CSR0_RXPKTRDY)))
1178#else
1179 !(value & MGC_M_CSR0_RXPKTRDY))
1180#endif
1181 musb_rx_req(s, ep);
1182 break;
1183
1184 case MUSB_HDRC_RXMAXP:
1185 s->ep[ep].maxp[1] = value;
1186 break;
1187 case MUSB_HDRC_RXCSR:
1188 /* (DMA mode only) */
1189 if (
1190 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1191 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1192 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1193 value |= MGC_M_RXCSR_H_REQPKT;
1194
1195 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1196 s->ep[ep].csr[1] |= value & 0xfeb0;
1197
1198 musb_ep_frame_cancel(&s->ep[ep], 1);
1199
1200 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1201 s->ep[ep].fifolen[1] = 0;
1202 s->ep[ep].fifostart[1] = 0;
1203 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1204 /* If double buffering and we have two packets ready, flush
1205 * only the first one and set up the fifo at the second packet. */
1206 }
1207#ifdef CLEAR_NAK
1208 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1209#else
1210 if (value & MGC_M_RXCSR_H_REQPKT)
1211#endif
1212 musb_rx_req(s, ep);
1213 break;
1214 case MUSB_HDRC_RXCOUNT:
1215 s->ep[ep].rxcount = value;
1216 break;
1217
1218 default:
1219 musb_ep_writeb(s, ep, addr, value & 0xff);
1220 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1221 };
1222}
1223
1224/* Generic control */
c227f099 1225static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
942ac052 1226{
bc24a225 1227 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1228 int ep, i;
1229 uint8_t ret;
1230
1231 switch (addr) {
1232 case MUSB_HDRC_FADDR:
1233 return s->faddr;
1234 case MUSB_HDRC_POWER:
1235 return s->power;
1236 case MUSB_HDRC_INTRUSB:
1237 ret = s->intr;
1238 for (i = 0; i < sizeof(ret) * 8; i ++)
1239 if (ret & (1 << i))
1240 musb_intr_set(s, i, 0);
1241 return ret;
1242 case MUSB_HDRC_INTRUSBE:
1243 return s->mask;
1244 case MUSB_HDRC_INDEX:
1245 return s->idx;
1246 case MUSB_HDRC_TESTMODE:
1247 return 0x00;
1248
1249 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1250 return musb_ep_readb(s, s->idx, addr & 0xf);
1251
1252 case MUSB_HDRC_DEVCTL:
1253 return s->devctl;
1254
1255 case MUSB_HDRC_TXFIFOSZ:
1256 case MUSB_HDRC_RXFIFOSZ:
1257 case MUSB_HDRC_VCTRL:
1258 /* TODO */
1259 return 0x00;
1260
1261 case MUSB_HDRC_HWVERS:
1262 return (1 << 10) | 400;
1263
1264 case (MUSB_HDRC_VCTRL | 1):
1265 case (MUSB_HDRC_HWVERS | 1):
1266 case (MUSB_HDRC_DEVCTL | 1):
1267 return 0x00;
1268
1269 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1270 ep = (addr >> 3) & 0xf;
1271 return musb_busctl_readb(s, ep, addr & 0x7);
1272
1273 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1274 ep = (addr >> 4) & 0xf;
1275 return musb_ep_readb(s, ep, addr & 0xf);
1276
384dce1e
RV		 1277 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1278 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1279 return musb_read_fifo(s->ep + ep);
1280
942ac052 1281 default:
384dce1e 1282 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1283 return 0x00;
1284 };
1285}
1286
c227f099 1287static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1288{
bc24a225 1289 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1290 int ep;
1291
1292 switch (addr) {
1293 case MUSB_HDRC_FADDR:
1294 s->faddr = value & 0x7f;
1295 break;
1296 case MUSB_HDRC_POWER:
1297 s->power = (value & 0xef) | (s->power & 0x10);
1298 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1299 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1300 usb_send_msg(s->port.dev, USB_MSG_RESET);
1301 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1302 if ((value & MGC_M_POWER_HSENAB) &&
1303 s->port.dev->speed == USB_SPEED_HIGH)
1304 s->power |= MGC_M_POWER_HSMODE; /* Success */
1305 /* Restart frame counting. */
1306 }
1307 if (value & MGC_M_POWER_SUSPENDM) {
1308 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1309 * is set, also go into low power mode. Frame counting stops. */
1310 /* XXX: Cleared when the interrupt register is read */
1311 }
1312 if (value & MGC_M_POWER_RESUME) {
1313 /* Wait 20ms and signal resuming on the bus. Frame counting
1314 * restarts. */
1315 }
1316 break;
1317 case MUSB_HDRC_INTRUSB:
1318 break;
1319 case MUSB_HDRC_INTRUSBE:
1320 s->mask = value & 0xff;
1321 break;
1322 case MUSB_HDRC_INDEX:
1323 s->idx = value & 0xf;
1324 break;
1325 case MUSB_HDRC_TESTMODE:
1326 break;
1327
1328 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1329 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1330 break;
1331
1332 case MUSB_HDRC_DEVCTL:
1333 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1334 musb_session_update(s,
1335 !!s->port.dev,
1336 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1337
1338 /* It seems this is the only R/W bit in this register? */
1339 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1340 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1341 break;
1342
1343 case MUSB_HDRC_TXFIFOSZ:
1344 case MUSB_HDRC_RXFIFOSZ:
1345 case MUSB_HDRC_VCTRL:
1346 /* TODO */
1347 break;
1348
1349 case (MUSB_HDRC_VCTRL | 1):
1350 case (MUSB_HDRC_DEVCTL | 1):
1351 break;
1352
1353 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1354 ep = (addr >> 3) & 0xf;
1355 musb_busctl_writeb(s, ep, addr & 0x7, value);
1356 break;
1357
1358 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1359 ep = (addr >> 4) & 0xf;
1360 musb_ep_writeb(s, ep, addr & 0xf, value);
1361 break;
1362
384dce1e
RV		 1363 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1364 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1365 musb_write_fifo(s->ep + ep, value & 0xff);
1366 break;
1367
942ac052 1368 default:
384dce1e
RV		 1369 TRACE("unknown register 0x%02x", (int) addr);
1370 break;
942ac052
AZ		 1371 };
1372}
1373
c227f099 1374static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
942ac052 1375{
bc24a225 1376 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1377 int ep, i;
1378 uint16_t ret;
1379
1380 switch (addr) {
1381 case MUSB_HDRC_INTRTX:
1382 ret = s->tx_intr;
1383 /* Auto clear */
1384 for (i = 0; i < sizeof(ret) * 8; i ++)
1385 if (ret & (1 << i))
1386 musb_tx_intr_set(s, i, 0);
1387 return ret;
1388 case MUSB_HDRC_INTRRX:
1389 ret = s->rx_intr;
1390 /* Auto clear */
1391 for (i = 0; i < sizeof(ret) * 8; i ++)
1392 if (ret & (1 << i))
1393 musb_rx_intr_set(s, i, 0);
1394 return ret;
1395 case MUSB_HDRC_INTRTXE:
1396 return s->tx_mask;
1397 case MUSB_HDRC_INTRRXE:
1398 return s->rx_mask;
1399
1400 case MUSB_HDRC_FRAME:
1401 /* TODO */
1402 return 0x0000;
1403 case MUSB_HDRC_TXFIFOADDR:
1404 return s->ep[s->idx].fifoaddr[0];
1405 case MUSB_HDRC_RXFIFOADDR:
1406 return s->ep[s->idx].fifoaddr[1];
1407
1408 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1409 return musb_ep_readh(s, s->idx, addr & 0xf);
1410
1411 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1412 ep = (addr >> 3) & 0xf;
1413 return musb_busctl_readh(s, ep, addr & 0x7);
1414
1415 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1416 ep = (addr >> 4) & 0xf;
1417 return musb_ep_readh(s, ep, addr & 0xf);
1418
384dce1e
RV		 1419 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1420 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1421 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1422
942ac052
AZ		 1423 default:
1424 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1425 };
1426}
1427
c227f099 1428static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1429{
bc24a225 1430 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1431 int ep;
1432
1433 switch (addr) {
1434 case MUSB_HDRC_INTRTXE:
1435 s->tx_mask = value;
1436 /* XXX: the masks seem to apply on the raising edge like with
1437 * edge-triggered interrupts, thus no need to update. I may be
1438 * wrong though. */
1439 break;
1440 case MUSB_HDRC_INTRRXE:
1441 s->rx_mask = value;
1442 break;
1443
1444 case MUSB_HDRC_FRAME:
1445 /* TODO */
1446 break;
1447 case MUSB_HDRC_TXFIFOADDR:
1448 s->ep[s->idx].fifoaddr[0] = value;
1449 s->ep[s->idx].buf[0] =
384dce1e 1450 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1451 break;
1452 case MUSB_HDRC_RXFIFOADDR:
1453 s->ep[s->idx].fifoaddr[1] = value;
1454 s->ep[s->idx].buf[1] =
384dce1e 1455 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1456 break;
1457
1458 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1459 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1460 break;
1461
1462 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1463 ep = (addr >> 3) & 0xf;
1464 musb_busctl_writeh(s, ep, addr & 0x7, value);
1465 break;
1466
1467 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1468 ep = (addr >> 4) & 0xf;
1469 musb_ep_writeh(s, ep, addr & 0xf, value);
1470 break;
1471
384dce1e
RV		 1472 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1473 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1474 musb_write_fifo(s->ep + ep, value & 0xff);
1475 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1476 break;
1477
942ac052
AZ		 1478 default:
1479 musb_writeb(s, addr, value & 0xff);
1480 musb_writeb(s, addr | 1, value >> 8);
1481 };
1482}
1483
c227f099 1484static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
942ac052 1485{
bc24a225 1486 MUSBState *s = (MUSBState *) opaque;
384dce1e 1487 int ep;
942ac052
AZ		 1488
1489 switch (addr) {
1490 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1491 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1492 return ( musb_read_fifo(s->ep + ep) |
1493 musb_read_fifo(s->ep + ep) << 8 |
1494 musb_read_fifo(s->ep + ep) << 16 |
1495 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1496 default:
384dce1e 1497 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1498 return 0x00000000;
1499 };
1500}
1501
c227f099 1502static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1503{
bc24a225 1504 MUSBState *s = (MUSBState *) opaque;
384dce1e 1505 int ep;
942ac052
AZ		 1506
1507 switch (addr) {
1508 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1509 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1510 musb_write_fifo(s->ep + ep, value & 0xff);
1511 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1512 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1513 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1514 break;
942ac052 1515 default:
384dce1e
RV		 1516 TRACE("unknown register 0x%02x", (int) addr);
1517 break;
942ac052
AZ		 1518 };
1519}
1520
d60efc6b 1521CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1522 musb_readb,
1523 musb_readh,
1524 musb_readw,
1525};
1526
d60efc6b 1527CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1528 musb_writeb,
1529 musb_writeh,
1530 musb_writew,
1531};
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