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usb: Make port wakeup and complete ops take a USBPort instead of a Device
[qemu.git] / hw / usb-musb.c
CommitLineData
942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "usb.h"
26#include "irq.h"
384dce1e 27#include "hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
618c169b
GH		 262static void musb_attach(USBPort *port);
263static void musb_detach(USBPort *port);
d47e59b8 264static void musb_schedule_cb(USBPort *port, USBPacket *p);
07771f6f 265static void musb_device_destroy(USBBus *bus, USBDevice *dev);
942ac052 266
0d86d2be
GH		 267static USBPortOps musb_port_ops = {
268 .attach = musb_attach,
618c169b 269 .detach = musb_detach,
13a9a0d3 270 .complete = musb_schedule_cb,
0d86d2be
GH		 271};
272
07771f6f
GH		 273static USBBusOps musb_bus_ops = {
274 .device_destroy = musb_device_destroy,
275};
276
5dc1672b
GH		 277typedef struct MUSBPacket MUSBPacket;
278typedef struct MUSBEndPoint MUSBEndPoint;
279
280struct MUSBPacket {
281 USBPacket p;
282 MUSBEndPoint *ep;
283 int dir;
284};
285
286struct MUSBEndPoint {
bc24a225
PB		 287 uint16_t faddr[2];
288 uint8_t haddr[2];
289 uint8_t hport[2];
290 uint16_t csr[2];
291 uint16_t maxp[2];
292 uint16_t rxcount;
293 uint8_t type[2];
294 uint8_t interval[2];
295 uint8_t config;
296 uint8_t fifosize;
297 int timeout[2]; /* Always in microframes */
298
384dce1e 299 uint8_t *buf[2];
bc24a225
PB		 300 int fifolen[2];
301 int fifostart[2];
302 int fifoaddr[2];
5dc1672b 303 MUSBPacket packey[2];
bc24a225
PB		 304 int status[2];
305 int ext_size[2];
306
307 /* For callbacks' use */
308 int epnum;
309 int interrupt[2];
310 MUSBState *musb;
311 USBCallback *delayed_cb[2];
312 QEMUTimer *intv_timer[2];
5dc1672b 313};
bc24a225
PB		 314
315struct MUSBState {
942ac052 316 qemu_irq *irqs;
b2317837 317 USBBus bus;
942ac052
AZ		 318 USBPort port;
319
320 int idx;
321 uint8_t devctl;
322 uint8_t power;
323 uint8_t faddr;
324
325 uint8_t intr;
326 uint8_t mask;
327 uint16_t tx_intr;
328 uint16_t tx_mask;
329 uint16_t rx_intr;
330 uint16_t rx_mask;
331
332 int setup_len;
333 int session;
334
384dce1e 335 uint8_t buf[0x8000];
942ac052 336
942ac052
AZ		 337 /* Duplicating the world since 2008!... probably we should have 32
338 * logical, single endpoints instead. */
bc24a225 339 MUSBEndPoint ep[16];
5dc1672b
GH		 340};
341
342struct MUSBState *musb_init(qemu_irq *irqs)
942ac052 343{
bc24a225 344 MUSBState *s = qemu_mallocz(sizeof(*s));
942ac052
AZ		 345 int i;
346
347 s->irqs = irqs;
348
349 s->faddr = 0x00;
350 s->power = MGC_M_POWER_HSENAB;
351 s->tx_intr = 0x0000;
352 s->rx_intr = 0x0000;
353 s->tx_mask = 0xffff;
354 s->rx_mask = 0xffff;
355 s->intr = 0x00;
356 s->mask = 0x06;
357 s->idx = 0;
358
359 /* TODO: _DW */
360 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
361 for (i = 0; i < 16; i ++) {
362 s->ep[i].fifosize = 64;
363 s->ep[i].maxp[0] = 0x40;
364 s->ep[i].maxp[1] = 0x40;
365 s->ep[i].musb = s;
366 s->ep[i].epnum = i;
367 }
368
07771f6f 369 usb_bus_new(&s->bus, &musb_bus_ops, NULL /* FIXME */);
ace1318b 370 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
843d4e0c 371 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
942ac052
AZ		 372
373 return s;
374}
375
bc24a225 376static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 377{
378 if (level)
379 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
380 else
381 s->devctl &= ~MGC_M_DEVCTL_VBUS;
382
383 qemu_set_irq(s->irqs[musb_set_vbus], level);
384}
385
bc24a225 386static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 387{
388 if (!level) {
389 s->intr &= ~(1 << line);
390 qemu_irq_lower(s->irqs[line]);
391 } else if (s->mask & (1 << line)) {
392 s->intr |= 1 << line;
393 qemu_irq_raise(s->irqs[line]);
394 }
395}
396
bc24a225 397static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 398{
399 if (!level) {
400 s->tx_intr &= ~(1 << line);
401 if (!s->tx_intr)
402 qemu_irq_lower(s->irqs[musb_irq_tx]);
403 } else if (s->tx_mask & (1 << line)) {
404 s->tx_intr |= 1 << line;
405 qemu_irq_raise(s->irqs[musb_irq_tx]);
406 }
407}
408
bc24a225 409static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 410{
411 if (line) {
412 if (!level) {
413 s->rx_intr &= ~(1 << line);
414 if (!s->rx_intr)
415 qemu_irq_lower(s->irqs[musb_irq_rx]);
416 } else if (s->rx_mask & (1 << line)) {
417 s->rx_intr |= 1 << line;
418 qemu_irq_raise(s->irqs[musb_irq_rx]);
419 }
420 } else
421 musb_tx_intr_set(s, line, level);
422}
423
bc24a225 424uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 425{
426 return (s->rx_intr << 15) | s->tx_intr;
427}
428
bc24a225 429void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 430{
431 if (s->rx_intr) {
432 s->rx_intr &= mask >> 15;
433 if (!s->rx_intr)
434 qemu_irq_lower(s->irqs[musb_irq_rx]);
435 }
436
437 if (s->tx_intr) {
438 s->tx_intr &= mask & 0xffff;
439 if (!s->tx_intr)
440 qemu_irq_lower(s->irqs[musb_irq_tx]);
441 }
442}
443
bc24a225 444void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 445{
446 s->ep[epnum].ext_size[!is_tx] = size;
447 s->ep[epnum].fifostart[0] = 0;
448 s->ep[epnum].fifostart[1] = 0;
449 s->ep[epnum].fifolen[0] = 0;
450 s->ep[epnum].fifolen[1] = 0;
451}
452
bc24a225 453static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 454{
455 int detect_prev = prev_dev && prev_sess;
456 int detect = !!s->port.dev && s->session;
457
458 if (detect && !detect_prev) {
459 /* Let's skip the ID pin sense and VBUS sense formalities and
460 * and signal a successful SRP directly. This should work at least
461 * for the Linux driver stack. */
462 musb_intr_set(s, musb_irq_connect, 1);
463
464 if (s->port.dev->speed == USB_SPEED_LOW) {
465 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
466 s->devctl |= MGC_M_DEVCTL_LSDEV;
467 } else {
468 s->devctl |= MGC_M_DEVCTL_FSDEV;
469 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
470 }
471
472 /* A-mode? */
473 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
474
475 /* Host-mode bit? */
476 s->devctl |= MGC_M_DEVCTL_HM;
477#if 1
478 musb_vbus_set(s, 1);
479#endif
480 } else if (!detect && detect_prev) {
481#if 1
482 musb_vbus_set(s, 0);
483#endif
484 }
485}
486
487/* Attach or detach a device on our only port. */
618c169b 488static void musb_attach(USBPort *port)
942ac052 489{
bc24a225 490 MUSBState *s = (MUSBState *) port->opaque;
942ac052 491
618c169b
GH		 492 musb_intr_set(s, musb_irq_vbus_request, 1);
493 musb_session_update(s, 0, s->session);
494}
942ac052 495
618c169b
GH		 496static void musb_detach(USBPort *port)
497{
498 MUSBState *s = (MUSBState *) port->opaque;
942ac052 499
618c169b
GH		 500 musb_intr_set(s, musb_irq_disconnect, 1);
501 musb_session_update(s, 1, s->session);
942ac052
AZ		 502}
503
b3e5759e 504static void musb_cb_tick0(void *opaque)
942ac052 505{
bc24a225 506 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 507
5dc1672b 508 ep->delayed_cb[0](&ep->packey[0].p, opaque);
942ac052
AZ		 509}
510
b3e5759e 511static void musb_cb_tick1(void *opaque)
942ac052 512{
bc24a225 513 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 514
5dc1672b 515 ep->delayed_cb[1](&ep->packey[1].p, opaque);
942ac052
AZ		 516}
517
518#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
519
d47e59b8 520static void musb_schedule_cb(USBPort *port, USBPacket *packey)
942ac052 521{
13a9a0d3
GH		 522 MUSBPacket *p = container_of(packey, MUSBPacket, p);
523 MUSBEndPoint *ep = p->ep;
524 int dir = p->dir;
942ac052
AZ		 525 int timeout = 0;
526
527 if (ep->status[dir] == USB_RET_NAK)
528 timeout = ep->timeout[dir];
529 else if (ep->interrupt[dir])
530 timeout = 8;
531 else
13a9a0d3 532 return musb_cb_tick(ep);
942ac052
AZ		 533
534 if (!ep->intv_timer[dir])
13a9a0d3 535 ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, ep);
942ac052 536
74475455 537 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
6ee093c9 538 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 539}
540
942ac052
AZ		 541static int musb_timeout(int ttype, int speed, int val)
542{
543#if 1
544 return val << 3;
545#endif
546
547 switch (ttype) {
548 case USB_ENDPOINT_XFER_CONTROL:
549 if (val < 2)
550 return 0;
551 else if (speed == USB_SPEED_HIGH)
552 return 1 << (val - 1);
553 else
554 return 8 << (val - 1);
555
556 case USB_ENDPOINT_XFER_INT:
557 if (speed == USB_SPEED_HIGH)
558 if (val < 2)
559 return 0;
560 else
561 return 1 << (val - 1);
562 else
563 return val << 3;
564
565 case USB_ENDPOINT_XFER_BULK:
566 case USB_ENDPOINT_XFER_ISOC:
567 if (val < 2)
568 return 0;
569 else if (speed == USB_SPEED_HIGH)
570 return 1 << (val - 1);
571 else
572 return 8 << (val - 1);
573 /* TODO: what with low-speed Bulk and Isochronous? */
574 }
575
2ac71179 576 hw_error("bad interval\n");
942ac052
AZ		 577}
578
b3e5759e 579static void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 580 int epnum, int pid, int len, USBCallback cb, int dir)
581{
582 int ret;
583 int idx = epnum && dir;
584 int ttype;
585
586 /* ep->type[0,1] contains:
587 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
588 * in bits 5:4 the transfer type (BULK / INT)
589 * in bits 3:0 the EP num
590 */
591 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
592
593 ep->timeout[dir] = musb_timeout(ttype,
594 ep->type[idx] >> 6, ep->interval[idx]);
595 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
596 ep->delayed_cb[dir] = cb;
942ac052 597
5dc1672b 598 ep->packey[dir].p.pid = pid;
942ac052 599 /* A wild guess on the FADDR semantics... */
5dc1672b
GH		 600 ep->packey[dir].p.devaddr = ep->faddr[idx];
601 ep->packey[dir].p.devep = ep->type[idx] & 0xf;
602 ep->packey[dir].p.data = (void *) ep->buf[idx];
603 ep->packey[dir].p.len = len;
5dc1672b
GH		 604 ep->packey[dir].ep = ep;
605 ep->packey[dir].dir = dir;
942ac052
AZ		 606
607 if (s->port.dev)
53aa8c0e 608 ret = usb_handle_packet(s->port.dev, &ep->packey[dir].p);
942ac052
AZ		 609 else
610 ret = USB_RET_NODEV;
611
612 if (ret == USB_RET_ASYNC) {
613 ep->status[dir] = len;
614 return;
615 }
616
617 ep->status[dir] = ret;
d47e59b8 618 musb_schedule_cb(&s->port, &ep->packey[dir].p);
942ac052
AZ		 619}
620
621static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
622{
623 /* Unfortunately we can't use packey->devep because that's the remote
624 * endpoint number and may be different than our local. */
bc24a225 625 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 626 int epnum = ep->epnum;
bc24a225 627 MUSBState *s = ep->musb;
942ac052
AZ		 628
629 ep->fifostart[0] = 0;
630 ep->fifolen[0] = 0;
631#ifdef CLEAR_NAK
632 if (ep->status[0] != USB_RET_NAK) {
633#endif
634 if (epnum)
635 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
636 else
637 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
638#ifdef CLEAR_NAK
639 }
640#endif
641
642 /* Clear all of the error bits first */
643 if (epnum)
644 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
645 MGC_M_TXCSR_H_NAKTIMEOUT);
646 else
647 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
648 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
649
650 if (ep->status[0] == USB_RET_STALL) {
651 /* Command not supported by target! */
652 ep->status[0] = 0;
653
654 if (epnum)
655 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
656 else
657 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
658 }
659
660 if (ep->status[0] == USB_RET_NAK) {
661 ep->status[0] = 0;
662
663 /* NAK timeouts are only generated in Bulk transfers and
664 * Data-errors in Isochronous. */
665 if (ep->interrupt[0]) {
666 return;
667 }
668
669 if (epnum)
670 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
671 else
672 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
673 }
674
675 if (ep->status[0] < 0) {
676 if (ep->status[0] == USB_RET_BABBLE)
677 musb_intr_set(s, musb_irq_rst_babble, 1);
678
679 /* Pretend we've tried three times already and failed (in
680 * case of USB_TOKEN_SETUP). */
681 if (epnum)
682 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
683 else
684 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
685
686 musb_tx_intr_set(s, epnum, 1);
687 return;
688 }
689 /* TODO: check len for over/underruns of an OUT packet? */
690
691#ifdef SETUPLEN_HACK
692 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
693 s->setup_len = ep->packey[0].data[6];
694#endif
695
696 /* In DMA mode: if no error, assert DMA request for this EP,
697 * and skip the interrupt. */
698 musb_tx_intr_set(s, epnum, 1);
699}
700
701static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
702{
703 /* Unfortunately we can't use packey->devep because that's the remote
704 * endpoint number and may be different than our local. */
bc24a225 705 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 706 int epnum = ep->epnum;
bc24a225 707 MUSBState *s = ep->musb;
942ac052
AZ		 708
709 ep->fifostart[1] = 0;
710 ep->fifolen[1] = 0;
711
712#ifdef CLEAR_NAK
713 if (ep->status[1] != USB_RET_NAK) {
714#endif
715 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
716 if (!epnum)
717 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
718#ifdef CLEAR_NAK
719 }
720#endif
721
722 /* Clear all of the imaginable error bits first */
723 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
724 MGC_M_RXCSR_DATAERROR);
725 if (!epnum)
726 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
727 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
728
729 if (ep->status[1] == USB_RET_STALL) {
730 ep->status[1] = 0;
731 packey->len = 0;
732
733 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
734 if (!epnum)
735 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
736 }
737
738 if (ep->status[1] == USB_RET_NAK) {
739 ep->status[1] = 0;
740
741 /* NAK timeouts are only generated in Bulk transfers and
742 * Data-errors in Isochronous. */
743 if (ep->interrupt[1])
744 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
745 packey->len, musb_rx_packet_complete, 1);
746
747 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
748 if (!epnum)
749 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
750 }
751
752 if (ep->status[1] < 0) {
753 if (ep->status[1] == USB_RET_BABBLE) {
754 musb_intr_set(s, musb_irq_rst_babble, 1);
755 return;
756 }
757
758 /* Pretend we've tried three times already and failed (in
759 * case of a control transfer). */
760 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
761 if (!epnum)
762 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
763
764 musb_rx_intr_set(s, epnum, 1);
765 return;
766 }
767 /* TODO: check len for over/underruns of an OUT packet? */
768 /* TODO: perhaps make use of e->ext_size[1] here. */
769
770 packey->len = ep->status[1];
771
772 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
773 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
774 if (!epnum)
775 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
776
777 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
778 /* In DMA mode: assert DMA request for this EP */
779 }
780
781 /* Only if DMA has not been asserted */
782 musb_rx_intr_set(s, epnum, 1);
783}
784
07771f6f
GH		 785static void musb_device_destroy(USBBus *bus, USBDevice *dev)
786{
787 MUSBState *s = container_of(bus, MUSBState, bus);
788 int ep, dir;
789
790 for (ep = 0; ep < 16; ep++) {
791 for (dir = 0; dir < 2; dir++) {
792 if (s->ep[ep].packey[dir].p.owner != dev) {
793 continue;
794 }
795 usb_cancel_packet(&s->ep[ep].packey[dir].p);
796 /* status updates needed here? */
797 }
798 }
799}
800
bc24a225 801static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 802{
bc24a225 803 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 804 int pid;
805 int total, valid = 0;
384dce1e 806 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 807 ep->fifostart[0] += ep->fifolen[0];
808 ep->fifolen[0] = 0;
809
810 /* XXX: how's the total size of the packet retrieved exactly in
811 * the generic case? */
812 total = ep->maxp[0] & 0x3ff;
813
814 if (ep->ext_size[0]) {
815 total = ep->ext_size[0];
816 ep->ext_size[0] = 0;
817 valid = 1;
818 }
819
820 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 821 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 822 return;
823
824 if (!valid)
384dce1e 825 total = ep->fifostart[0];
942ac052
AZ		 826
827 pid = USB_TOKEN_OUT;
828 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
829 pid = USB_TOKEN_SETUP;
384dce1e
RV		 830 if (total != 8) {
831 TRACE("illegal SETUPPKT length of %i bytes", total);
832 }
942ac052
AZ		 833 /* Controller should retry SETUP packets three times on errors
834 * but it doesn't make sense for us to do that. */
835 }
836
837 return musb_packet(s, ep, epnum, pid,
838 total, musb_tx_packet_complete, 0);
839}
840
bc24a225 841static void musb_rx_req(MUSBState *s, int epnum)
942ac052 842{
bc24a225 843 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 844 int total;
845
846 /* If we already have a packet, which didn't fit into the
847 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
5dc1672b 848 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 849 (ep->fifostart[1]) + ep->rxcount <
5dc1672b 850 ep->packey[1].p.len) {
384dce1e
RV		 851 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
852 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 853 ep->fifolen[1] = 0;
854
5dc1672b 855 ep->rxcount = MIN(ep->packey[0].p.len - (ep->fifostart[1]),
942ac052
AZ		 856 ep->maxp[1]);
857
858 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
859 if (!epnum)
860 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
861
862 /* Clear all of the error bits first */
863 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
864 MGC_M_RXCSR_DATAERROR);
865 if (!epnum)
866 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
867 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
868
869 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
870 if (!epnum)
871 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
872 musb_rx_intr_set(s, epnum, 1);
873 return;
874 }
875
876 /* The driver sets maxp[1] to 64 or less because it knows the hardware
877 * FIFO is this deep. Bigger packets get split in
878 * usb_generic_handle_packet but we can also do the splitting locally
879 * for performance. It turns out we can also have a bigger FIFO and
880 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
881 * OK with single packets of even 32KB and we avoid splitting, however
882 * usb_msd.c sometimes sends a packet bigger than what Linux expects
883 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
884 * hides this overrun from Linux. Up to 4096 everything is fine
885 * though. Currently this is disabled.
886 *
887 * XXX: mind ep->fifosize. */
888 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
889
890#ifdef SETUPLEN_HACK
891 /* Why should *we* do that instead of Linux? */
892 if (!epnum) {
5dc1672b 893 if (ep->packey[0].p.devaddr == 2) {
942ac052 894 total = MIN(s->setup_len, 8);
5dc1672b 895 } else {
942ac052 896 total = MIN(s->setup_len, 64);
5dc1672b 897 }
942ac052
AZ		 898 s->setup_len -= total;
899 }
900#endif
901
902 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
903 total, musb_rx_packet_complete, 1);
904}
905
384dce1e
RV		 906static uint8_t musb_read_fifo(MUSBEndPoint *ep)
907{
908 uint8_t value;
909 if (ep->fifolen[1] >= 64) {
910 /* We have a FIFO underrun */
911 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
912 return 0x00000000;
913 }
914 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
915 * (if AUTOREQ is set) */
916
917 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
918 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
919 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
920 return value;
921}
922
923static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
924{
925 TRACE("EP%d = %02x", ep->epnum, value);
926 if (ep->fifolen[0] >= 64) {
927 /* We have a FIFO overrun */
928 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
929 return;
930 }
931
932 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
933 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
934}
935
bc24a225 936static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 937{
938 if (ep->intv_timer[dir])
939 qemu_del_timer(ep->intv_timer[dir]);
940}
941
942/* Bus control */
943static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
944{
bc24a225 945 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 946
947 switch (addr) {
948 /* For USB2.0 HS hubs only */
949 case MUSB_HDRC_TXHUBADDR:
950 return s->ep[ep].haddr[0];
951 case MUSB_HDRC_TXHUBPORT:
952 return s->ep[ep].hport[0];
953 case MUSB_HDRC_RXHUBADDR:
954 return s->ep[ep].haddr[1];
955 case MUSB_HDRC_RXHUBPORT:
956 return s->ep[ep].hport[1];
957
958 default:
384dce1e 959 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 960 return 0x00;
961 };
962}
963
964static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
965{
bc24a225 966 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 967
968 switch (addr) {
384dce1e
RV		 969 case MUSB_HDRC_TXFUNCADDR:
970 s->ep[ep].faddr[0] = value;
971 break;
972 case MUSB_HDRC_RXFUNCADDR:
973 s->ep[ep].faddr[1] = value;
974 break;
942ac052
AZ		 975 case MUSB_HDRC_TXHUBADDR:
976 s->ep[ep].haddr[0] = value;
977 break;
978 case MUSB_HDRC_TXHUBPORT:
979 s->ep[ep].hport[0] = value;
980 break;
981 case MUSB_HDRC_RXHUBADDR:
982 s->ep[ep].haddr[1] = value;
983 break;
984 case MUSB_HDRC_RXHUBPORT:
985 s->ep[ep].hport[1] = value;
986 break;
987
988 default:
384dce1e
RV		 989 TRACE("unknown register 0x%02x", addr);
990 break;
942ac052
AZ		 991 };
992}
993
994static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
995{
bc24a225 996 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 997
998 switch (addr) {
999 case MUSB_HDRC_TXFUNCADDR:
1000 return s->ep[ep].faddr[0];
1001 case MUSB_HDRC_RXFUNCADDR:
1002 return s->ep[ep].faddr[1];
1003
1004 default:
1005 return musb_busctl_readb(s, ep, addr) |
1006 (musb_busctl_readb(s, ep, addr | 1) << 8);
1007 };
1008}
1009
1010static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
1011{
bc24a225 1012 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1013
1014 switch (addr) {
1015 case MUSB_HDRC_TXFUNCADDR:
1016 s->ep[ep].faddr[0] = value;
1017 break;
1018 case MUSB_HDRC_RXFUNCADDR:
1019 s->ep[ep].faddr[1] = value;
1020 break;
1021
1022 default:
1023 musb_busctl_writeb(s, ep, addr, value & 0xff);
1024 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1025 };
1026}
1027
1028/* Endpoint control */
1029static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1030{
bc24a225 1031 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1032
1033 switch (addr) {
1034 case MUSB_HDRC_TXTYPE:
1035 return s->ep[ep].type[0];
1036 case MUSB_HDRC_TXINTERVAL:
1037 return s->ep[ep].interval[0];
1038 case MUSB_HDRC_RXTYPE:
1039 return s->ep[ep].type[1];
1040 case MUSB_HDRC_RXINTERVAL:
1041 return s->ep[ep].interval[1];
1042 case (MUSB_HDRC_FIFOSIZE & ~1):
1043 return 0x00;
1044 case MUSB_HDRC_FIFOSIZE:
1045 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1046 case MUSB_HDRC_RXCOUNT:
1047 return s->ep[ep].rxcount;
942ac052
AZ		 1048
1049 default:
384dce1e 1050 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1051 return 0x00;
1052 };
1053}
1054
1055static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1056{
bc24a225 1057 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1058
1059 switch (addr) {
1060 case MUSB_HDRC_TXTYPE:
1061 s->ep[ep].type[0] = value;
1062 break;
1063 case MUSB_HDRC_TXINTERVAL:
1064 s->ep[ep].interval[0] = value;
1065 musb_ep_frame_cancel(&s->ep[ep], 0);
1066 break;
1067 case MUSB_HDRC_RXTYPE:
1068 s->ep[ep].type[1] = value;
1069 break;
1070 case MUSB_HDRC_RXINTERVAL:
1071 s->ep[ep].interval[1] = value;
1072 musb_ep_frame_cancel(&s->ep[ep], 1);
1073 break;
1074 case (MUSB_HDRC_FIFOSIZE & ~1):
1075 break;
1076 case MUSB_HDRC_FIFOSIZE:
384dce1e 1077 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1078 s->ep[ep].fifosize = value;
1079 break;
942ac052 1080 default:
384dce1e
RV		 1081 TRACE("unknown register 0x%02x", addr);
1082 break;
942ac052
AZ		 1083 };
1084}
1085
1086static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1087{
bc24a225 1088 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1089 uint16_t ret;
1090
1091 switch (addr) {
1092 case MUSB_HDRC_TXMAXP:
1093 return s->ep[ep].maxp[0];
1094 case MUSB_HDRC_TXCSR:
1095 return s->ep[ep].csr[0];
1096 case MUSB_HDRC_RXMAXP:
1097 return s->ep[ep].maxp[1];
1098 case MUSB_HDRC_RXCSR:
1099 ret = s->ep[ep].csr[1];
1100
1101 /* TODO: This and other bits probably depend on
1102 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1103 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1104 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1105
1106 return ret;
1107 case MUSB_HDRC_RXCOUNT:
1108 return s->ep[ep].rxcount;
1109
1110 default:
1111 return musb_ep_readb(s, ep, addr) |
1112 (musb_ep_readb(s, ep, addr | 1) << 8);
1113 };
1114}
1115
1116static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1117{
bc24a225 1118 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1119
1120 switch (addr) {
1121 case MUSB_HDRC_TXMAXP:
1122 s->ep[ep].maxp[0] = value;
1123 break;
1124 case MUSB_HDRC_TXCSR:
1125 if (ep) {
1126 s->ep[ep].csr[0] &= value & 0xa6;
1127 s->ep[ep].csr[0] |= value & 0xff59;
1128 } else {
1129 s->ep[ep].csr[0] &= value & 0x85;
1130 s->ep[ep].csr[0] |= value & 0xf7a;
1131 }
1132
1133 musb_ep_frame_cancel(&s->ep[ep], 0);
1134
1135 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1136 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1137 s->ep[ep].fifolen[0] = 0;
1138 s->ep[ep].fifostart[0] = 0;
1139 if (ep)
1140 s->ep[ep].csr[0] &=
1141 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1142 else
1143 s->ep[ep].csr[0] &=
1144 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1145 }
1146 if (
1147 (ep &&
1148#ifdef CLEAR_NAK
1149 (value & MGC_M_TXCSR_TXPKTRDY) &&
1150 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1151#else
1152 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1153#endif
1154 (!ep &&
1155#ifdef CLEAR_NAK
1156 (value & MGC_M_CSR0_TXPKTRDY) &&
1157 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1158#else
1159 (value & MGC_M_CSR0_TXPKTRDY)))
1160#endif
1161 musb_tx_rdy(s, ep);
1162 if (!ep &&
1163 (value & MGC_M_CSR0_H_REQPKT) &&
1164#ifdef CLEAR_NAK
1165 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1166 MGC_M_CSR0_RXPKTRDY)))
1167#else
1168 !(value & MGC_M_CSR0_RXPKTRDY))
1169#endif
1170 musb_rx_req(s, ep);
1171 break;
1172
1173 case MUSB_HDRC_RXMAXP:
1174 s->ep[ep].maxp[1] = value;
1175 break;
1176 case MUSB_HDRC_RXCSR:
1177 /* (DMA mode only) */
1178 if (
1179 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1180 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1181 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1182 value |= MGC_M_RXCSR_H_REQPKT;
1183
1184 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1185 s->ep[ep].csr[1] |= value & 0xfeb0;
1186
1187 musb_ep_frame_cancel(&s->ep[ep], 1);
1188
1189 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1190 s->ep[ep].fifolen[1] = 0;
1191 s->ep[ep].fifostart[1] = 0;
1192 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1193 /* If double buffering and we have two packets ready, flush
1194 * only the first one and set up the fifo at the second packet. */
1195 }
1196#ifdef CLEAR_NAK
1197 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1198#else
1199 if (value & MGC_M_RXCSR_H_REQPKT)
1200#endif
1201 musb_rx_req(s, ep);
1202 break;
1203 case MUSB_HDRC_RXCOUNT:
1204 s->ep[ep].rxcount = value;
1205 break;
1206
1207 default:
1208 musb_ep_writeb(s, ep, addr, value & 0xff);
1209 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1210 };
1211}
1212
1213/* Generic control */
c227f099 1214static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
942ac052 1215{
bc24a225 1216 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1217 int ep, i;
1218 uint8_t ret;
1219
1220 switch (addr) {
1221 case MUSB_HDRC_FADDR:
1222 return s->faddr;
1223 case MUSB_HDRC_POWER:
1224 return s->power;
1225 case MUSB_HDRC_INTRUSB:
1226 ret = s->intr;
1227 for (i = 0; i < sizeof(ret) * 8; i ++)
1228 if (ret & (1 << i))
1229 musb_intr_set(s, i, 0);
1230 return ret;
1231 case MUSB_HDRC_INTRUSBE:
1232 return s->mask;
1233 case MUSB_HDRC_INDEX:
1234 return s->idx;
1235 case MUSB_HDRC_TESTMODE:
1236 return 0x00;
1237
1238 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1239 return musb_ep_readb(s, s->idx, addr & 0xf);
1240
1241 case MUSB_HDRC_DEVCTL:
1242 return s->devctl;
1243
1244 case MUSB_HDRC_TXFIFOSZ:
1245 case MUSB_HDRC_RXFIFOSZ:
1246 case MUSB_HDRC_VCTRL:
1247 /* TODO */
1248 return 0x00;
1249
1250 case MUSB_HDRC_HWVERS:
1251 return (1 << 10) | 400;
1252
1253 case (MUSB_HDRC_VCTRL | 1):
1254 case (MUSB_HDRC_HWVERS | 1):
1255 case (MUSB_HDRC_DEVCTL | 1):
1256 return 0x00;
1257
1258 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1259 ep = (addr >> 3) & 0xf;
1260 return musb_busctl_readb(s, ep, addr & 0x7);
1261
1262 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1263 ep = (addr >> 4) & 0xf;
1264 return musb_ep_readb(s, ep, addr & 0xf);
1265
384dce1e
RV		 1266 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1267 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1268 return musb_read_fifo(s->ep + ep);
1269
942ac052 1270 default:
384dce1e 1271 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1272 return 0x00;
1273 };
1274}
1275
c227f099 1276static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1277{
bc24a225 1278 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1279 int ep;
1280
1281 switch (addr) {
1282 case MUSB_HDRC_FADDR:
1283 s->faddr = value & 0x7f;
1284 break;
1285 case MUSB_HDRC_POWER:
1286 s->power = (value & 0xef) | (s->power & 0x10);
1287 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1288 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1289 usb_send_msg(s->port.dev, USB_MSG_RESET);
1290 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1291 if ((value & MGC_M_POWER_HSENAB) &&
1292 s->port.dev->speed == USB_SPEED_HIGH)
1293 s->power |= MGC_M_POWER_HSMODE; /* Success */
1294 /* Restart frame counting. */
1295 }
1296 if (value & MGC_M_POWER_SUSPENDM) {
1297 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1298 * is set, also go into low power mode. Frame counting stops. */
1299 /* XXX: Cleared when the interrupt register is read */
1300 }
1301 if (value & MGC_M_POWER_RESUME) {
1302 /* Wait 20ms and signal resuming on the bus. Frame counting
1303 * restarts. */
1304 }
1305 break;
1306 case MUSB_HDRC_INTRUSB:
1307 break;
1308 case MUSB_HDRC_INTRUSBE:
1309 s->mask = value & 0xff;
1310 break;
1311 case MUSB_HDRC_INDEX:
1312 s->idx = value & 0xf;
1313 break;
1314 case MUSB_HDRC_TESTMODE:
1315 break;
1316
1317 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1318 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1319 break;
1320
1321 case MUSB_HDRC_DEVCTL:
1322 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1323 musb_session_update(s,
1324 !!s->port.dev,
1325 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1326
1327 /* It seems this is the only R/W bit in this register? */
1328 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1329 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1330 break;
1331
1332 case MUSB_HDRC_TXFIFOSZ:
1333 case MUSB_HDRC_RXFIFOSZ:
1334 case MUSB_HDRC_VCTRL:
1335 /* TODO */
1336 break;
1337
1338 case (MUSB_HDRC_VCTRL | 1):
1339 case (MUSB_HDRC_DEVCTL | 1):
1340 break;
1341
1342 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1343 ep = (addr >> 3) & 0xf;
1344 musb_busctl_writeb(s, ep, addr & 0x7, value);
1345 break;
1346
1347 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1348 ep = (addr >> 4) & 0xf;
1349 musb_ep_writeb(s, ep, addr & 0xf, value);
1350 break;
1351
384dce1e
RV		 1352 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1353 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1354 musb_write_fifo(s->ep + ep, value & 0xff);
1355 break;
1356
942ac052 1357 default:
384dce1e
RV		 1358 TRACE("unknown register 0x%02x", (int) addr);
1359 break;
942ac052
AZ		 1360 };
1361}
1362
c227f099 1363static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
942ac052 1364{
bc24a225 1365 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1366 int ep, i;
1367 uint16_t ret;
1368
1369 switch (addr) {
1370 case MUSB_HDRC_INTRTX:
1371 ret = s->tx_intr;
1372 /* Auto clear */
1373 for (i = 0; i < sizeof(ret) * 8; i ++)
1374 if (ret & (1 << i))
1375 musb_tx_intr_set(s, i, 0);
1376 return ret;
1377 case MUSB_HDRC_INTRRX:
1378 ret = s->rx_intr;
1379 /* Auto clear */
1380 for (i = 0; i < sizeof(ret) * 8; i ++)
1381 if (ret & (1 << i))
1382 musb_rx_intr_set(s, i, 0);
1383 return ret;
1384 case MUSB_HDRC_INTRTXE:
1385 return s->tx_mask;
1386 case MUSB_HDRC_INTRRXE:
1387 return s->rx_mask;
1388
1389 case MUSB_HDRC_FRAME:
1390 /* TODO */
1391 return 0x0000;
1392 case MUSB_HDRC_TXFIFOADDR:
1393 return s->ep[s->idx].fifoaddr[0];
1394 case MUSB_HDRC_RXFIFOADDR:
1395 return s->ep[s->idx].fifoaddr[1];
1396
1397 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1398 return musb_ep_readh(s, s->idx, addr & 0xf);
1399
1400 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1401 ep = (addr >> 3) & 0xf;
1402 return musb_busctl_readh(s, ep, addr & 0x7);
1403
1404 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1405 ep = (addr >> 4) & 0xf;
1406 return musb_ep_readh(s, ep, addr & 0xf);
1407
384dce1e
RV		 1408 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1409 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1410 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1411
942ac052
AZ		 1412 default:
1413 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1414 };
1415}
1416
c227f099 1417static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1418{
bc24a225 1419 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1420 int ep;
1421
1422 switch (addr) {
1423 case MUSB_HDRC_INTRTXE:
1424 s->tx_mask = value;
1425 /* XXX: the masks seem to apply on the raising edge like with
1426 * edge-triggered interrupts, thus no need to update. I may be
1427 * wrong though. */
1428 break;
1429 case MUSB_HDRC_INTRRXE:
1430 s->rx_mask = value;
1431 break;
1432
1433 case MUSB_HDRC_FRAME:
1434 /* TODO */
1435 break;
1436 case MUSB_HDRC_TXFIFOADDR:
1437 s->ep[s->idx].fifoaddr[0] = value;
1438 s->ep[s->idx].buf[0] =
384dce1e 1439 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1440 break;
1441 case MUSB_HDRC_RXFIFOADDR:
1442 s->ep[s->idx].fifoaddr[1] = value;
1443 s->ep[s->idx].buf[1] =
384dce1e 1444 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1445 break;
1446
1447 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1448 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1449 break;
1450
1451 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1452 ep = (addr >> 3) & 0xf;
1453 musb_busctl_writeh(s, ep, addr & 0x7, value);
1454 break;
1455
1456 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1457 ep = (addr >> 4) & 0xf;
1458 musb_ep_writeh(s, ep, addr & 0xf, value);
1459 break;
1460
384dce1e
RV		 1461 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1462 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1463 musb_write_fifo(s->ep + ep, value & 0xff);
1464 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1465 break;
1466
942ac052
AZ		 1467 default:
1468 musb_writeb(s, addr, value & 0xff);
1469 musb_writeb(s, addr | 1, value >> 8);
1470 };
1471}
1472
c227f099 1473static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
942ac052 1474{
bc24a225 1475 MUSBState *s = (MUSBState *) opaque;
384dce1e 1476 int ep;
942ac052
AZ		 1477
1478 switch (addr) {
1479 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1480 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1481 return ( musb_read_fifo(s->ep + ep) |
1482 musb_read_fifo(s->ep + ep) << 8 |
1483 musb_read_fifo(s->ep + ep) << 16 |
1484 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1485 default:
384dce1e 1486 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1487 return 0x00000000;
1488 };
1489}
1490
c227f099 1491static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1492{
bc24a225 1493 MUSBState *s = (MUSBState *) opaque;
384dce1e 1494 int ep;
942ac052
AZ		 1495
1496 switch (addr) {
1497 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1498 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1499 musb_write_fifo(s->ep + ep, value & 0xff);
1500 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1501 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1502 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1503 break;
942ac052 1504 default:
384dce1e
RV		 1505 TRACE("unknown register 0x%02x", (int) addr);
1506 break;
942ac052
AZ		 1507 };
1508}
1509
d60efc6b 1510CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1511 musb_readb,
1512 musb_readh,
1513 musb_readw,
1514};
1515
d60efc6b 1516CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1517 musb_writeb,
1518 musb_writeh,
1519 musb_writew,
1520};
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