[qemu.git] / hw / m48t59.c

/*
 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
 *
 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "nvram.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "sysbus.h"

//#define DEBUG_NVRAM

#if defined(DEBUG_NVRAM)
#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
#else
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
#endif

/*
 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
 * alarm and a watchdog timer and related control registers. In the
 * PPC platform there is also a nvram lock function.
 */
struct m48t59_t {
    SysBusDevice busdev;
    /* Model parameters */
    uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
    /* Hardware parameters */
    qemu_irq IRQ;
    uint32_t io_base;
    uint32_t size;
    /* RTC management */
    time_t   time_offset;
    time_t   stop_time;
    /* Alarm & watchdog */
    struct tm alarm;
    struct QEMUTimer *alrm_timer;
    struct QEMUTimer *wd_timer;
    /* NVRAM storage */
    uint8_t  lock;
    uint16_t addr;
    uint8_t *buffer;
};

/* Fake timer functions */
/* Generic helpers for BCD */
static inline uint8_t toBCD (uint8_t value)
{
    return (((value / 10) % 10) << 4) | (value % 10);
}

static inline uint8_t fromBCD (uint8_t BCD)
{
    return ((BCD >> 4) * 10) + (BCD & 0x0F);
}

/* Alarm management */
static void alarm_cb (void *opaque)
{
    struct tm tm;
    uint64_t next_time;
    m48t59_t *NVRAM = opaque;

    qemu_set_irq(NVRAM->IRQ, 1);
    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a month */
        qemu_get_timedate(&tm, NVRAM->time_offset);
        tm.tm_mon++;
        if (tm.tm_mon == 13) {
            tm.tm_mon = 1;
            tm.tm_year++;
        }
        next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a day */
        next_time = 24 * 60 * 60;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once an hour */
        next_time = 60 * 60;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a minute */
        next_time = 60;
    } else {
        /* Repeat once a second */
        next_time = 1;
    }
    qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
                    next_time * 1000);
    qemu_set_irq(NVRAM->IRQ, 0);
}

static void set_alarm (m48t59_t *NVRAM)
{
    int diff;
    if (NVRAM->alrm_timer != NULL) {
        qemu_del_timer(NVRAM->alrm_timer);
        diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
        if (diff > 0)
            qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
    }
}

/* RTC management helpers */
static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
{
    qemu_get_timedate(tm, NVRAM->time_offset);
}

static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
    NVRAM->time_offset = qemu_timedate_diff(tm);
    set_alarm(NVRAM);
}

/* Watchdog management */
static void watchdog_cb (void *opaque)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->buffer[0x1FF0] |= 0x80;
    if (NVRAM->buffer[0x1FF7] & 0x80) {
	NVRAM->buffer[0x1FF7] = 0x00;
	NVRAM->buffer[0x1FFC] &= ~0x40;
        /* May it be a hw CPU Reset instead ? */
        qemu_system_reset_request();
    } else {
	qemu_set_irq(NVRAM->IRQ, 1);
	qemu_set_irq(NVRAM->IRQ, 0);
    }
}

static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
    uint64_t interval; /* in 1/16 seconds */

    NVRAM->buffer[0x1FF0] &= ~0x80;
    if (NVRAM->wd_timer != NULL) {
        qemu_del_timer(NVRAM->wd_timer);
        if (value != 0) {
            interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
            qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
                           ((interval * 1000) >> 4));
        }
    }
}

/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    int tmp;

    if (addr > 0x1FF8 && addr < 0x2000)
	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x7f8) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_write;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register : read-only */
        break;
    case 0x1FF1:
        /* unused */
        break;
    case 0x1FF2:
        /* alarm seconds */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            NVRAM->alarm.tm_sec = tmp;
            NVRAM->buffer[0x1FF2] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF3:
        /* alarm minutes */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            NVRAM->alarm.tm_min = tmp;
            NVRAM->buffer[0x1FF3] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF4:
        /* alarm hours */
        tmp = fromBCD(val & 0x3F);
        if (tmp >= 0 && tmp <= 23) {
            NVRAM->alarm.tm_hour = tmp;
            NVRAM->buffer[0x1FF4] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF5:
        /* alarm date */
        tmp = fromBCD(val & 0x1F);
        if (tmp != 0) {
            NVRAM->alarm.tm_mday = tmp;
            NVRAM->buffer[0x1FF5] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF6:
        /* interrupts */
        NVRAM->buffer[0x1FF6] = val;
        break;
    case 0x1FF7:
        /* watchdog */
        NVRAM->buffer[0x1FF7] = val;
        set_up_watchdog(NVRAM, val);
        break;
    case 0x1FF8:
    case 0x07F8:
        /* control */
       NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
        break;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_sec = tmp;
	    set_time(NVRAM, &tm);
	}
        if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
	    if (val & 0x80) {
		NVRAM->stop_time = time(NULL);
	    } else {
		NVRAM->time_offset += NVRAM->stop_time - time(NULL);
		NVRAM->stop_time = 0;
	    }
	}
        NVRAM->buffer[addr] = val & 0x80;
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_min = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
	tmp = fromBCD(val & 0x3F);
	if (tmp >= 0 && tmp <= 23) {
	    get_time(NVRAM, &tm);
	    tm.tm_hour = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
	tmp = fromBCD(val & 0x07);
	get_time(NVRAM, &tm);
	tm.tm_wday = tmp;
	set_time(NVRAM, &tm);
        NVRAM->buffer[addr] = val & 0x40;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
	tmp = fromBCD(val & 0x1F);
	if (tmp != 0) {
	    get_time(NVRAM, &tm);
	    tm.tm_mday = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
	tmp = fromBCD(val & 0x1F);
	if (tmp >= 1 && tmp <= 12) {
	    get_time(NVRAM, &tm);
	    tm.tm_mon = tmp - 1;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
	tmp = fromBCD(val);
	if (tmp >= 0 && tmp <= 99) {
	    get_time(NVRAM, &tm);
            if (NVRAM->type == 8)
                tm.tm_year = fromBCD(val) + 68; // Base year is 1968
            else
                tm.tm_year = fromBCD(val);
	    set_time(NVRAM, &tm);
	}
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_write:
        if (addr < NVRAM->size) {
            NVRAM->buffer[addr] = val & 0xFF;
	}
        break;
    }
}

uint32_t m48t59_read (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    uint32_t retval = 0xFF;

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x078f) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_read;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register */
	goto do_read;
    case 0x1FF1:
        /* unused */
	retval = 0;
        break;
    case 0x1FF2:
        /* alarm seconds */
	goto do_read;
    case 0x1FF3:
        /* alarm minutes */
	goto do_read;
    case 0x1FF4:
        /* alarm hours */
	goto do_read;
    case 0x1FF5:
        /* alarm date */
	goto do_read;
    case 0x1FF6:
        /* interrupts */
	goto do_read;
    case 0x1FF7:
	/* A read resets the watchdog */
	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	goto do_read;
    case 0x1FF8:
    case 0x07F8:
        /* control */
	goto do_read;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
        get_time(NVRAM, &tm);
        retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_min);
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_hour);
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
        get_time(NVRAM, &tm);
        retval = NVRAM->buffer[addr] | tm.tm_wday;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mday);
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mon + 1);
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
        get_time(NVRAM, &tm);
        if (NVRAM->type == 8)
            retval = toBCD(tm.tm_year - 68); // Base year is 1968
        else
            retval = toBCD(tm.tm_year);
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_read:
        if (addr < NVRAM->size) {
            retval = NVRAM->buffer[addr];
	}
        break;
    }
    if (addr > 0x1FF9 && addr < 0x2000)
       NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

void m48t59_set_addr (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->addr = addr;
}

void m48t59_toggle_lock (void *opaque, int lock)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->lock ^= 1 << lock;
}

/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->io_base;
    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
    switch (addr) {
    case 0:
        NVRAM->addr &= ~0x00FF;
        NVRAM->addr |= val;
        break;
    case 1:
        NVRAM->addr &= ~0xFF00;
        NVRAM->addr |= val << 8;
        break;
    case 3:
        m48t59_write(NVRAM, val, NVRAM->addr);
        NVRAM->addr = 0x0000;
        break;
    default:
        break;
    }
}

static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->io_base;
    switch (addr) {
    case 3:
        retval = m48t59_read(NVRAM, NVRAM->addr);
        break;
    default:
        retval = -1;
        break;
    }
    NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, value & 0xff);
}

static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 1, value & 0xff);
}

static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 3, value & 0xff);
}

static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    retval = m48t59_read(NVRAM, addr);
    return retval;
}

static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 8;
    retval |= m48t59_read(NVRAM, addr + 1);
    return retval;
}

static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    retval = m48t59_read(NVRAM, addr) << 24;
    retval |= m48t59_read(NVRAM, addr + 1) << 16;
    retval |= m48t59_read(NVRAM, addr + 2) << 8;
    retval |= m48t59_read(NVRAM, addr + 3);
    return retval;
}

static CPUWriteMemoryFunc * const nvram_write[] = {
    &nvram_writeb,
    &nvram_writew,
    &nvram_writel,
};

static CPUReadMemoryFunc * const nvram_read[] = {
    &nvram_readb,
    &nvram_readw,
    &nvram_readl,
};

static void m48t59_save(QEMUFile *f, void *opaque)
{
    m48t59_t *s = opaque;

    qemu_put_8s(f, &s->lock);
    qemu_put_be16s(f, &s->addr);
    qemu_put_buffer(f, s->buffer, s->size);
}

static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
    m48t59_t *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_8s(f, &s->lock);
    qemu_get_be16s(f, &s->addr);
    qemu_get_buffer(f, s->buffer, s->size);

    return 0;
}

static void m48t59_reset(void *opaque)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->addr = 0;
    NVRAM->lock = 0;
    if (NVRAM->alrm_timer != NULL)
        qemu_del_timer(NVRAM->alrm_timer);

    if (NVRAM->wd_timer != NULL)
        qemu_del_timer(NVRAM->wd_timer);
}

/* Initialisation routine */
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
                       uint32_t io_base, uint16_t size,
                       int type)
{
    DeviceState *dev;
    SysBusDevice *s;
    m48t59_t *d;

    dev = qdev_create(NULL, "m48t59");
    qdev_prop_set_uint32(dev, "type", type);
    qdev_prop_set_uint32(dev, "size", size);
    qdev_prop_set_uint32(dev, "io_base", io_base);
    qdev_init(dev);
    s = sysbus_from_qdev(dev);
    sysbus_connect_irq(s, 0, IRQ);
    if (io_base != 0) {
        register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
    }
    if (mem_base != 0) {
        sysbus_mmio_map(s, 0, mem_base);
    }

    d = FROM_SYSBUS(m48t59_t, s);

    return d;
}

static int m48t59_init1(SysBusDevice *dev)
{
    m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);
    int mem_index;

    s->buffer = qemu_mallocz(s->size);
    sysbus_init_irq(dev, &s->IRQ);

    mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
    sysbus_init_mmio(dev, s->size, mem_index);

    if (s->type == 59) {
        s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
        s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
    }
    qemu_get_timedate(&s->alarm, 0);

    qemu_register_reset(m48t59_reset, s);
    register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
    return 0;
}

static SysBusDeviceInfo m48t59_info = {
    .init = m48t59_init1,
    .qdev.name  = "m48t59",
    .qdev.size  = sizeof(m48t59_t),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("size",    m48t59_t, size,    -1),
        DEFINE_PROP_UINT32("type",    m48t59_t, type,    -1),
        DEFINE_PROP_HEX32( "io_base", m48t59_t, io_base,  0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void m48t59_register_devices(void)
{
    sysbus_register_withprop(&m48t59_info);
}

device_init(m48t59_register_devices)
Commit	Line	Data
a541f297	1	/*
819385c5	2	* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
5fafdf24	3	*
3ccacc4a	4	* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5fafdf24	5	*
a541f297 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "nvram.h"
87ecb68b PB	26	#include "qemu-timer.h"
87ecb68b PB	27	#include "sysemu.h"
d27cf0ae	28	#include "sysbus.h"
a541f297	29
13ab5daa	30	//#define DEBUG_NVRAM
a541f297	31
13ab5daa	32	#if defined(DEBUG_NVRAM)
001faf32	33	#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
a541f297	34	#else
001faf32	35	#define NVRAM_PRINTF(fmt, ...) do { } while (0)
a541f297 FB	36	#endif
a541f297 FB	37
819385c5	38	/*
4aed2c33	39	* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
819385c5 FB	40	* alarm and a watchdog timer and related control registers. In the
	41	* PPC platform there is also a nvram lock function.
	42	*/
c5df018e	43	struct m48t59_t {
d27cf0ae	44	SysBusDevice busdev;
819385c5	45	/* Model parameters */
ee6847d1	46	uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
a541f297	47	/* Hardware parameters */
d537cf6c	48	qemu_irq IRQ;
a541f297	49	uint32_t io_base;
ee6847d1	50	uint32_t size;
a541f297 FB	51	/* RTC management */
	52	time_t time_offset;
	53	time_t stop_time;
	54	/* Alarm & watchdog */
f6503059	55	struct tm alarm;
a541f297 FB	56	struct QEMUTimer *alrm_timer;
	57	struct QEMUTimer *wd_timer;
	58	/* NVRAM storage */
13ab5daa	59	uint8_t lock;
a541f297 FB	60	uint16_t addr;
a541f297 FB	61	uint8_t *buffer;
c5df018e	62	};
a541f297 FB	63
	64	/* Fake timer functions */
	65	/* Generic helpers for BCD */
	66	static inline uint8_t toBCD (uint8_t value)
	67	{
	68	return (((value / 10) % 10) << 4) \| (value % 10);
	69	}
	70
	71	static inline uint8_t fromBCD (uint8_t BCD)
	72	{
	73	return ((BCD >> 4) * 10) + (BCD & 0x0F);
	74	}
	75
a541f297 FB	76	/* Alarm management */
	77	static void alarm_cb (void *opaque)
	78	{
f6503059	79	struct tm tm;
a541f297 FB	80	uint64_t next_time;
	81	m48t59_t *NVRAM = opaque;
	82
d537cf6c	83	qemu_set_irq(NVRAM->IRQ, 1);
5fafdf24	84	if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
a541f297 FB	85	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	86	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	87	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	88	/* Repeat once a month */
	89	qemu_get_timedate(&tm, NVRAM->time_offset);
	90	tm.tm_mon++;
	91	if (tm.tm_mon == 13) {
	92	tm.tm_mon = 1;
	93	tm.tm_year++;
	94	}
	95	next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
a541f297 FB	96	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	97	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	98	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	99	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	100	/* Repeat once a day */
f6503059 AZ	101	next_time = 24 * 60 * 60;
a541f297 FB	102	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	103	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	104	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	105	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	106	/* Repeat once an hour */
f6503059 AZ	107	next_time = 60 * 60;
a541f297 FB	108	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	109	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	110	(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	111	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	112	/* Repeat once a minute */
f6503059 AZ	113	next_time = 60;
a541f297	114	} else {
f6503059 AZ	115	/* Repeat once a second */
f6503059 AZ	116	next_time = 1;
a541f297	117	}
f6503059 AZ	118	qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
f6503059 AZ	119	next_time * 1000);
d537cf6c	120	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	121	}
a541f297 FB	122
f6503059 AZ	123	static void set_alarm (m48t59_t *NVRAM)
	124	{
	125	int diff;
	126	if (NVRAM->alrm_timer != NULL) {
	127	qemu_del_timer(NVRAM->alrm_timer);
	128	diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
	129	if (diff > 0)
	130	qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
	131	}
	132	}
a541f297	133
f6503059 AZ	134	/* RTC management helpers */
f6503059 AZ	135	static inline void get_time (m48t59_t NVRAM, struct tm tm)
a541f297	136	{
f6503059	137	qemu_get_timedate(tm, NVRAM->time_offset);
a541f297 FB	138	}
a541f297 FB	139
f6503059	140	static void set_time (m48t59_t NVRAM, struct tm tm)
a541f297	141	{
f6503059 AZ	142	NVRAM->time_offset = qemu_timedate_diff(tm);
f6503059 AZ	143	set_alarm(NVRAM);
a541f297 FB	144	}
	145
	146	/* Watchdog management */
	147	static void watchdog_cb (void *opaque)
	148	{
	149	m48t59_t *NVRAM = opaque;
	150
	151	NVRAM->buffer[0x1FF0] \|= 0x80;
	152	if (NVRAM->buffer[0x1FF7] & 0x80) {
	153	NVRAM->buffer[0x1FF7] = 0x00;
	154	NVRAM->buffer[0x1FFC] &= ~0x40;
13ab5daa	155	/* May it be a hw CPU Reset instead ? */
d7d02e3c	156	qemu_system_reset_request();
a541f297	157	} else {
d537cf6c PB	158	qemu_set_irq(NVRAM->IRQ, 1);
d537cf6c PB	159	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	160	}
	161	}
	162
	163	static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
	164	{
	165	uint64_t interval; /* in 1/16 seconds */
	166
868d585a	167	NVRAM->buffer[0x1FF0] &= ~0x80;
a541f297 FB	168	if (NVRAM->wd_timer != NULL) {
a541f297 FB	169	qemu_del_timer(NVRAM->wd_timer);
868d585a JM	170	if (value != 0) {
	171	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
	172	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
	173	((interval * 1000) >> 4));
	174	}
a541f297 FB	175	}
	176	}
	177
	178	/* Direct access to NVRAM */
897b4c6c	179	void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
a541f297	180	{
897b4c6c	181	m48t59_t *NVRAM = opaque;
a541f297 FB	182	struct tm tm;
	183	int tmp;
	184
819385c5 FB	185	if (addr > 0x1FF8 && addr < 0x2000)
819385c5 FB	186	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
4aed2c33 BS	187
	188	/* check for NVRAM access */
	189	if ((NVRAM->type == 2 && addr < 0x7f8) \|\|
	190	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	191	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	192	goto do_write;
4aed2c33 BS	193
4aed2c33 BS	194	/* TOD access */
819385c5	195	switch (addr) {
a541f297 FB	196	case 0x1FF0:
	197	/* flags register : read-only */
	198	break;
	199	case 0x1FF1:
	200	/* unused */
	201	break;
	202	case 0x1FF2:
	203	/* alarm seconds */
819385c5 FB	204	tmp = fromBCD(val & 0x7F);
819385c5 FB	205	if (tmp >= 0 && tmp <= 59) {
f6503059	206	NVRAM->alarm.tm_sec = tmp;
819385c5	207	NVRAM->buffer[0x1FF2] = val;
f6503059	208	set_alarm(NVRAM);
819385c5	209	}
a541f297 FB	210	break;
	211	case 0x1FF3:
	212	/* alarm minutes */
819385c5 FB	213	tmp = fromBCD(val & 0x7F);
819385c5 FB	214	if (tmp >= 0 && tmp <= 59) {
f6503059	215	NVRAM->alarm.tm_min = tmp;
819385c5	216	NVRAM->buffer[0x1FF3] = val;
f6503059	217	set_alarm(NVRAM);
819385c5	218	}
a541f297 FB	219	break;
	220	case 0x1FF4:
	221	/* alarm hours */
819385c5 FB	222	tmp = fromBCD(val & 0x3F);
819385c5 FB	223	if (tmp >= 0 && tmp <= 23) {
f6503059	224	NVRAM->alarm.tm_hour = tmp;
819385c5	225	NVRAM->buffer[0x1FF4] = val;
f6503059	226	set_alarm(NVRAM);
819385c5	227	}
a541f297 FB	228	break;
	229	case 0x1FF5:
	230	/* alarm date */
819385c5 FB	231	tmp = fromBCD(val & 0x1F);
819385c5 FB	232	if (tmp != 0) {
f6503059	233	NVRAM->alarm.tm_mday = tmp;
819385c5	234	NVRAM->buffer[0x1FF5] = val;
f6503059	235	set_alarm(NVRAM);
819385c5	236	}
a541f297 FB	237	break;
	238	case 0x1FF6:
	239	/* interrupts */
819385c5	240	NVRAM->buffer[0x1FF6] = val;
a541f297 FB	241	break;
	242	case 0x1FF7:
	243	/* watchdog */
819385c5 FB	244	NVRAM->buffer[0x1FF7] = val;
819385c5 FB	245	set_up_watchdog(NVRAM, val);
a541f297 FB	246	break;
a541f297 FB	247	case 0x1FF8:
4aed2c33	248	case 0x07F8:
a541f297	249	/* control */
4aed2c33	250	NVRAM->buffer[addr] = (val & ~0xA0) \| 0x90;
a541f297 FB	251	break;
a541f297 FB	252	case 0x1FF9:
4aed2c33	253	case 0x07F9:
a541f297 FB	254	/* seconds (BCD) */
	255	tmp = fromBCD(val & 0x7F);
	256	if (tmp >= 0 && tmp <= 59) {
	257	get_time(NVRAM, &tm);
	258	tm.tm_sec = tmp;
	259	set_time(NVRAM, &tm);
	260	}
f6503059	261	if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
a541f297 FB	262	if (val & 0x80) {
	263	NVRAM->stop_time = time(NULL);
	264	} else {
	265	NVRAM->time_offset += NVRAM->stop_time - time(NULL);
	266	NVRAM->stop_time = 0;
	267	}
	268	}
f6503059	269	NVRAM->buffer[addr] = val & 0x80;
a541f297 FB	270	break;
a541f297 FB	271	case 0x1FFA:
4aed2c33	272	case 0x07FA:
a541f297 FB	273	/* minutes (BCD) */
	274	tmp = fromBCD(val & 0x7F);
	275	if (tmp >= 0 && tmp <= 59) {
	276	get_time(NVRAM, &tm);
	277	tm.tm_min = tmp;
	278	set_time(NVRAM, &tm);
	279	}
	280	break;
	281	case 0x1FFB:
4aed2c33	282	case 0x07FB:
a541f297 FB	283	/* hours (BCD) */
	284	tmp = fromBCD(val & 0x3F);
	285	if (tmp >= 0 && tmp <= 23) {
	286	get_time(NVRAM, &tm);
	287	tm.tm_hour = tmp;
	288	set_time(NVRAM, &tm);
	289	}
	290	break;
	291	case 0x1FFC:
4aed2c33	292	case 0x07FC:
a541f297 FB	293	/* day of the week / century */
	294	tmp = fromBCD(val & 0x07);
	295	get_time(NVRAM, &tm);
	296	tm.tm_wday = tmp;
	297	set_time(NVRAM, &tm);
4aed2c33	298	NVRAM->buffer[addr] = val & 0x40;
a541f297 FB	299	break;
a541f297 FB	300	case 0x1FFD:
4aed2c33	301	case 0x07FD:
a541f297 FB	302	/* date */
	303	tmp = fromBCD(val & 0x1F);
	304	if (tmp != 0) {
	305	get_time(NVRAM, &tm);
	306	tm.tm_mday = tmp;
	307	set_time(NVRAM, &tm);
	308	}
	309	break;
	310	case 0x1FFE:
4aed2c33	311	case 0x07FE:
a541f297 FB	312	/* month */
	313	tmp = fromBCD(val & 0x1F);
	314	if (tmp >= 1 && tmp <= 12) {
	315	get_time(NVRAM, &tm);
	316	tm.tm_mon = tmp - 1;
	317	set_time(NVRAM, &tm);
	318	}
	319	break;
	320	case 0x1FFF:
4aed2c33	321	case 0x07FF:
a541f297 FB	322	/* year */
	323	tmp = fromBCD(val);
	324	if (tmp >= 0 && tmp <= 99) {
	325	get_time(NVRAM, &tm);
180b700d FB	326	if (NVRAM->type == 8)
	327	tm.tm_year = fromBCD(val) + 68; // Base year is 1968
	328	else
	329	tm.tm_year = fromBCD(val);
a541f297 FB	330	set_time(NVRAM, &tm);
	331	}
	332	break;
	333	default:
13ab5daa	334	/* Check lock registers state */
819385c5	335	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	336	break;
819385c5	337	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	338	break;
819385c5 FB	339	do_write:
	340	if (addr < NVRAM->size) {
	341	NVRAM->buffer[addr] = val & 0xFF;
a541f297 FB	342	}
	343	break;
	344	}
	345	}
	346
897b4c6c	347	uint32_t m48t59_read (void *opaque, uint32_t addr)
a541f297	348	{
897b4c6c	349	m48t59_t *NVRAM = opaque;
a541f297 FB	350	struct tm tm;
	351	uint32_t retval = 0xFF;
	352
4aed2c33 BS	353	/* check for NVRAM access */
	354	if ((NVRAM->type == 2 && addr < 0x078f) \|\|
	355	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	356	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	357	goto do_read;
4aed2c33 BS	358
4aed2c33 BS	359	/* TOD access */
819385c5	360	switch (addr) {
a541f297 FB	361	case 0x1FF0:
	362	/* flags register */
	363	goto do_read;
	364	case 0x1FF1:
	365	/* unused */
	366	retval = 0;
	367	break;
	368	case 0x1FF2:
	369	/* alarm seconds */
	370	goto do_read;
	371	case 0x1FF3:
	372	/* alarm minutes */
	373	goto do_read;
	374	case 0x1FF4:
	375	/* alarm hours */
	376	goto do_read;
	377	case 0x1FF5:
	378	/* alarm date */
	379	goto do_read;
	380	case 0x1FF6:
	381	/* interrupts */
	382	goto do_read;
	383	case 0x1FF7:
	384	/* A read resets the watchdog */
	385	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	386	goto do_read;
	387	case 0x1FF8:
4aed2c33	388	case 0x07F8:
a541f297 FB	389	/* control */
	390	goto do_read;
	391	case 0x1FF9:
4aed2c33	392	case 0x07F9:
a541f297 FB	393	/* seconds (BCD) */
a541f297 FB	394	get_time(NVRAM, &tm);
4aed2c33	395	retval = (NVRAM->buffer[addr] & 0x80) \| toBCD(tm.tm_sec);
a541f297 FB	396	break;
a541f297 FB	397	case 0x1FFA:
4aed2c33	398	case 0x07FA:
a541f297 FB	399	/* minutes (BCD) */
	400	get_time(NVRAM, &tm);
	401	retval = toBCD(tm.tm_min);
	402	break;
	403	case 0x1FFB:
4aed2c33	404	case 0x07FB:
a541f297 FB	405	/* hours (BCD) */
	406	get_time(NVRAM, &tm);
	407	retval = toBCD(tm.tm_hour);
	408	break;
	409	case 0x1FFC:
4aed2c33	410	case 0x07FC:
a541f297 FB	411	/* day of the week / century */
a541f297 FB	412	get_time(NVRAM, &tm);
4aed2c33	413	retval = NVRAM->buffer[addr] \| tm.tm_wday;
a541f297 FB	414	break;
a541f297 FB	415	case 0x1FFD:
4aed2c33	416	case 0x07FD:
a541f297 FB	417	/* date */
	418	get_time(NVRAM, &tm);
	419	retval = toBCD(tm.tm_mday);
	420	break;
	421	case 0x1FFE:
4aed2c33	422	case 0x07FE:
a541f297 FB	423	/* month */
	424	get_time(NVRAM, &tm);
	425	retval = toBCD(tm.tm_mon + 1);
	426	break;
	427	case 0x1FFF:
4aed2c33	428	case 0x07FF:
a541f297 FB	429	/* year */
a541f297 FB	430	get_time(NVRAM, &tm);
5fafdf24	431	if (NVRAM->type == 8)
180b700d FB	432	retval = toBCD(tm.tm_year - 68); // Base year is 1968
	433	else
	434	retval = toBCD(tm.tm_year);
a541f297 FB	435	break;
a541f297 FB	436	default:
13ab5daa	437	/* Check lock registers state */
819385c5	438	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	439	break;
819385c5	440	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	441	break;
819385c5 FB	442	do_read:
	443	if (addr < NVRAM->size) {
	444	retval = NVRAM->buffer[addr];
a541f297 FB	445	}
	446	break;
	447	}
819385c5	448	if (addr > 0x1FF9 && addr < 0x2000)
9ed1e667	449	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297 FB	450
	451	return retval;
	452	}
	453
897b4c6c	454	void m48t59_set_addr (void *opaque, uint32_t addr)
a541f297	455	{
897b4c6c JM	456	m48t59_t *NVRAM = opaque;
897b4c6c JM	457
a541f297 FB	458	NVRAM->addr = addr;
	459	}
	460
897b4c6c	461	void m48t59_toggle_lock (void *opaque, int lock)
13ab5daa	462	{
897b4c6c JM	463	m48t59_t *NVRAM = opaque;
897b4c6c JM	464
13ab5daa FB	465	NVRAM->lock ^= 1 << lock;
	466	}
	467
a541f297 FB	468	/* IO access to NVRAM */
	469	static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
	470	{
	471	m48t59_t *NVRAM = opaque;
	472
	473	addr -= NVRAM->io_base;
9ed1e667	474	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
a541f297 FB	475	switch (addr) {
	476	case 0:
	477	NVRAM->addr &= ~0x00FF;
	478	NVRAM->addr \|= val;
	479	break;
	480	case 1:
	481	NVRAM->addr &= ~0xFF00;
	482	NVRAM->addr \|= val << 8;
	483	break;
	484	case 3:
819385c5	485	m48t59_write(NVRAM, val, NVRAM->addr);
a541f297 FB	486	NVRAM->addr = 0x0000;
	487	break;
	488	default:
	489	break;
	490	}
	491	}
	492
	493	static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
	494	{
	495	m48t59_t *NVRAM = opaque;
13ab5daa	496	uint32_t retval;
a541f297	497
13ab5daa FB	498	addr -= NVRAM->io_base;
	499	switch (addr) {
	500	case 3:
819385c5	501	retval = m48t59_read(NVRAM, NVRAM->addr);
13ab5daa FB	502	break;
	503	default:
	504	retval = -1;
	505	break;
	506	}
9ed1e667	507	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297	508
13ab5daa	509	return retval;
a541f297 FB	510	}
a541f297 FB	511
e1bb04f7 FB	512	static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	513	{
	514	m48t59_t *NVRAM = opaque;
3b46e624	515
819385c5	516	m48t59_write(NVRAM, addr, value & 0xff);
e1bb04f7 FB	517	}
	518
	519	static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	520	{
	521	m48t59_t *NVRAM = opaque;
3b46e624	522
819385c5 FB	523	m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
819385c5 FB	524	m48t59_write(NVRAM, addr + 1, value & 0xff);
e1bb04f7 FB	525	}
	526
	527	static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	528	{
	529	m48t59_t *NVRAM = opaque;
3b46e624	530
819385c5 FB	531	m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
	532	m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
	533	m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
	534	m48t59_write(NVRAM, addr + 3, value & 0xff);
e1bb04f7 FB	535	}
	536
	537	static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
	538	{
	539	m48t59_t *NVRAM = opaque;
819385c5	540	uint32_t retval;
3b46e624	541
819385c5	542	retval = m48t59_read(NVRAM, addr);
e1bb04f7 FB	543	return retval;
	544	}
	545
	546	static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
	547	{
	548	m48t59_t *NVRAM = opaque;
819385c5	549	uint32_t retval;
3b46e624	550
819385c5 FB	551	retval = m48t59_read(NVRAM, addr) << 8;
819385c5 FB	552	retval \|= m48t59_read(NVRAM, addr + 1);
e1bb04f7 FB	553	return retval;
	554	}
	555
	556	static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
	557	{
	558	m48t59_t *NVRAM = opaque;
819385c5	559	uint32_t retval;
e1bb04f7	560
819385c5 FB	561	retval = m48t59_read(NVRAM, addr) << 24;
	562	retval \|= m48t59_read(NVRAM, addr + 1) << 16;
	563	retval \|= m48t59_read(NVRAM, addr + 2) << 8;
	564	retval \|= m48t59_read(NVRAM, addr + 3);
e1bb04f7 FB	565	return retval;
	566	}
	567
d60efc6b	568	static CPUWriteMemoryFunc * const nvram_write[] = {
e1bb04f7 FB	569	&nvram_writeb,
	570	&nvram_writew,
	571	&nvram_writel,
	572	};
	573
d60efc6b	574	static CPUReadMemoryFunc * const nvram_read[] = {
e1bb04f7 FB	575	&nvram_readb,
	576	&nvram_readw,
	577	&nvram_readl,
	578	};
819385c5	579
3ccacc4a BS	580	static void m48t59_save(QEMUFile f, void opaque)
	581	{
	582	m48t59_t *s = opaque;
	583
	584	qemu_put_8s(f, &s->lock);
	585	qemu_put_be16s(f, &s->addr);
	586	qemu_put_buffer(f, s->buffer, s->size);
	587	}
	588
	589	static int m48t59_load(QEMUFile f, void opaque, int version_id)
	590	{
	591	m48t59_t *s = opaque;
	592
	593	if (version_id != 1)
	594	return -EINVAL;
	595
	596	qemu_get_8s(f, &s->lock);
	597	qemu_get_be16s(f, &s->addr);
	598	qemu_get_buffer(f, s->buffer, s->size);
	599
	600	return 0;
	601	}
	602
	603	static void m48t59_reset(void *opaque)
	604	{
	605	m48t59_t *NVRAM = opaque;
	606
6e6b7363 BS	607	NVRAM->addr = 0;
6e6b7363 BS	608	NVRAM->lock = 0;
3ccacc4a BS	609	if (NVRAM->alrm_timer != NULL)
	610	qemu_del_timer(NVRAM->alrm_timer);
	611
	612	if (NVRAM->wd_timer != NULL)
	613	qemu_del_timer(NVRAM->wd_timer);
	614	}
	615
a541f297	616	/* Initialisation routine */
5dcb6b91	617	m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
819385c5 FB	618	uint32_t io_base, uint16_t size,
819385c5 FB	619	int type)
a541f297	620	{
d27cf0ae BS	621	DeviceState *dev;
	622	SysBusDevice *s;
	623	m48t59_t *d;
	624
	625	dev = qdev_create(NULL, "m48t59");
ee6847d1 GH	626	qdev_prop_set_uint32(dev, "type", type);
	627	qdev_prop_set_uint32(dev, "size", size);
	628	qdev_prop_set_uint32(dev, "io_base", io_base);
d27cf0ae BS	629	qdev_init(dev);
	630	s = sysbus_from_qdev(dev);
	631	sysbus_connect_irq(s, 0, IRQ);
819385c5 FB	632	if (io_base != 0) {
	633	register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
	634	register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
	635	}
e1bb04f7	636	if (mem_base != 0) {
d27cf0ae	637	sysbus_mmio_map(s, 0, mem_base);
e1bb04f7	638	}
d27cf0ae BS	639
	640	d = FROM_SYSBUS(m48t59_t, s);
	641
	642	return d;
	643	}
	644
81a322d4	645	static int m48t59_init1(SysBusDevice *dev)
d27cf0ae BS	646	{
	647	m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);
	648	int mem_index;
	649
d27cf0ae BS	650	s->buffer = qemu_mallocz(s->size);
d27cf0ae BS	651	sysbus_init_irq(dev, &s->IRQ);
d27cf0ae BS	652
	653	mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
	654	sysbus_init_mmio(dev, s->size, mem_index);
	655
	656	if (s->type == 59) {
819385c5 FB	657	s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
	658	s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
	659	}
f6503059	660	qemu_get_timedate(&s->alarm, 0);
13ab5daa	661
a08d4367	662	qemu_register_reset(m48t59_reset, s);
d27cf0ae	663	register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
81a322d4	664	return 0;
d27cf0ae	665	}
3ccacc4a	666
ee6847d1 GH	667	static SysBusDeviceInfo m48t59_info = {
	668	.init = m48t59_init1,
	669	.qdev.name = "m48t59",
	670	.qdev.size = sizeof(m48t59_t),
	671	.qdev.props = (Property[]) {
01274424 GH	672	DEFINE_PROP_UINT32("size", m48t59_t, size, -1),
	673	DEFINE_PROP_UINT32("type", m48t59_t, type, -1),
	674	DEFINE_PROP_HEX32( "io_base", m48t59_t, io_base, 0),
	675	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	676	}
	677	};
	678
d27cf0ae BS	679	static void m48t59_register_devices(void)
d27cf0ae BS	680	{
ee6847d1	681	sysbus_register_withprop(&m48t59_info);
a541f297	682	}
d27cf0ae BS	683
d27cf0ae BS	684	device_init(m48t59_register_devices)