[qemu.git] / hw / syborg_serial.c

/*
 * Syborg serial port
 *
 * Copyright (c) 2008 CodeSourcery
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "qemu-char.h"
#include "syborg.h"

//#define DEBUG_SYBORG_SERIAL

#ifdef DEBUG_SYBORG_SERIAL
#define DPRINTF(fmt, ...) \
do { printf("syborg_serial: " fmt , ##args); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__); \
    exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

enum {
    SERIAL_ID           = 0,
    SERIAL_DATA         = 1,
    SERIAL_FIFO_COUNT   = 2,
    SERIAL_INT_ENABLE   = 3,
    SERIAL_DMA_TX_ADDR  = 4,
    SERIAL_DMA_TX_COUNT = 5, /* triggers dma */
    SERIAL_DMA_RX_ADDR  = 6,
    SERIAL_DMA_RX_COUNT = 7, /* triggers dma */
    SERIAL_FIFO_SIZE    = 8
};

#define SERIAL_INT_FIFO   (1u << 0)
#define SERIAL_INT_DMA_TX (1u << 1)
#define SERIAL_INT_DMA_RX (1u << 2)

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    uint32_t int_enable;
    uint32_t fifo_size;
    uint32_t *read_fifo;
    int read_pos;
    int read_count;
    CharDriverState *chr;
    qemu_irq irq;
    uint32_t dma_tx_ptr;
    uint32_t dma_rx_ptr;
    uint32_t dma_rx_size;
} SyborgSerialState;

static void syborg_serial_update(SyborgSerialState *s)
{
    int level;
    level = 0;
    if ((s->int_enable & SERIAL_INT_FIFO) && s->read_count)
        level = 1;
    if (s->int_enable & SERIAL_INT_DMA_TX)
        level = 1;
    if ((s->int_enable & SERIAL_INT_DMA_RX) && s->dma_rx_size == 0)
        level = 1;

    qemu_set_irq(s->irq, level);
}

static uint32_t fifo_pop(SyborgSerialState *s)
{
    const uint32_t c = s->read_fifo[s->read_pos];
    s->read_count--;
    s->read_pos++;
    if (s->read_pos == s->fifo_size)
        s->read_pos = 0;

    DPRINTF("FIFO pop %x (%d)\n", c, s->read_count);
    return c;
}

static void fifo_push(SyborgSerialState *s, uint32_t new_value)
{
    int slot;

    DPRINTF("FIFO push %x (%d)\n", new_value, s->read_count);
    slot = s->read_pos + s->read_count;
    if (slot >= s->fifo_size)
          slot -= s->fifo_size;
    s->read_fifo[slot] = new_value;
    s->read_count++;
}

static void do_dma_tx(SyborgSerialState *s, uint32_t count)
{
    unsigned char ch;

    if (count == 0)
        return;

    if (s->chr != NULL) {
        /* optimize later. Now, 1 byte per iteration */
        while (count--) {
            cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
            qemu_chr_fe_write(s->chr, &ch, 1);
            s->dma_tx_ptr++;
        }
    } else {
        s->dma_tx_ptr += count;
    }
    /* QEMU char backends do not have a nonblocking mode, so we transmit all
       the data immediately and the interrupt status will be unchanged.  */
}

/* Initiate RX DMA, and transfer data from the FIFO.  */
static void dma_rx_start(SyborgSerialState *s, uint32_t len)
{
    uint32_t dest;
    unsigned char ch;

    dest = s->dma_rx_ptr;
    if (s->read_count < len) {
        s->dma_rx_size = len - s->read_count;
        len = s->read_count;
    } else {
        s->dma_rx_size = 0;
    }

    while (len--) {
        ch = fifo_pop(s);
        cpu_physical_memory_write(dest, &ch, 1);
        dest++;
    }
    s->dma_rx_ptr = dest;
    syborg_serial_update(s);
}

static uint64_t syborg_serial_read(void *opaque, target_phys_addr_t offset,
                                   unsigned size)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;
    uint32_t c;

    offset &= 0xfff;
    DPRINTF("read 0x%x\n", (int)offset);
    switch(offset >> 2) {
    case SERIAL_ID:
        return SYBORG_ID_SERIAL;
    case SERIAL_DATA:
        if (s->read_count > 0)
            c = fifo_pop(s);
        else
            c = -1;
        syborg_serial_update(s);
        return c;
    case SERIAL_FIFO_COUNT:
        return s->read_count;
    case SERIAL_INT_ENABLE:
        return s->int_enable;
    case SERIAL_DMA_TX_ADDR:
        return s->dma_tx_ptr;
    case SERIAL_DMA_TX_COUNT:
        return 0;
    case SERIAL_DMA_RX_ADDR:
        return s->dma_rx_ptr;
    case SERIAL_DMA_RX_COUNT:
        return s->dma_rx_size;
    case SERIAL_FIFO_SIZE:
        return s->fifo_size;

    default:
        cpu_abort(cpu_single_env, "syborg_serial_read: Bad offset %x\n",
                  (int)offset);
        return 0;
    }
}

static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
                                uint64_t value, unsigned size)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;
    unsigned char ch;

    offset &= 0xfff;
    DPRINTF("Write 0x%x=0x%x\n", (int)offset, value);
    switch (offset >> 2) {
    case SERIAL_DATA:
        ch = value;
        if (s->chr)
            qemu_chr_fe_write(s->chr, &ch, 1);
        break;
    case SERIAL_INT_ENABLE:
        s->int_enable = value;
        syborg_serial_update(s);
        break;
    case SERIAL_DMA_TX_ADDR:
        s->dma_tx_ptr = value;
        break;
    case SERIAL_DMA_TX_COUNT:
        do_dma_tx(s, value);
        break;
    case SERIAL_DMA_RX_ADDR:
        /* For safety, writes to this register cancel any pending DMA.  */
        s->dma_rx_size = 0;
        s->dma_rx_ptr = value;
        break;
    case SERIAL_DMA_RX_COUNT:
        dma_rx_start(s, value);
        break;
    default:
        cpu_abort(cpu_single_env, "syborg_serial_write: Bad offset %x\n",
                  (int)offset);
        break;
    }
}

static int syborg_serial_can_receive(void *opaque)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;

    if (s->dma_rx_size)
        return s->dma_rx_size;
    return s->fifo_size - s->read_count;
}

static void syborg_serial_receive(void *opaque, const uint8_t *buf, int size)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;

    if (s->dma_rx_size) {
        /* Place it in the DMA buffer.  */
        cpu_physical_memory_write(s->dma_rx_ptr, buf, size);
        s->dma_rx_size -= size;
        s->dma_rx_ptr += size;
    } else {
        while (size--)
            fifo_push(s, *buf);
    }

    syborg_serial_update(s);
}

static void syborg_serial_event(void *opaque, int event)
{
    /* TODO: Report BREAK events?  */
}

static const MemoryRegionOps syborg_serial_ops = {
    .read = syborg_serial_read,
    .write = syborg_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_syborg_serial = {
    .name = "syborg_serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_EQUAL(fifo_size, SyborgSerialState),
        VMSTATE_UINT32(int_enable, SyborgSerialState),
        VMSTATE_INT32(read_pos, SyborgSerialState),
        VMSTATE_INT32(read_count, SyborgSerialState),
        VMSTATE_UINT32(dma_tx_ptr, SyborgSerialState),
        VMSTATE_UINT32(dma_rx_ptr, SyborgSerialState),
        VMSTATE_UINT32(dma_rx_size, SyborgSerialState),
        VMSTATE_VARRAY_UINT32(read_fifo, SyborgSerialState, fifo_size, 1,
                              vmstate_info_uint32, uint32),
        VMSTATE_END_OF_LIST()
    }
};

static int syborg_serial_init(SysBusDevice *dev)
{
    SyborgSerialState *s = FROM_SYSBUS(SyborgSerialState, dev);

    sysbus_init_irq(dev, &s->irq);
    memory_region_init_io(&s->iomem, &syborg_serial_ops, s,
                          "serial", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, syborg_serial_can_receive,
                              syborg_serial_receive, syborg_serial_event, s);
    }
    if (s->fifo_size <= 0) {
        fprintf(stderr, "syborg_serial: fifo too small\n");
        s->fifo_size = 16;
    }
    s->read_fifo = g_malloc0(s->fifo_size * sizeof(s->read_fifo[0]));

    return 0;
}

static SysBusDeviceInfo syborg_serial_info = {
    .init = syborg_serial_init,
    .qdev.name  = "syborg,serial",
    .qdev.size  = sizeof(SyborgSerialState),
    .qdev.vmsd  = &vmstate_syborg_serial,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("fifo-size", SyborgSerialState, fifo_size, 16),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void syborg_serial_register_devices(void)
{
    sysbus_register_withprop(&syborg_serial_info);
}

device_init(syborg_serial_register_devices)
Commit	Line	Data
4af39611 PB	1	/*
	2	* Syborg serial port
	3	*
	4	* Copyright (c) 2008 CodeSourcery
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
	26	#include "qemu-char.h"
	27	#include "syborg.h"
	28
	29	//#define DEBUG_SYBORG_SERIAL
	30
	31	#ifdef DEBUG_SYBORG_SERIAL
	32	#define DPRINTF(fmt, ...) \
	33	do { printf("syborg_serial: " fmt , ##args); } while (0)
	34	#define BADF(fmt, ...) \
	35	do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__); \
	36	exit(1);} while (0)
	37	#else
	38	#define DPRINTF(fmt, ...) do {} while(0)
	39	#define BADF(fmt, ...) \
	40	do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__);} while (0)
	41	#endif
	42
	43	enum {
	44	SERIAL_ID = 0,
	45	SERIAL_DATA = 1,
	46	SERIAL_FIFO_COUNT = 2,
	47	SERIAL_INT_ENABLE = 3,
	48	SERIAL_DMA_TX_ADDR = 4,
	49	SERIAL_DMA_TX_COUNT = 5, /* triggers dma */
	50	SERIAL_DMA_RX_ADDR = 6,
	51	SERIAL_DMA_RX_COUNT = 7, /* triggers dma */
	52	SERIAL_FIFO_SIZE = 8
	53	};
	54
	55	#define SERIAL_INT_FIFO (1u << 0)
	56	#define SERIAL_INT_DMA_TX (1u << 1)
	57	#define SERIAL_INT_DMA_RX (1u << 2)
	58
	59	typedef struct {
	60	SysBusDevice busdev;
a8a00822	61	MemoryRegion iomem;
4af39611	62	uint32_t int_enable;
ee6847d1	63	uint32_t fifo_size;
4af39611 PB	64	uint32_t *read_fifo;
	65	int read_pos;
	66	int read_count;
	67	CharDriverState *chr;
	68	qemu_irq irq;
	69	uint32_t dma_tx_ptr;
	70	uint32_t dma_rx_ptr;
	71	uint32_t dma_rx_size;
	72	} SyborgSerialState;
	73
	74	static void syborg_serial_update(SyborgSerialState *s)
	75	{
	76	int level;
	77	level = 0;
	78	if ((s->int_enable & SERIAL_INT_FIFO) && s->read_count)
	79	level = 1;
	80	if (s->int_enable & SERIAL_INT_DMA_TX)
	81	level = 1;
	82	if ((s->int_enable & SERIAL_INT_DMA_RX) && s->dma_rx_size == 0)
	83	level = 1;
	84
	85	qemu_set_irq(s->irq, level);
	86	}
	87
	88	static uint32_t fifo_pop(SyborgSerialState *s)
	89	{
	90	const uint32_t c = s->read_fifo[s->read_pos];
	91	s->read_count--;
	92	s->read_pos++;
	93	if (s->read_pos == s->fifo_size)
	94	s->read_pos = 0;
	95
	96	DPRINTF("FIFO pop %x (%d)\n", c, s->read_count);
	97	return c;
	98	}
	99
	100	static void fifo_push(SyborgSerialState *s, uint32_t new_value)
	101	{
	102	int slot;
	103
	104	DPRINTF("FIFO push %x (%d)\n", new_value, s->read_count);
	105	slot = s->read_pos + s->read_count;
	106	if (slot >= s->fifo_size)
	107	slot -= s->fifo_size;
	108	s->read_fifo[slot] = new_value;
	109	s->read_count++;
	110	}
	111
	112	static void do_dma_tx(SyborgSerialState *s, uint32_t count)
	113	{
	114	unsigned char ch;
	115
	116	if (count == 0)
	117	return;
	118
	119	if (s->chr != NULL) {
	120	/* optimize later. Now, 1 byte per iteration */
	121	while (count--) {
	122	cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
2cc6e0a1	123	qemu_chr_fe_write(s->chr, &ch, 1);
4af39611 PB	124	s->dma_tx_ptr++;
	125	}
	126	} else {
	127	s->dma_tx_ptr += count;
	128	}
	129	/* QEMU char backends do not have a nonblocking mode, so we transmit all
4b71051e	130	the data immediately and the interrupt status will be unchanged. */
4af39611 PB	131	}
	132
	133	/* Initiate RX DMA, and transfer data from the FIFO. */
	134	static void dma_rx_start(SyborgSerialState *s, uint32_t len)
	135	{
	136	uint32_t dest;
	137	unsigned char ch;
	138
	139	dest = s->dma_rx_ptr;
	140	if (s->read_count < len) {
	141	s->dma_rx_size = len - s->read_count;
	142	len = s->read_count;
	143	} else {
	144	s->dma_rx_size = 0;
	145	}
	146
	147	while (len--) {
	148	ch = fifo_pop(s);
	149	cpu_physical_memory_write(dest, &ch, 1);
	150	dest++;
	151	}
	152	s->dma_rx_ptr = dest;
	153	syborg_serial_update(s);
	154	}
	155
a8a00822 BC	156	static uint64_t syborg_serial_read(void *opaque, target_phys_addr_t offset,
a8a00822 BC	157	unsigned size)
4af39611 PB	158	{
	159	SyborgSerialState s = (SyborgSerialState )opaque;
	160	uint32_t c;
	161
	162	offset &= 0xfff;
	163	DPRINTF("read 0x%x\n", (int)offset);
	164	switch(offset >> 2) {
	165	case SERIAL_ID:
	166	return SYBORG_ID_SERIAL;
	167	case SERIAL_DATA:
	168	if (s->read_count > 0)
	169	c = fifo_pop(s);
	170	else
	171	c = -1;
	172	syborg_serial_update(s);
	173	return c;
	174	case SERIAL_FIFO_COUNT:
	175	return s->read_count;
	176	case SERIAL_INT_ENABLE:
	177	return s->int_enable;
	178	case SERIAL_DMA_TX_ADDR:
	179	return s->dma_tx_ptr;
	180	case SERIAL_DMA_TX_COUNT:
	181	return 0;
	182	case SERIAL_DMA_RX_ADDR:
	183	return s->dma_rx_ptr;
	184	case SERIAL_DMA_RX_COUNT:
	185	return s->dma_rx_size;
	186	case SERIAL_FIFO_SIZE:
	187	return s->fifo_size;
	188
	189	default:
	190	cpu_abort(cpu_single_env, "syborg_serial_read: Bad offset %x\n",
	191	(int)offset);
	192	return 0;
	193	}
	194	}
	195
c227f099	196	static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
a8a00822	197	uint64_t value, unsigned size)
4af39611 PB	198	{
	199	SyborgSerialState s = (SyborgSerialState )opaque;
	200	unsigned char ch;
	201
	202	offset &= 0xfff;
	203	DPRINTF("Write 0x%x=0x%x\n", (int)offset, value);
	204	switch (offset >> 2) {
	205	case SERIAL_DATA:
	206	ch = value;
	207	if (s->chr)
2cc6e0a1	208	qemu_chr_fe_write(s->chr, &ch, 1);
4af39611 PB	209	break;
	210	case SERIAL_INT_ENABLE:
	211	s->int_enable = value;
	212	syborg_serial_update(s);
	213	break;
	214	case SERIAL_DMA_TX_ADDR:
	215	s->dma_tx_ptr = value;
	216	break;
	217	case SERIAL_DMA_TX_COUNT:
	218	do_dma_tx(s, value);
	219	break;
	220	case SERIAL_DMA_RX_ADDR:
	221	/* For safety, writes to this register cancel any pending DMA. */
	222	s->dma_rx_size = 0;
	223	s->dma_rx_ptr = value;
	224	break;
	225	case SERIAL_DMA_RX_COUNT:
	226	dma_rx_start(s, value);
	227	break;
	228	default:
	229	cpu_abort(cpu_single_env, "syborg_serial_write: Bad offset %x\n",
	230	(int)offset);
	231	break;
	232	}
	233	}
	234
	235	static int syborg_serial_can_receive(void *opaque)
	236	{
	237	SyborgSerialState s = (SyborgSerialState )opaque;
	238
	239	if (s->dma_rx_size)
	240	return s->dma_rx_size;
	241	return s->fifo_size - s->read_count;
	242	}
	243
	244	static void syborg_serial_receive(void opaque, const uint8_t buf, int size)
	245	{
	246	SyborgSerialState s = (SyborgSerialState )opaque;
	247
	248	if (s->dma_rx_size) {
	249	/* Place it in the DMA buffer. */
	250	cpu_physical_memory_write(s->dma_rx_ptr, buf, size);
	251	s->dma_rx_size -= size;
	252	s->dma_rx_ptr += size;
	253	} else {
	254	while (size--)
	255	fifo_push(s, *buf);
	256	}
	257
	258	syborg_serial_update(s);
	259	}
	260
	261	static void syborg_serial_event(void *opaque, int event)
	262	{
	263	/* TODO: Report BREAK events? */
	264	}
	265
a8a00822 BC	266	static const MemoryRegionOps syborg_serial_ops = {
	267	.read = syborg_serial_read,
	268	.write = syborg_serial_write,
	269	.endianness = DEVICE_NATIVE_ENDIAN,
4af39611 PB	270	};
4af39611 PB	271
8dc59070 JQ	272	static const VMStateDescription vmstate_syborg_serial = {
	273	.name = "syborg_serial",
	274	.version_id = 1,
	275	.minimum_version_id = 1,
	276	.minimum_version_id_old = 1,
	277	.fields = (VMStateField[]) {
	278	VMSTATE_UINT32_EQUAL(fifo_size, SyborgSerialState),
	279	VMSTATE_UINT32(int_enable, SyborgSerialState),
	280	VMSTATE_INT32(read_pos, SyborgSerialState),
	281	VMSTATE_INT32(read_count, SyborgSerialState),
	282	VMSTATE_UINT32(dma_tx_ptr, SyborgSerialState),
	283	VMSTATE_UINT32(dma_rx_ptr, SyborgSerialState),
	284	VMSTATE_UINT32(dma_rx_size, SyborgSerialState),
	285	VMSTATE_VARRAY_UINT32(read_fifo, SyborgSerialState, fifo_size, 1,
	286	vmstate_info_uint32, uint32),
	287	VMSTATE_END_OF_LIST()
4af39611	288	}
8dc59070	289	};
4af39611	290
81a322d4	291	static int syborg_serial_init(SysBusDevice *dev)
4af39611 PB	292	{
4af39611 PB	293	SyborgSerialState *s = FROM_SYSBUS(SyborgSerialState, dev);
4af39611 PB	294
4af39611 PB	295	sysbus_init_irq(dev, &s->irq);
a8a00822 BC	296	memory_region_init_io(&s->iomem, &syborg_serial_ops, s,
a8a00822 BC	297	"serial", 0x1000);
750ecd44	298	sysbus_init_mmio(dev, &s->iomem);
4af39611 PB	299	s->chr = qdev_init_chardev(&dev->qdev);
	300	if (s->chr) {
	301	qemu_chr_add_handlers(s->chr, syborg_serial_can_receive,
	302	syborg_serial_receive, syborg_serial_event, s);
	303	}
4af39611 PB	304	if (s->fifo_size <= 0) {
	305	fprintf(stderr, "syborg_serial: fifo too small\n");
	306	s->fifo_size = 16;
	307	}
7267c094	308	s->read_fifo = g_malloc0(s->fifo_size * sizeof(s->read_fifo[0]));
4af39611	309
81a322d4	310	return 0;
4af39611 PB	311	}
4af39611 PB	312
ee6847d1 GH	313	static SysBusDeviceInfo syborg_serial_info = {
	314	.init = syborg_serial_init,
	315	.qdev.name = "syborg,serial",
	316	.qdev.size = sizeof(SyborgSerialState),
8dc59070	317	.qdev.vmsd = &vmstate_syborg_serial,
ee6847d1	318	.qdev.props = (Property[]) {
c4470b25 GH	319	DEFINE_PROP_UINT32("fifo-size", SyborgSerialState, fifo_size, 16),
c4470b25 GH	320	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	321	}
	322	};
	323
4af39611 PB	324	static void syborg_serial_register_devices(void)
4af39611 PB	325	{
ee6847d1	326	sysbus_register_withprop(&syborg_serial_info);
4af39611 PB	327	}
	328
	329	device_init(syborg_serial_register_devices)