[qemu.git] / hw / syborg_serial.c

/*
 * Syborg serial port
 *
 * Copyright (c) 2008 CodeSourcery
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "qemu-char.h"
#include "syborg.h"

//#define DEBUG_SYBORG_SERIAL

#ifdef DEBUG_SYBORG_SERIAL
#define DPRINTF(fmt, ...) \
do { printf("syborg_serial: " fmt , ##args); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__); \
    exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

enum {
    SERIAL_ID           = 0,
    SERIAL_DATA         = 1,
    SERIAL_FIFO_COUNT   = 2,
    SERIAL_INT_ENABLE   = 3,
    SERIAL_DMA_TX_ADDR  = 4,
    SERIAL_DMA_TX_COUNT = 5, /* triggers dma */
    SERIAL_DMA_RX_ADDR  = 6,
    SERIAL_DMA_RX_COUNT = 7, /* triggers dma */
    SERIAL_FIFO_SIZE    = 8
};

#define SERIAL_INT_FIFO   (1u << 0)
#define SERIAL_INT_DMA_TX (1u << 1)
#define SERIAL_INT_DMA_RX (1u << 2)

typedef struct {
    SysBusDevice busdev;
    uint32_t int_enable;
    uint32_t fifo_size;
    uint32_t *read_fifo;
    int read_pos;
    int read_count;
    CharDriverState *chr;
    qemu_irq irq;
    uint32_t dma_tx_ptr;
    uint32_t dma_rx_ptr;
    uint32_t dma_rx_size;
} SyborgSerialState;

static void syborg_serial_update(SyborgSerialState *s)
{
    int level;
    level = 0;
    if ((s->int_enable & SERIAL_INT_FIFO) && s->read_count)
        level = 1;
    if (s->int_enable & SERIAL_INT_DMA_TX)
        level = 1;
    if ((s->int_enable & SERIAL_INT_DMA_RX) && s->dma_rx_size == 0)
        level = 1;

    qemu_set_irq(s->irq, level);
}

static uint32_t fifo_pop(SyborgSerialState *s)
{
    const uint32_t c = s->read_fifo[s->read_pos];
    s->read_count--;
    s->read_pos++;
    if (s->read_pos == s->fifo_size)
        s->read_pos = 0;

    DPRINTF("FIFO pop %x (%d)\n", c, s->read_count);
    return c;
}

static void fifo_push(SyborgSerialState *s, uint32_t new_value)
{
    int slot;

    DPRINTF("FIFO push %x (%d)\n", new_value, s->read_count);
    slot = s->read_pos + s->read_count;
    if (slot >= s->fifo_size)
          slot -= s->fifo_size;
    s->read_fifo[slot] = new_value;
    s->read_count++;
}

static void do_dma_tx(SyborgSerialState *s, uint32_t count)
{
    unsigned char ch;

    if (count == 0)
        return;

    if (s->chr != NULL) {
        /* optimize later. Now, 1 byte per iteration */
        while (count--) {
            cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
            qemu_chr_write(s->chr, &ch, 1);
            s->dma_tx_ptr++;
        }
    } else {
        s->dma_tx_ptr += count;
    }
    /* QEMU char backends do not have a nonblocking mode, so we transmit all
       the data imediately and the interrupt status will be unchanged.  */
}

/* Initiate RX DMA, and transfer data from the FIFO.  */
static void dma_rx_start(SyborgSerialState *s, uint32_t len)
{
    uint32_t dest;
    unsigned char ch;

    dest = s->dma_rx_ptr;
    if (s->read_count < len) {
        s->dma_rx_size = len - s->read_count;
        len = s->read_count;
    } else {
        s->dma_rx_size = 0;
    }

    while (len--) {
        ch = fifo_pop(s);
        cpu_physical_memory_write(dest, &ch, 1);
        dest++;
    }
    s->dma_rx_ptr = dest;
    syborg_serial_update(s);
}

static uint32_t syborg_serial_read(void *opaque, target_phys_addr_t offset)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;
    uint32_t c;

    offset &= 0xfff;
    DPRINTF("read 0x%x\n", (int)offset);
    switch(offset >> 2) {
    case SERIAL_ID:
        return SYBORG_ID_SERIAL;
    case SERIAL_DATA:
        if (s->read_count > 0)
            c = fifo_pop(s);
        else
            c = -1;
        syborg_serial_update(s);
        return c;
    case SERIAL_FIFO_COUNT:
        return s->read_count;
    case SERIAL_INT_ENABLE:
        return s->int_enable;
    case SERIAL_DMA_TX_ADDR:
        return s->dma_tx_ptr;
    case SERIAL_DMA_TX_COUNT:
        return 0;
    case SERIAL_DMA_RX_ADDR:
        return s->dma_rx_ptr;
    case SERIAL_DMA_RX_COUNT:
        return s->dma_rx_size;
    case SERIAL_FIFO_SIZE:
        return s->fifo_size;

    default:
        cpu_abort(cpu_single_env, "syborg_serial_read: Bad offset %x\n",
                  (int)offset);
        return 0;
    }
}

static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
                                uint32_t value)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;
    unsigned char ch;

    offset &= 0xfff;
    DPRINTF("Write 0x%x=0x%x\n", (int)offset, value);
    switch (offset >> 2) {
    case SERIAL_DATA:
        ch = value;
        if (s->chr)
            qemu_chr_write(s->chr, &ch, 1);
        break;
    case SERIAL_INT_ENABLE:
        s->int_enable = value;
        syborg_serial_update(s);
        break;
    case SERIAL_DMA_TX_ADDR:
        s->dma_tx_ptr = value;
        break;
    case SERIAL_DMA_TX_COUNT:
        do_dma_tx(s, value);
        break;
    case SERIAL_DMA_RX_ADDR:
        /* For safety, writes to this register cancel any pending DMA.  */
        s->dma_rx_size = 0;
        s->dma_rx_ptr = value;
        break;
    case SERIAL_DMA_RX_COUNT:
        dma_rx_start(s, value);
        break;
    default:
        cpu_abort(cpu_single_env, "syborg_serial_write: Bad offset %x\n",
                  (int)offset);
        break;
    }
}

static int syborg_serial_can_receive(void *opaque)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;

    if (s->dma_rx_size)
        return s->dma_rx_size;
    return s->fifo_size - s->read_count;
}

static void syborg_serial_receive(void *opaque, const uint8_t *buf, int size)
{
    SyborgSerialState *s = (SyborgSerialState *)opaque;

    if (s->dma_rx_size) {
        /* Place it in the DMA buffer.  */
        cpu_physical_memory_write(s->dma_rx_ptr, buf, size);
        s->dma_rx_size -= size;
        s->dma_rx_ptr += size;
    } else {
        while (size--)
            fifo_push(s, *buf);
    }

    syborg_serial_update(s);
}

static void syborg_serial_event(void *opaque, int event)
{
    /* TODO: Report BREAK events?  */
}

static CPUReadMemoryFunc * const syborg_serial_readfn[] = {
     syborg_serial_read,
     syborg_serial_read,
     syborg_serial_read
};

static CPUWriteMemoryFunc * const syborg_serial_writefn[] = {
     syborg_serial_write,
     syborg_serial_write,
     syborg_serial_write
};

static void syborg_serial_save(QEMUFile *f, void *opaque)
{
    SyborgSerialState *s = opaque;
    int i;

    qemu_put_be32(f, s->fifo_size);
    qemu_put_be32(f, s->int_enable);
    qemu_put_be32(f, s->read_pos);
    qemu_put_be32(f, s->read_count);
    qemu_put_be32(f, s->dma_tx_ptr);
    qemu_put_be32(f, s->dma_rx_ptr);
    qemu_put_be32(f, s->dma_rx_size);
    for (i = 0; i < s->fifo_size; i++) {
        qemu_put_be32(f, s->read_fifo[i]);
    }
}

static int syborg_serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SyborgSerialState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    i = qemu_get_be32(f);
    if (s->fifo_size != i)
        return -EINVAL;

    s->int_enable = qemu_get_be32(f);
    s->read_pos = qemu_get_be32(f);
    s->read_count = qemu_get_be32(f);
    s->dma_tx_ptr = qemu_get_be32(f);
    s->dma_rx_ptr = qemu_get_be32(f);
    s->dma_rx_size = qemu_get_be32(f);
    for (i = 0; i < s->fifo_size; i++) {
        s->read_fifo[i] = qemu_get_be32(f);
    }

    return 0;
}

static void syborg_serial_init(SysBusDevice *dev)
{
    SyborgSerialState *s = FROM_SYSBUS(SyborgSerialState, dev);
    int iomemtype;

    sysbus_init_irq(dev, &s->irq);
    iomemtype = cpu_register_io_memory(syborg_serial_readfn,
                                       syborg_serial_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, syborg_serial_can_receive,
                              syborg_serial_receive, syborg_serial_event, s);
    }
    if (s->fifo_size <= 0) {
        fprintf(stderr, "syborg_serial: fifo too small\n");
        s->fifo_size = 16;
    }
    s->read_fifo = qemu_mallocz(s->fifo_size * sizeof(s->read_fifo[0]));

    register_savevm("syborg_serial", -1, 1,
                    syborg_serial_save, syborg_serial_load, s);
}

static SysBusDeviceInfo syborg_serial_info = {
    .init = syborg_serial_init,
    .qdev.name  = "syborg,serial",
    .qdev.size  = sizeof(SyborgSerialState),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("fifo-size", SyborgSerialState, fifo_size, 16),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void syborg_serial_register_devices(void)
{
    sysbus_register_withprop(&syborg_serial_info);
}

device_init(syborg_serial_register_devices)
Commit	Line	Data
4af39611 PB	1	/*
	2	* Syborg serial port
	3	*
	4	* Copyright (c) 2008 CodeSourcery
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
	26	#include "qemu-char.h"
	27	#include "syborg.h"
	28
	29	//#define DEBUG_SYBORG_SERIAL
	30
	31	#ifdef DEBUG_SYBORG_SERIAL
	32	#define DPRINTF(fmt, ...) \
	33	do { printf("syborg_serial: " fmt , ##args); } while (0)
	34	#define BADF(fmt, ...) \
	35	do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__); \
	36	exit(1);} while (0)
	37	#else
	38	#define DPRINTF(fmt, ...) do {} while(0)
	39	#define BADF(fmt, ...) \
	40	do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__);} while (0)
	41	#endif
	42
	43	enum {
	44	SERIAL_ID = 0,
	45	SERIAL_DATA = 1,
	46	SERIAL_FIFO_COUNT = 2,
	47	SERIAL_INT_ENABLE = 3,
	48	SERIAL_DMA_TX_ADDR = 4,
	49	SERIAL_DMA_TX_COUNT = 5, /* triggers dma */
	50	SERIAL_DMA_RX_ADDR = 6,
	51	SERIAL_DMA_RX_COUNT = 7, /* triggers dma */
	52	SERIAL_FIFO_SIZE = 8
	53	};
	54
	55	#define SERIAL_INT_FIFO (1u << 0)
	56	#define SERIAL_INT_DMA_TX (1u << 1)
	57	#define SERIAL_INT_DMA_RX (1u << 2)
	58
	59	typedef struct {
	60	SysBusDevice busdev;
	61	uint32_t int_enable;
ee6847d1	62	uint32_t fifo_size;
4af39611 PB	63	uint32_t *read_fifo;
	64	int read_pos;
	65	int read_count;
	66	CharDriverState *chr;
	67	qemu_irq irq;
	68	uint32_t dma_tx_ptr;
	69	uint32_t dma_rx_ptr;
	70	uint32_t dma_rx_size;
	71	} SyborgSerialState;
	72
	73	static void syborg_serial_update(SyborgSerialState *s)
	74	{
	75	int level;
	76	level = 0;
	77	if ((s->int_enable & SERIAL_INT_FIFO) && s->read_count)
	78	level = 1;
	79	if (s->int_enable & SERIAL_INT_DMA_TX)
	80	level = 1;
	81	if ((s->int_enable & SERIAL_INT_DMA_RX) && s->dma_rx_size == 0)
	82	level = 1;
	83
	84	qemu_set_irq(s->irq, level);
	85	}
	86
	87	static uint32_t fifo_pop(SyborgSerialState *s)
	88	{
	89	const uint32_t c = s->read_fifo[s->read_pos];
	90	s->read_count--;
	91	s->read_pos++;
	92	if (s->read_pos == s->fifo_size)
	93	s->read_pos = 0;
	94
	95	DPRINTF("FIFO pop %x (%d)\n", c, s->read_count);
	96	return c;
	97	}
	98
	99	static void fifo_push(SyborgSerialState *s, uint32_t new_value)
	100	{
	101	int slot;
	102
	103	DPRINTF("FIFO push %x (%d)\n", new_value, s->read_count);
	104	slot = s->read_pos + s->read_count;
	105	if (slot >= s->fifo_size)
	106	slot -= s->fifo_size;
	107	s->read_fifo[slot] = new_value;
	108	s->read_count++;
	109	}
	110
	111	static void do_dma_tx(SyborgSerialState *s, uint32_t count)
	112	{
	113	unsigned char ch;
	114
	115	if (count == 0)
	116	return;
	117
	118	if (s->chr != NULL) {
	119	/* optimize later. Now, 1 byte per iteration */
	120	while (count--) {
	121	cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
	122	qemu_chr_write(s->chr, &ch, 1);
	123	s->dma_tx_ptr++;
	124	}
	125	} else {
	126	s->dma_tx_ptr += count;
127	}
128	/* QEMU char backends do not have a nonblocking mode, so we transmit all
129	the data imediately and the interrupt status will be unchanged. */
130	}
131
132	/* Initiate RX DMA, and transfer data from the FIFO. */
133	static void dma_rx_start(SyborgSerialState *s, uint32_t len)
134	{
135	uint32_t dest;
136	unsigned char ch;
137
138	dest = s->dma_rx_ptr;
139	if (s->read_count < len) {
140	s->dma_rx_size = len - s->read_count;
141	len = s->read_count;
142	} else {
143	s->dma_rx_size = 0;
144	}
145
146	while (len--) {
147	ch = fifo_pop(s);
148	cpu_physical_memory_write(dest, &ch, 1);
149	dest++;
150	}
151	s->dma_rx_ptr = dest;
152	syborg_serial_update(s);
153	}
154
155	static uint32_t syborg_serial_read(void *opaque, target_phys_addr_t offset)
156	{
157	SyborgSerialState s = (SyborgSerialState )opaque;
158	uint32_t c;
159
160	offset &= 0xfff;
161	DPRINTF("read 0x%x\n", (int)offset);
162	switch(offset >> 2) {
163	case SERIAL_ID:
164	return SYBORG_ID_SERIAL;
165	case SERIAL_DATA:
166	if (s->read_count > 0)
167	c = fifo_pop(s);
168	else
169	c = -1;
170	syborg_serial_update(s);
171	return c;
172	case SERIAL_FIFO_COUNT:
173	return s->read_count;
174	case SERIAL_INT_ENABLE:
175	return s->int_enable;
176	case SERIAL_DMA_TX_ADDR:
177	return s->dma_tx_ptr;
178	case SERIAL_DMA_TX_COUNT:
179	return 0;
180	case SERIAL_DMA_RX_ADDR:
181	return s->dma_rx_ptr;
182	case SERIAL_DMA_RX_COUNT:
183	return s->dma_rx_size;
184	case SERIAL_FIFO_SIZE:
185	return s->fifo_size;
186
187	default:
188	cpu_abort(cpu_single_env, "syborg_serial_read: Bad offset %x\n",
189	(int)offset);
190	return 0;
191	}
192	}
193
194	static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
195	uint32_t value)
196	{
197	SyborgSerialState s = (SyborgSerialState )opaque;
198	unsigned char ch;
199
200	offset &= 0xfff;
201	DPRINTF("Write 0x%x=0x%x\n", (int)offset, value);
202	switch (offset >> 2) {
203	case SERIAL_DATA:
204	ch = value;
205	if (s->chr)
206	qemu_chr_write(s->chr, &ch, 1);
207	break;
208	case SERIAL_INT_ENABLE:
209	s->int_enable = value;
210	syborg_serial_update(s);
211	break;
212	case SERIAL_DMA_TX_ADDR:
213	s->dma_tx_ptr = value;
214	break;
215	case SERIAL_DMA_TX_COUNT:
216	do_dma_tx(s, value);
217	break;
218	case SERIAL_DMA_RX_ADDR:
219	/* For safety, writes to this register cancel any pending DMA. */
220	s->dma_rx_size = 0;
221	s->dma_rx_ptr = value;
222	break;
223	case SERIAL_DMA_RX_COUNT:
224	dma_rx_start(s, value);
225	break;
226	default:
227	cpu_abort(cpu_single_env, "syborg_serial_write: Bad offset %x\n",
228	(int)offset);
229	break;
230	}
231	}
232
233	static int syborg_serial_can_receive(void *opaque)
234	{
235	SyborgSerialState s = (SyborgSerialState )opaque;
236
237	if (s->dma_rx_size)
238	return s->dma_rx_size;
239	return s->fifo_size - s->read_count;
240	}
241
242	static void syborg_serial_receive(void opaque, const uint8_t buf, int size)
243	{
244	SyborgSerialState s = (SyborgSerialState )opaque;
245
246	if (s->dma_rx_size) {
247	/* Place it in the DMA buffer. */
248	cpu_physical_memory_write(s->dma_rx_ptr, buf, size);
249	s->dma_rx_size -= size;
250	s->dma_rx_ptr += size;
251	} else {
252	while (size--)
253	fifo_push(s, *buf);
254	}
255
256	syborg_serial_update(s);
257	}
258
259	static void syborg_serial_event(void *opaque, int event)
260	{
261	/* TODO: Report BREAK events? */
262	}
263
d60efc6b	264	static CPUReadMemoryFunc * const syborg_serial_readfn[] = {
4af39611 PB	265	syborg_serial_read,
	266	syborg_serial_read,
	267	syborg_serial_read
	268	};
	269
d60efc6b	270	static CPUWriteMemoryFunc * const syborg_serial_writefn[] = {
4af39611 PB	271	syborg_serial_write,
	272	syborg_serial_write,
	273	syborg_serial_write
	274	};
	275
	276	static void syborg_serial_save(QEMUFile f, void opaque)
	277	{
	278	SyborgSerialState *s = opaque;
	279	int i;
	280
	281	qemu_put_be32(f, s->fifo_size);
	282	qemu_put_be32(f, s->int_enable);
	283	qemu_put_be32(f, s->read_pos);
	284	qemu_put_be32(f, s->read_count);
	285	qemu_put_be32(f, s->dma_tx_ptr);
	286	qemu_put_be32(f, s->dma_rx_ptr);
	287	qemu_put_be32(f, s->dma_rx_size);
	288	for (i = 0; i < s->fifo_size; i++) {
	289	qemu_put_be32(f, s->read_fifo[i]);
	290	}
	291	}
	292
	293	static int syborg_serial_load(QEMUFile f, void opaque, int version_id)
	294	{
	295	SyborgSerialState *s = opaque;
	296	int i;
	297
	298	if (version_id != 1)
	299	return -EINVAL;
	300
	301	i = qemu_get_be32(f);
	302	if (s->fifo_size != i)
	303	return -EINVAL;
	304
	305	s->int_enable = qemu_get_be32(f);
	306	s->read_pos = qemu_get_be32(f);
	307	s->read_count = qemu_get_be32(f);
	308	s->dma_tx_ptr = qemu_get_be32(f);
	309	s->dma_rx_ptr = qemu_get_be32(f);
	310	s->dma_rx_size = qemu_get_be32(f);
	311	for (i = 0; i < s->fifo_size; i++) {
	312	s->read_fifo[i] = qemu_get_be32(f);
	313	}
	314
	315	return 0;
	316	}
	317
	318	static void syborg_serial_init(SysBusDevice *dev)
	319	{
	320	SyborgSerialState *s = FROM_SYSBUS(SyborgSerialState, dev);
	321	int iomemtype;
	322
	323	sysbus_init_irq(dev, &s->irq);
1eed09cb	324	iomemtype = cpu_register_io_memory(syborg_serial_readfn,
4af39611 PB	325	syborg_serial_writefn, s);
	326	sysbus_init_mmio(dev, 0x1000, iomemtype);
	327	s->chr = qdev_init_chardev(&dev->qdev);
	328	if (s->chr) {
	329	qemu_chr_add_handlers(s->chr, syborg_serial_can_receive,
	330	syborg_serial_receive, syborg_serial_event, s);
	331	}
4af39611 PB	332	if (s->fifo_size <= 0) {
	333	fprintf(stderr, "syborg_serial: fifo too small\n");
	334	s->fifo_size = 16;
	335	}
	336	s->read_fifo = qemu_mallocz(s->fifo_size * sizeof(s->read_fifo[0]));
	337
	338	register_savevm("syborg_serial", -1, 1,
	339	syborg_serial_save, syborg_serial_load, s);
	340	}
	341
ee6847d1 GH	342	static SysBusDeviceInfo syborg_serial_info = {
	343	.init = syborg_serial_init,
	344	.qdev.name = "syborg,serial",
	345	.qdev.size = sizeof(SyborgSerialState),
	346	.qdev.props = (Property[]) {
c4470b25 GH	347	DEFINE_PROP_UINT32("fifo-size", SyborgSerialState, fifo_size, 16),
c4470b25 GH	348	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	349	}
	350	};
	351
4af39611 PB	352	static void syborg_serial_register_devices(void)
4af39611 PB	353	{
ee6847d1	354	sysbus_register_withprop(&syborg_serial_info);
4af39611 PB	355	}
	356
	357	device_init(syborg_serial_register_devices)