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[qemu.git] / hw / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
a41b2ff2
PB		 48 */
49
87ecb68b
PB		 50#include "hw.h"
51#include "pci.h"
52#include "qemu-timer.h"
53#include "net.h"
254111ec 54#include "loader.h"
1ca4d09a 55#include "sysemu.h"
a41b2ff2 56
a41b2ff2
PB		 57/* debug RTL8139 card */
58//#define DEBUG_RTL8139 1
59
6cadb320
FB		 60#define PCI_FREQUENCY 33000000L
61
a41b2ff2
PB		 62/* debug RTL8139 card C+ mode only */
63//#define DEBUG_RTL8139CP 1
64
ccf1d14a
TS		 65/* Calculate CRCs properly on Rx packets */
66#define RTL8139_CALCULATE_RXCRC 1
a41b2ff2 67
a41b2ff2
PB		 68#if defined(RTL8139_CALCULATE_RXCRC)
69/* For crc32 */
70#include <zlib.h>
71#endif
72
73#define SET_MASKED(input, mask, curr) \
74 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
75
76/* arg % size for size which is a power of 2 */
77#define MOD2(input, size) \
78 ( ( input ) & ( size - 1 ) )
79
6cadb320
FB		 80#if defined (DEBUG_RTL8139)
81# define DEBUG_PRINT(x) do { printf x ; } while (0)
82#else
83# define DEBUG_PRINT(x)
84#endif
85
a41b2ff2
PB		 86/* Symbolic offsets to registers. */
87enum RTL8139_registers {
88 MAC0 = 0, /* Ethernet hardware address. */
89 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 90 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
91 /* Dump Tally Conter control register(64bit). C+ mode only */
92 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 93 RxBuf = 0x30,
94 ChipCmd = 0x37,
95 RxBufPtr = 0x38,
96 RxBufAddr = 0x3A,
97 IntrMask = 0x3C,
98 IntrStatus = 0x3E,
99 TxConfig = 0x40,
100 RxConfig = 0x44,
101 Timer = 0x48, /* A general-purpose counter. */
102 RxMissed = 0x4C, /* 24 bits valid, write clears. */
103 Cfg9346 = 0x50,
104 Config0 = 0x51,
105 Config1 = 0x52,
106 FlashReg = 0x54,
107 MediaStatus = 0x58,
108 Config3 = 0x59,
109 Config4 = 0x5A, /* absent on RTL-8139A */
110 HltClk = 0x5B,
111 MultiIntr = 0x5C,
112 PCIRevisionID = 0x5E,
113 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
114 BasicModeCtrl = 0x62,
115 BasicModeStatus = 0x64,
116 NWayAdvert = 0x66,
117 NWayLPAR = 0x68,
118 NWayExpansion = 0x6A,
119 /* Undocumented registers, but required for proper operation. */
120 FIFOTMS = 0x70, /* FIFO Control and test. */
121 CSCR = 0x74, /* Chip Status and Configuration Register. */
122 PARA78 = 0x78,
123 PARA7c = 0x7c, /* Magic transceiver parameter register. */
124 Config5 = 0xD8, /* absent on RTL-8139A */
125 /* C+ mode */
126 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
127 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
128 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
129 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
130 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
131 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
132 TxThresh = 0xEC, /* Early Tx threshold */
133};
134
135enum ClearBitMasks {
136 MultiIntrClear = 0xF000,
137 ChipCmdClear = 0xE2,
138 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
139};
140
141enum ChipCmdBits {
142 CmdReset = 0x10,
143 CmdRxEnb = 0x08,
144 CmdTxEnb = 0x04,
145 RxBufEmpty = 0x01,
146};
147
148/* C+ mode */
149enum CplusCmdBits {
6cadb320
FB		 150 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
151 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
152 CPlusRxEnb = 0x0002,
153 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 154};
155
156/* Interrupt register bits, using my own meaningful names. */
157enum IntrStatusBits {
158 PCIErr = 0x8000,
159 PCSTimeout = 0x4000,
160 RxFIFOOver = 0x40,
161 RxUnderrun = 0x20,
162 RxOverflow = 0x10,
163 TxErr = 0x08,
164 TxOK = 0x04,
165 RxErr = 0x02,
166 RxOK = 0x01,
167
168 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
169};
170
171enum TxStatusBits {
172 TxHostOwns = 0x2000,
173 TxUnderrun = 0x4000,
174 TxStatOK = 0x8000,
175 TxOutOfWindow = 0x20000000,
176 TxAborted = 0x40000000,
177 TxCarrierLost = 0x80000000,
178};
179enum RxStatusBits {
180 RxMulticast = 0x8000,
181 RxPhysical = 0x4000,
182 RxBroadcast = 0x2000,
183 RxBadSymbol = 0x0020,
184 RxRunt = 0x0010,
185 RxTooLong = 0x0008,
186 RxCRCErr = 0x0004,
187 RxBadAlign = 0x0002,
188 RxStatusOK = 0x0001,
189};
190
191/* Bits in RxConfig. */
192enum rx_mode_bits {
193 AcceptErr = 0x20,
194 AcceptRunt = 0x10,
195 AcceptBroadcast = 0x08,
196 AcceptMulticast = 0x04,
197 AcceptMyPhys = 0x02,
198 AcceptAllPhys = 0x01,
199};
200
201/* Bits in TxConfig. */
202enum tx_config_bits {
203
204 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
205 TxIFGShift = 24,
206 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
207 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
208 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
209 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
210
211 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
212 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
213 TxClearAbt = (1 << 0), /* Clear abort (WO) */
214 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
215 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
216
217 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
218};
219
220
221/* Transmit Status of All Descriptors (TSAD) Register */
222enum TSAD_bits {
223 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
224 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
225 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
226 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
227 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
228 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
229 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
230 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
231 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
232 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
233 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
234 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
235 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
236 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
237 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
238 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
239};
240
241
242/* Bits in Config1 */
243enum Config1Bits {
244 Cfg1_PM_Enable = 0x01,
245 Cfg1_VPD_Enable = 0x02,
246 Cfg1_PIO = 0x04,
247 Cfg1_MMIO = 0x08,
248 LWAKE = 0x10, /* not on 8139, 8139A */
249 Cfg1_Driver_Load = 0x20,
250 Cfg1_LED0 = 0x40,
251 Cfg1_LED1 = 0x80,
252 SLEEP = (1 << 1), /* only on 8139, 8139A */
253 PWRDN = (1 << 0), /* only on 8139, 8139A */
254};
255
256/* Bits in Config3 */
257enum Config3Bits {
258 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
259 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
260 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
261 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
262 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
263 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
264 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
265 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
266};
267
268/* Bits in Config4 */
269enum Config4Bits {
270 LWPTN = (1 << 2), /* not on 8139, 8139A */
271};
272
273/* Bits in Config5 */
274enum Config5Bits {
275 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
276 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
277 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
278 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
279 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
280 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
281 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
282};
283
284enum RxConfigBits {
285 /* rx fifo threshold */
286 RxCfgFIFOShift = 13,
287 RxCfgFIFONone = (7 << RxCfgFIFOShift),
288
289 /* Max DMA burst */
290 RxCfgDMAShift = 8,
291 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
292
293 /* rx ring buffer length */
294 RxCfgRcv8K = 0,
295 RxCfgRcv16K = (1 << 11),
296 RxCfgRcv32K = (1 << 12),
297 RxCfgRcv64K = (1 << 11) | (1 << 12),
298
299 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
300 RxNoWrap = (1 << 7),
301};
302
303/* Twister tuning parameters from RealTek.
304 Completely undocumented, but required to tune bad links on some boards. */
305/*
306enum CSCRBits {
307 CSCR_LinkOKBit = 0x0400,
308 CSCR_LinkChangeBit = 0x0800,
309 CSCR_LinkStatusBits = 0x0f000,
310 CSCR_LinkDownOffCmd = 0x003c0,
311 CSCR_LinkDownCmd = 0x0f3c0,
312*/
313enum CSCRBits {
5fafdf24 314 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 315 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
316 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
317 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 318 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 319 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
320 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
321 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
322 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
323};
324
325enum Cfg9346Bits {
326 Cfg9346_Lock = 0x00,
327 Cfg9346_Unlock = 0xC0,
328};
329
330typedef enum {
331 CH_8139 = 0,
332 CH_8139_K,
333 CH_8139A,
334 CH_8139A_G,
335 CH_8139B,
336 CH_8130,
337 CH_8139C,
338 CH_8100,
339 CH_8100B_8139D,
340 CH_8101,
c227f099 341} chip_t;
a41b2ff2
PB		 342
343enum chip_flags {
344 HasHltClk = (1 << 0),
345 HasLWake = (1 << 1),
346};
347
348#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
349 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
350#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
351
6cadb320
FB		 352#define RTL8139_PCI_REVID_8139 0x10
353#define RTL8139_PCI_REVID_8139CPLUS 0x20
354
355#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
356
a41b2ff2
PB		 357/* Size is 64 * 16bit words */
358#define EEPROM_9346_ADDR_BITS 6
359#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
360#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
361
362enum Chip9346Operation
363{
364 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
365 Chip9346_op_read = 0x80, /* 10 AAAAAA */
366 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
367 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
368 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
369 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
370 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
371};
372
373enum Chip9346Mode
374{
375 Chip9346_none = 0,
376 Chip9346_enter_command_mode,
377 Chip9346_read_command,
378 Chip9346_data_read, /* from output register */
379 Chip9346_data_write, /* to input register, then to contents at specified address */
380 Chip9346_data_write_all, /* to input register, then filling contents */
381};
382
383typedef struct EEprom9346
384{
385 uint16_t contents[EEPROM_9346_SIZE];
386 int mode;
387 uint32_t tick;
388 uint8_t address;
389 uint16_t input;
390 uint16_t output;
391
392 uint8_t eecs;
393 uint8_t eesk;
394 uint8_t eedi;
395 uint8_t eedo;
396} EEprom9346;
397
6cadb320
FB		 398typedef struct RTL8139TallyCounters
399{
400 /* Tally counters */
401 uint64_t TxOk;
402 uint64_t RxOk;
403 uint64_t TxERR;
404 uint32_t RxERR;
405 uint16_t MissPkt;
406 uint16_t FAE;
407 uint32_t Tx1Col;
408 uint32_t TxMCol;
409 uint64_t RxOkPhy;
410 uint64_t RxOkBrd;
411 uint32_t RxOkMul;
412 uint16_t TxAbt;
413 uint16_t TxUndrn;
414} RTL8139TallyCounters;
415
416/* Clears all tally counters */
417static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
418
419/* Writes tally counters to specified physical memory address */
c227f099 420static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 421
a41b2ff2 422typedef struct RTL8139State {
efd6dd45 423 PCIDevice dev;
a41b2ff2
PB		 424 uint8_t phys[8]; /* mac address */
425 uint8_t mult[8]; /* multicast mask array */
426
6cadb320 427 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 428 uint32_t TxAddr[4]; /* TxAddr0 */
429 uint32_t RxBuf; /* Receive buffer */
430 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
431 uint32_t RxBufPtr;
432 uint32_t RxBufAddr;
433
434 uint16_t IntrStatus;
435 uint16_t IntrMask;
436
437 uint32_t TxConfig;
438 uint32_t RxConfig;
439 uint32_t RxMissed;
440
441 uint16_t CSCR;
442
443 uint8_t Cfg9346;
444 uint8_t Config0;
445 uint8_t Config1;
446 uint8_t Config3;
447 uint8_t Config4;
448 uint8_t Config5;
449
450 uint8_t clock_enabled;
451 uint8_t bChipCmdState;
452
453 uint16_t MultiIntr;
454
455 uint16_t BasicModeCtrl;
456 uint16_t BasicModeStatus;
457 uint16_t NWayAdvert;
458 uint16_t NWayLPAR;
459 uint16_t NWayExpansion;
460
461 uint16_t CpCmd;
462 uint8_t TxThresh;
463
1673ad51 464 NICState *nic;
254111ec 465 NICConf conf;
a41b2ff2
PB		 466 int rtl8139_mmio_io_addr;
467
468 /* C ring mode */
469 uint32_t currTxDesc;
470
471 /* C+ mode */
2c3891ab
AL		 472 uint32_t cplus_enabled;
473
a41b2ff2
PB		 474 uint32_t currCPlusRxDesc;
475 uint32_t currCPlusTxDesc;
476
477 uint32_t RxRingAddrLO;
478 uint32_t RxRingAddrHI;
479
480 EEprom9346 eeprom;
6cadb320
FB		 481
482 uint32_t TCTR;
483 uint32_t TimerInt;
484 int64_t TCTR_base;
485
486 /* Tally counters */
487 RTL8139TallyCounters tally_counters;
488
489 /* Non-persistent data */
490 uint8_t *cplus_txbuffer;
491 int cplus_txbuffer_len;
492 int cplus_txbuffer_offset;
493
494 /* PCI interrupt timer */
495 QEMUTimer *timer;
05447803 496 int64_t TimerExpire;
6cadb320 497
c574ba5a
AW		 498 /* Support migration to/from old versions */
499 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 500} RTL8139State;
501
05447803
FZ		 502static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
503
9596ebb7 504static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 505{
6cadb320 506 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 507
508 switch (command & Chip9346_op_mask)
509 {
510 case Chip9346_op_read:
511 {
512 eeprom->address = command & EEPROM_9346_ADDR_MASK;
513 eeprom->output = eeprom->contents[eeprom->address];
514 eeprom->eedo = 0;
515 eeprom->tick = 0;
516 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 517 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
518 eeprom->address, eeprom->output));
a41b2ff2
PB		 519 }
520 break;
521
522 case Chip9346_op_write:
523 {
524 eeprom->address = command & EEPROM_9346_ADDR_MASK;
525 eeprom->input = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 528 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
529 eeprom->address));
a41b2ff2
PB		 530 }
531 break;
532 default:
533 eeprom->mode = Chip9346_none;
534 switch (command & Chip9346_op_ext_mask)
535 {
536 case Chip9346_op_write_enable:
6cadb320 537 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 538 break;
539 case Chip9346_op_write_all:
6cadb320 540 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 541 break;
542 case Chip9346_op_write_disable:
6cadb320 543 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 544 break;
545 }
546 break;
547 }
548}
549
9596ebb7 550static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 551{
552 int bit = eeprom->eedi?1:0;
553
554 ++ eeprom->tick;
555
6cadb320 556 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 557
558 switch (eeprom->mode)
559 {
560 case Chip9346_enter_command_mode:
561 if (bit)
562 {
563 eeprom->mode = Chip9346_read_command;
564 eeprom->tick = 0;
565 eeprom->input = 0;
6cadb320 566 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 567 }
568 break;
569
570 case Chip9346_read_command:
571 eeprom->input = (eeprom->input << 1) | (bit & 1);
572 if (eeprom->tick == 8)
573 {
574 prom9346_decode_command(eeprom, eeprom->input & 0xff);
575 }
576 break;
577
578 case Chip9346_data_read:
579 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
580 eeprom->output <<= 1;
581 if (eeprom->tick == 16)
582 {
6cadb320
FB		 583#if 1
584 // the FreeBSD drivers (rl and re) don't explicitly toggle
585 // CS between reads (or does setting Cfg9346 to 0 count too?),
586 // so we need to enter wait-for-command state here
587 eeprom->mode = Chip9346_enter_command_mode;
588 eeprom->input = 0;
589 eeprom->tick = 0;
590
591 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
592#else
593 // original behaviour
a41b2ff2
PB		 594 ++eeprom->address;
595 eeprom->address &= EEPROM_9346_ADDR_MASK;
596 eeprom->output = eeprom->contents[eeprom->address];
597 eeprom->tick = 0;
598
6cadb320
FB		 599 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
600 eeprom->address, eeprom->output));
a41b2ff2
PB		 601#endif
602 }
603 break;
604
605 case Chip9346_data_write:
606 eeprom->input = (eeprom->input << 1) | (bit & 1);
607 if (eeprom->tick == 16)
608 {
6cadb320
FB		 609 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
610 eeprom->address, eeprom->input));
611
a41b2ff2
PB		 612 eeprom->contents[eeprom->address] = eeprom->input;
613 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
614 eeprom->tick = 0;
615 eeprom->input = 0;
616 }
617 break;
618
619 case Chip9346_data_write_all:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
623 int i;
624 for (i = 0; i < EEPROM_9346_SIZE; i++)
625 {
626 eeprom->contents[i] = eeprom->input;
627 }
6cadb320
FB		 628 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
629 eeprom->input));
630
a41b2ff2
PB		 631 eeprom->mode = Chip9346_enter_command_mode;
632 eeprom->tick = 0;
633 eeprom->input = 0;
634 }
635 break;
636
637 default:
638 break;
639 }
640}
641
9596ebb7 642static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 643{
644 EEprom9346 *eeprom = &s->eeprom;
645 if (!eeprom->eecs)
646 return 0;
647
648 return eeprom->eedo;
649}
650
9596ebb7
PB		 651/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
652static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 653{
654 EEprom9346 *eeprom = &s->eeprom;
655 uint8_t old_eecs = eeprom->eecs;
656 uint8_t old_eesk = eeprom->eesk;
657
658 eeprom->eecs = eecs;
659 eeprom->eesk = eesk;
660 eeprom->eedi = eedi;
661
6cadb320
FB		 662 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
663 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 664
665 if (!old_eecs && eecs)
666 {
667 /* Synchronize start */
668 eeprom->tick = 0;
669 eeprom->input = 0;
670 eeprom->output = 0;
671 eeprom->mode = Chip9346_enter_command_mode;
672
6cadb320 673 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 674 }
675
676 if (!eecs)
677 {
6cadb320 678 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 679 return;
680 }
681
682 if (!old_eesk && eesk)
683 {
684 /* SK front rules */
685 prom9346_shift_clock(eeprom);
686 }
687}
688
689static void rtl8139_update_irq(RTL8139State *s)
690{
691 int isr;
692 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 693
80a34d67
PB		 694 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
695 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 696
efd6dd45 697 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 698}
699
700#define POLYNOMIAL 0x04c11db6
701
702/* From FreeBSD */
703/* XXX: optimize */
704static int compute_mcast_idx(const uint8_t *ep)
705{
706 uint32_t crc;
707 int carry, i, j;
708 uint8_t b;
709
710 crc = 0xffffffff;
711 for (i = 0; i < 6; i++) {
712 b = *ep++;
713 for (j = 0; j < 8; j++) {
714 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
715 crc <<= 1;
716 b >>= 1;
717 if (carry)
718 crc = ((crc ^ POLYNOMIAL) | carry);
719 }
720 }
721 return (crc >> 26);
722}
723
724static int rtl8139_RxWrap(RTL8139State *s)
725{
726 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
727 return (s->RxConfig & (1 << 7));
728}
729
730static int rtl8139_receiver_enabled(RTL8139State *s)
731{
732 return s->bChipCmdState & CmdRxEnb;
733}
734
735static int rtl8139_transmitter_enabled(RTL8139State *s)
736{
737 return s->bChipCmdState & CmdTxEnb;
738}
739
740static int rtl8139_cp_receiver_enabled(RTL8139State *s)
741{
742 return s->CpCmd & CPlusRxEnb;
743}
744
745static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
746{
747 return s->CpCmd & CPlusTxEnb;
748}
749
750static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
751{
752 if (s->RxBufAddr + size > s->RxBufferSize)
753 {
754 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
755
756 /* write packet data */
ccf1d14a 757 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 758 {
6cadb320 759 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 760
761 if (size > wrapped)
762 {
763 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
764 buf, size-wrapped );
765 }
766
767 /* reset buffer pointer */
768 s->RxBufAddr = 0;
769
770 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
771 buf + (size-wrapped), wrapped );
772
773 s->RxBufAddr = wrapped;
774
775 return;
776 }
777 }
778
779 /* non-wrapping path or overwrapping enabled */
780 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
781
782 s->RxBufAddr += size;
783}
784
785#define MIN_BUF_SIZE 60
c227f099 786static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 787{
788#if TARGET_PHYS_ADDR_BITS > 32
c227f099 789 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 790#else
791 return low;
792#endif
793}
794
1673ad51 795static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 796{
1673ad51 797 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 798 int avail;
799
aa1f17c1 800 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 801 if (!s->clock_enabled)
802 return 1;
803 if (!rtl8139_receiver_enabled(s))
804 return 1;
805
806 if (rtl8139_cp_receiver_enabled(s)) {
807 /* ??? Flow control not implemented in c+ mode.
808 This is a hack to work around slirp deficiencies anyway. */
809 return 1;
810 } else {
811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
812 s->RxBufferSize);
813 return (avail == 0 || avail >= 1514);
814 }
815}
816
1673ad51 817static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 818{
1673ad51 819 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
4f1c942b 820 int size = size_;
a41b2ff2
PB		 821
822 uint32_t packet_header = 0;
823
824 uint8_t buf1[60];
5fafdf24 825 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 826 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
827
6cadb320 828 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 829
830 /* test if board clock is stopped */
831 if (!s->clock_enabled)
832 {
6cadb320 833 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
4f1c942b 834 return -1;
a41b2ff2
PB		 835 }
836
837 /* first check if receiver is enabled */
838
839 if (!rtl8139_receiver_enabled(s))
840 {
6cadb320 841 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
4f1c942b 842 return -1;
a41b2ff2
PB		 843 }
844
845 /* XXX: check this */
846 if (s->RxConfig & AcceptAllPhys) {
847 /* promiscuous: receive all */
6cadb320 848 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 849
850 } else {
851 if (!memcmp(buf, broadcast_macaddr, 6)) {
852 /* broadcast address */
853 if (!(s->RxConfig & AcceptBroadcast))
854 {
6cadb320
FB		 855 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
856
857 /* update tally counter */
858 ++s->tally_counters.RxERR;
859
4f1c942b 860 return size;
a41b2ff2
PB		 861 }
862
863 packet_header |= RxBroadcast;
864
6cadb320
FB		 865 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
866
867 /* update tally counter */
868 ++s->tally_counters.RxOkBrd;
869
a41b2ff2
PB		 870 } else if (buf[0] & 0x01) {
871 /* multicast */
872 if (!(s->RxConfig & AcceptMulticast))
873 {
6cadb320
FB		 874 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
875
876 /* update tally counter */
877 ++s->tally_counters.RxERR;
878
4f1c942b 879 return size;
a41b2ff2
PB		 880 }
881
882 int mcast_idx = compute_mcast_idx(buf);
883
884 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
885 {
6cadb320
FB		 886 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
887
888 /* update tally counter */
889 ++s->tally_counters.RxERR;
890
4f1c942b 891 return size;
a41b2ff2
PB		 892 }
893
894 packet_header |= RxMulticast;
895
6cadb320
FB		 896 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
897
898 /* update tally counter */
899 ++s->tally_counters.RxOkMul;
900
a41b2ff2 901 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 902 s->phys[1] == buf[1] &&
903 s->phys[2] == buf[2] &&
904 s->phys[3] == buf[3] &&
905 s->phys[4] == buf[4] &&
a41b2ff2
PB		 906 s->phys[5] == buf[5]) {
907 /* match */
908 if (!(s->RxConfig & AcceptMyPhys))
909 {
6cadb320
FB		 910 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
911
912 /* update tally counter */
913 ++s->tally_counters.RxERR;
914
4f1c942b 915 return size;
a41b2ff2
PB		 916 }
917
918 packet_header |= RxPhysical;
919
6cadb320
FB		 920 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
921
922 /* update tally counter */
923 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 924
925 } else {
926
6cadb320
FB		 927 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
928
929 /* update tally counter */
930 ++s->tally_counters.RxERR;
931
4f1c942b 932 return size;
a41b2ff2
PB		 933 }
934 }
935
936 /* if too small buffer, then expand it */
937 if (size < MIN_BUF_SIZE) {
938 memcpy(buf1, buf, size);
939 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
940 buf = buf1;
941 size = MIN_BUF_SIZE;
942 }
943
944 if (rtl8139_cp_receiver_enabled(s))
945 {
6cadb320 946 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 947
948 /* begin C+ receiver mode */
949
950/* w0 ownership flag */
951#define CP_RX_OWN (1<<31)
952/* w0 end of ring flag */
953#define CP_RX_EOR (1<<30)
954/* w0 bits 0...12 : buffer size */
955#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
956/* w1 tag available flag */
957#define CP_RX_TAVA (1<<16)
958/* w1 bits 0...15 : VLAN tag */
959#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
960/* w2 low 32bit of Rx buffer ptr */
961/* w3 high 32bit of Rx buffer ptr */
962
963 int descriptor = s->currCPlusRxDesc;
c227f099 964 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 965
966 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
967 cplus_rx_ring_desc += 16 * descriptor;
968
6cadb320
FB		 969 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
970 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 971
972 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
973
974 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
975 rxdw0 = le32_to_cpu(val);
976 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
977 rxdw1 = le32_to_cpu(val);
978 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
979 rxbufLO = le32_to_cpu(val);
980 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
981 rxbufHI = le32_to_cpu(val);
982
6cadb320 983 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 984 descriptor,
6cadb320 985 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 986
987 if (!(rxdw0 & CP_RX_OWN))
988 {
6cadb320
FB		 989 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
990
a41b2ff2
PB		 991 s->IntrStatus |= RxOverflow;
992 ++s->RxMissed;
6cadb320
FB		 993
994 /* update tally counter */
995 ++s->tally_counters.RxERR;
996 ++s->tally_counters.MissPkt;
997
a41b2ff2 998 rtl8139_update_irq(s);
4f1c942b 999 return size_;
a41b2ff2
PB		 1000 }
1001
1002 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1003
6cadb320
FB		 1004 /* TODO: scatter the packet over available receive ring descriptors space */
1005
a41b2ff2
PB		 1006 if (size+4 > rx_space)
1007 {
6cadb320
FB		 1008 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1009 descriptor, rx_space, size));
1010
a41b2ff2
PB		 1011 s->IntrStatus |= RxOverflow;
1012 ++s->RxMissed;
6cadb320
FB		 1013
1014 /* update tally counter */
1015 ++s->tally_counters.RxERR;
1016 ++s->tally_counters.MissPkt;
1017
a41b2ff2 1018 rtl8139_update_irq(s);
4f1c942b 1019 return size_;
a41b2ff2
PB		 1020 }
1021
c227f099 1022 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1023
1024 /* receive/copy to target memory */
1025 cpu_physical_memory_write( rx_addr, buf, size );
1026
6cadb320
FB		 1027 if (s->CpCmd & CPlusRxChkSum)
1028 {
1029 /* do some packet checksumming */
1030 }
1031
a41b2ff2
PB		 1032 /* write checksum */
1033#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1034 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1035#else
1036 val = 0;
1037#endif
1038 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1039
1040/* first segment of received packet flag */
1041#define CP_RX_STATUS_FS (1<<29)
1042/* last segment of received packet flag */
1043#define CP_RX_STATUS_LS (1<<28)
1044/* multicast packet flag */
1045#define CP_RX_STATUS_MAR (1<<26)
1046/* physical-matching packet flag */
1047#define CP_RX_STATUS_PAM (1<<25)
1048/* broadcast packet flag */
1049#define CP_RX_STATUS_BAR (1<<24)
1050/* runt packet flag */
1051#define CP_RX_STATUS_RUNT (1<<19)
1052/* crc error flag */
1053#define CP_RX_STATUS_CRC (1<<18)
1054/* IP checksum error flag */
1055#define CP_RX_STATUS_IPF (1<<15)
1056/* UDP checksum error flag */
1057#define CP_RX_STATUS_UDPF (1<<14)
1058/* TCP checksum error flag */
1059#define CP_RX_STATUS_TCPF (1<<13)
1060
1061 /* transfer ownership to target */
1062 rxdw0 &= ~CP_RX_OWN;
1063
1064 /* set first segment bit */
1065 rxdw0 |= CP_RX_STATUS_FS;
1066
1067 /* set last segment bit */
1068 rxdw0 |= CP_RX_STATUS_LS;
1069
1070 /* set received packet type flags */
1071 if (packet_header & RxBroadcast)
1072 rxdw0 |= CP_RX_STATUS_BAR;
1073 if (packet_header & RxMulticast)
1074 rxdw0 |= CP_RX_STATUS_MAR;
1075 if (packet_header & RxPhysical)
1076 rxdw0 |= CP_RX_STATUS_PAM;
1077
1078 /* set received size */
1079 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1080 rxdw0 |= (size+4);
1081
1082 /* reset VLAN tag flag */
1083 rxdw1 &= ~CP_RX_TAVA;
1084
1085 /* update ring data */
1086 val = cpu_to_le32(rxdw0);
1087 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1088 val = cpu_to_le32(rxdw1);
1089 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1090
6cadb320
FB		 1091 /* update tally counter */
1092 ++s->tally_counters.RxOk;
1093
a41b2ff2
PB		 1094 /* seek to next Rx descriptor */
1095 if (rxdw0 & CP_RX_EOR)
1096 {
1097 s->currCPlusRxDesc = 0;
1098 }
1099 else
1100 {
1101 ++s->currCPlusRxDesc;
1102 }
1103
6cadb320 1104 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1105
1106 }
1107 else
1108 {
6cadb320
FB		 1109 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1110
a41b2ff2
PB		 1111 /* begin ring receiver mode */
1112 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1113
1114 /* if receiver buffer is empty then avail == 0 */
1115
1116 if (avail != 0 && size + 8 >= avail)
1117 {
6cadb320
FB		 1118 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1119 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1120
a41b2ff2
PB		 1121 s->IntrStatus |= RxOverflow;
1122 ++s->RxMissed;
1123 rtl8139_update_irq(s);
4f1c942b 1124 return size_;
a41b2ff2
PB		 1125 }
1126
1127 packet_header |= RxStatusOK;
1128
1129 packet_header |= (((size+4) << 16) & 0xffff0000);
1130
1131 /* write header */
1132 uint32_t val = cpu_to_le32(packet_header);
1133
1134 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1135
1136 rtl8139_write_buffer(s, buf, size);
1137
1138 /* write checksum */
1139#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1140 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1141#else
1142 val = 0;
1143#endif
1144
1145 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1146
1147 /* correct buffer write pointer */
1148 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1149
1150 /* now we can signal we have received something */
1151
6cadb320
FB		 1152 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1153 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1154 }
1155
1156 s->IntrStatus |= RxOK;
6cadb320
FB		 1157
1158 if (do_interrupt)
1159 {
1160 rtl8139_update_irq(s);
1161 }
4f1c942b
MM		 1162
1163 return size_;
6cadb320
FB		 1164}
1165
1673ad51 1166static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1167{
1673ad51 1168 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1169}
1170
1171static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1172{
1173 s->RxBufferSize = bufferSize;
1174 s->RxBufPtr = 0;
1175 s->RxBufAddr = 0;
1176}
1177
7f23f812 1178static void rtl8139_reset(DeviceState *d)
a41b2ff2 1179{
7f23f812 1180 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1181 int i;
1182
1183 /* restore MAC address */
254111ec 1184 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1185
1186 /* reset interrupt mask */
1187 s->IntrStatus = 0;
1188 s->IntrMask = 0;
1189
1190 rtl8139_update_irq(s);
1191
1192 /* prepare eeprom */
1193 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1194#if 1
1195 // PCI vendor and device ID should be mirrored here
deb54399
AL		 1196 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1197 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
6cadb320 1198#endif
290a0933 1199
254111ec
GH		 1200 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
1201 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
1202 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
a41b2ff2
PB		 1203
1204 /* mark all status registers as owned by host */
1205 for (i = 0; i < 4; ++i)
1206 {
1207 s->TxStatus[i] = TxHostOwns;
1208 }
1209
1210 s->currTxDesc = 0;
1211 s->currCPlusRxDesc = 0;
1212 s->currCPlusTxDesc = 0;
1213
1214 s->RxRingAddrLO = 0;
1215 s->RxRingAddrHI = 0;
1216
1217 s->RxBuf = 0;
1218
1219 rtl8139_reset_rxring(s, 8192);
1220
1221 /* ACK the reset */
1222 s->TxConfig = 0;
1223
1224#if 0
1225// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1226 s->clock_enabled = 0;
1227#else
6cadb320 1228 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1229 s->clock_enabled = 1;
1230#endif
1231
1232 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1233
1234 /* set initial state data */
1235 s->Config0 = 0x0; /* No boot ROM */
1236 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1237 s->Config3 = 0x1; /* fast back-to-back compatible */
1238 s->Config5 = 0x0;
1239
5fafdf24 1240 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1241
1242 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1243 s->cplus_enabled = 0;
1244
a41b2ff2
PB		 1245
1246// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1247// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1248 s->BasicModeCtrl = 0x1000; // autonegotiation
1249
1250 s->BasicModeStatus = 0x7809;
1251 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1252 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1253 s->BasicModeStatus |= 0x0004; /* link is up */
1254
1255 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1256 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1257 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1258
1259 /* also reset timer and disable timer interrupt */
1260 s->TCTR = 0;
1261 s->TimerInt = 0;
1262 s->TCTR_base = 0;
1263
1264 /* reset tally counters */
1265 RTL8139TallyCounters_clear(&s->tally_counters);
1266}
1267
b1d8e52e 1268static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1269{
1270 counters->TxOk = 0;
1271 counters->RxOk = 0;
1272 counters->TxERR = 0;
1273 counters->RxERR = 0;
1274 counters->MissPkt = 0;
1275 counters->FAE = 0;
1276 counters->Tx1Col = 0;
1277 counters->TxMCol = 0;
1278 counters->RxOkPhy = 0;
1279 counters->RxOkBrd = 0;
1280 counters->RxOkMul = 0;
1281 counters->TxAbt = 0;
1282 counters->TxUndrn = 0;
1283}
1284
c227f099 1285static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1286{
1287 uint16_t val16;
1288 uint32_t val32;
1289 uint64_t val64;
1290
1291 val64 = cpu_to_le64(tally_counters->TxOk);
1292 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1293
1294 val64 = cpu_to_le64(tally_counters->RxOk);
1295 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1296
1297 val64 = cpu_to_le64(tally_counters->TxERR);
1298 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1299
1300 val32 = cpu_to_le32(tally_counters->RxERR);
1301 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1302
1303 val16 = cpu_to_le16(tally_counters->MissPkt);
1304 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1305
1306 val16 = cpu_to_le16(tally_counters->FAE);
1307 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1308
1309 val32 = cpu_to_le32(tally_counters->Tx1Col);
1310 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1311
1312 val32 = cpu_to_le32(tally_counters->TxMCol);
1313 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1314
1315 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1316 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1317
1318 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1319 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1320
1321 val32 = cpu_to_le32(tally_counters->RxOkMul);
1322 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1323
1324 val16 = cpu_to_le16(tally_counters->TxAbt);
1325 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1326
1327 val16 = cpu_to_le16(tally_counters->TxUndrn);
1328 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1329}
1330
1331/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1332
1333static const VMStateDescription vmstate_tally_counters = {
1334 .name = "tally_counters",
1335 .version_id = 1,
1336 .minimum_version_id = 1,
1337 .minimum_version_id_old = 1,
1338 .fields = (VMStateField []) {
1339 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1340 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1341 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1342 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1343 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1344 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1345 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1346 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1347 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1348 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1349 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1350 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1351 VMSTATE_END_OF_LIST()
1352 }
1353};
a41b2ff2
PB		 1354
1355static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1356{
1357 val &= 0xff;
1358
6cadb320 1359 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1360
1361 if (val & CmdReset)
1362 {
6cadb320 1363 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
7f23f812 1364 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1365 }
1366 if (val & CmdRxEnb)
1367 {
6cadb320 1368 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1369
1370 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1371 }
1372 if (val & CmdTxEnb)
1373 {
6cadb320 1374 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1375
1376 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1377 }
1378
1379 /* mask unwriteable bits */
1380 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1381
1382 /* Deassert reset pin before next read */
1383 val &= ~CmdReset;
1384
1385 s->bChipCmdState = val;
1386}
1387
1388static int rtl8139_RxBufferEmpty(RTL8139State *s)
1389{
1390 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1391
1392 if (unread != 0)
1393 {
6cadb320 1394 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1395 return 0;
1396 }
1397
6cadb320 1398 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1399
1400 return 1;
1401}
1402
1403static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1404{
1405 uint32_t ret = s->bChipCmdState;
1406
1407 if (rtl8139_RxBufferEmpty(s))
1408 ret |= RxBufEmpty;
1409
6cadb320 1410 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1411
1412 return ret;
1413}
1414
1415static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1416{
1417 val &= 0xffff;
1418
6cadb320 1419 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2 1420
2c3891ab
AL		 1421 s->cplus_enabled = 1;
1422
a41b2ff2
PB		 1423 /* mask unwriteable bits */
1424 val = SET_MASKED(val, 0xff84, s->CpCmd);
1425
1426 s->CpCmd = val;
1427}
1428
1429static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1430{
1431 uint32_t ret = s->CpCmd;
1432
6cadb320
FB		 1433 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1434
1435 return ret;
1436}
1437
1438static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1439{
1440 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1441}
1442
1443static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1444{
1445 uint32_t ret = 0;
1446
1447 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1448
1449 return ret;
1450}
1451
9596ebb7 1452static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1453{
1454 if (s->Cfg9346 & Cfg9346_Unlock)
1455 {
1456 return 1;
1457 }
1458
6cadb320 1459 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1460
1461 return 0;
1462}
1463
1464static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1465{
1466 val &= 0xffff;
1467
6cadb320 1468 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1469
1470 /* mask unwriteable bits */
e3d7e843 1471 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1472
1473 if (1 || !rtl8139_config_writeable(s))
1474 {
1475 /* Speed setting and autonegotiation enable bits are read-only */
1476 mask |= 0x3000;
1477 /* Duplex mode setting is read-only */
1478 mask |= 0x0100;
1479 }
1480
1481 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1482
1483 s->BasicModeCtrl = val;
1484}
1485
1486static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1487{
1488 uint32_t ret = s->BasicModeCtrl;
1489
6cadb320 1490 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1491
1492 return ret;
1493}
1494
1495static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1496{
1497 val &= 0xffff;
1498
6cadb320 1499 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1500
1501 /* mask unwriteable bits */
1502 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1503
1504 s->BasicModeStatus = val;
1505}
1506
1507static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1508{
1509 uint32_t ret = s->BasicModeStatus;
1510
6cadb320 1511 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1512
1513 return ret;
1514}
1515
1516static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1517{
1518 val &= 0xff;
1519
6cadb320 1520 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1521
1522 /* mask unwriteable bits */
1523 val = SET_MASKED(val, 0x31, s->Cfg9346);
1524
1525 uint32_t opmode = val & 0xc0;
1526 uint32_t eeprom_val = val & 0xf;
1527
1528 if (opmode == 0x80) {
1529 /* eeprom access */
1530 int eecs = (eeprom_val & 0x08)?1:0;
1531 int eesk = (eeprom_val & 0x04)?1:0;
1532 int eedi = (eeprom_val & 0x02)?1:0;
1533 prom9346_set_wire(s, eecs, eesk, eedi);
1534 } else if (opmode == 0x40) {
1535 /* Reset. */
1536 val = 0;
7f23f812 1537 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1538 }
1539
1540 s->Cfg9346 = val;
1541}
1542
1543static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1544{
1545 uint32_t ret = s->Cfg9346;
1546
1547 uint32_t opmode = ret & 0xc0;
1548
1549 if (opmode == 0x80)
1550 {
1551 /* eeprom access */
1552 int eedo = prom9346_get_wire(s);
1553 if (eedo)
1554 {
1555 ret |= 0x01;
1556 }
1557 else
1558 {
1559 ret &= ~0x01;
1560 }
1561 }
1562
6cadb320 1563 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1564
1565 return ret;
1566}
1567
1568static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1569{
1570 val &= 0xff;
1571
6cadb320 1572 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1573
1574 if (!rtl8139_config_writeable(s))
1575 return;
1576
1577 /* mask unwriteable bits */
1578 val = SET_MASKED(val, 0xf8, s->Config0);
1579
1580 s->Config0 = val;
1581}
1582
1583static uint32_t rtl8139_Config0_read(RTL8139State *s)
1584{
1585 uint32_t ret = s->Config0;
1586
6cadb320 1587 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1588
1589 return ret;
1590}
1591
1592static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1593{
1594 val &= 0xff;
1595
6cadb320 1596 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1597
1598 if (!rtl8139_config_writeable(s))
1599 return;
1600
1601 /* mask unwriteable bits */
1602 val = SET_MASKED(val, 0xC, s->Config1);
1603
1604 s->Config1 = val;
1605}
1606
1607static uint32_t rtl8139_Config1_read(RTL8139State *s)
1608{
1609 uint32_t ret = s->Config1;
1610
6cadb320 1611 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1612
1613 return ret;
1614}
1615
1616static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1617{
1618 val &= 0xff;
1619
6cadb320 1620 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1621
1622 if (!rtl8139_config_writeable(s))
1623 return;
1624
1625 /* mask unwriteable bits */
1626 val = SET_MASKED(val, 0x8F, s->Config3);
1627
1628 s->Config3 = val;
1629}
1630
1631static uint32_t rtl8139_Config3_read(RTL8139State *s)
1632{
1633 uint32_t ret = s->Config3;
1634
6cadb320 1635 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1636
1637 return ret;
1638}
1639
1640static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1641{
1642 val &= 0xff;
1643
6cadb320 1644 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1645
1646 if (!rtl8139_config_writeable(s))
1647 return;
1648
1649 /* mask unwriteable bits */
1650 val = SET_MASKED(val, 0x0a, s->Config4);
1651
1652 s->Config4 = val;
1653}
1654
1655static uint32_t rtl8139_Config4_read(RTL8139State *s)
1656{
1657 uint32_t ret = s->Config4;
1658
6cadb320 1659 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1660
1661 return ret;
1662}
1663
1664static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1665{
1666 val &= 0xff;
1667
6cadb320 1668 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1669
1670 /* mask unwriteable bits */
1671 val = SET_MASKED(val, 0x80, s->Config5);
1672
1673 s->Config5 = val;
1674}
1675
1676static uint32_t rtl8139_Config5_read(RTL8139State *s)
1677{
1678 uint32_t ret = s->Config5;
1679
6cadb320 1680 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1681
1682 return ret;
1683}
1684
1685static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1686{
1687 if (!rtl8139_transmitter_enabled(s))
1688 {
6cadb320 1689 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1690 return;
1691 }
1692
6cadb320 1693 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1694
1695 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1696
1697 s->TxConfig = val;
1698}
1699
1700static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1701{
6cadb320
FB		 1702 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1703
1704 uint32_t tc = s->TxConfig;
1705 tc &= 0xFFFFFF00;
1706 tc |= (val & 0x000000FF);
1707 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1708}
1709
1710static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1711{
1712 uint32_t ret = s->TxConfig;
1713
6cadb320 1714 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1715
1716 return ret;
1717}
1718
1719static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1720{
6cadb320 1721 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1722
1723 /* mask unwriteable bits */
1724 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1725
1726 s->RxConfig = val;
1727
1728 /* reset buffer size and read/write pointers */
1729 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1730
6cadb320 1731 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1732}
1733
1734static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1735{
1736 uint32_t ret = s->RxConfig;
1737
6cadb320 1738 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1739
1740 return ret;
1741}
1742
718da2b9
FB		 1743static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1744{
1745 if (!size)
1746 {
1747 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1748 return;
1749 }
1750
1751 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1752 {
1753 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1673ad51 1754 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
718da2b9
FB		 1755 }
1756 else
1757 {
1673ad51 1758 qemu_send_packet(&s->nic->nc, buf, size);
718da2b9
FB		 1759 }
1760}
1761
a41b2ff2
PB		 1762static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1763{
1764 if (!rtl8139_transmitter_enabled(s))
1765 {
6cadb320
FB		 1766 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1767 descriptor));
a41b2ff2
PB		 1768 return 0;
1769 }
1770
1771 if (s->TxStatus[descriptor] & TxHostOwns)
1772 {
6cadb320
FB		 1773 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1774 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1775 return 0;
1776 }
1777
6cadb320 1778 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1779
1780 int txsize = s->TxStatus[descriptor] & 0x1fff;
1781 uint8_t txbuffer[0x2000];
1782
6cadb320
FB		 1783 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1784 txsize, s->TxAddr[descriptor]));
a41b2ff2 1785
6cadb320 1786 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1787
1788 /* Mark descriptor as transferred */
1789 s->TxStatus[descriptor] |= TxHostOwns;
1790 s->TxStatus[descriptor] |= TxStatOK;
1791
718da2b9 1792 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1793
1794 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1795
1796 /* update interrupt */
1797 s->IntrStatus |= TxOK;
1798 rtl8139_update_irq(s);
1799
1800 return 1;
1801}
1802
718da2b9
FB		 1803/* structures and macros for task offloading */
1804typedef struct ip_header
1805{
1806 uint8_t ip_ver_len; /* version and header length */
1807 uint8_t ip_tos; /* type of service */
1808 uint16_t ip_len; /* total length */
1809 uint16_t ip_id; /* identification */
1810 uint16_t ip_off; /* fragment offset field */
1811 uint8_t ip_ttl; /* time to live */
1812 uint8_t ip_p; /* protocol */
1813 uint16_t ip_sum; /* checksum */
1814 uint32_t ip_src,ip_dst; /* source and dest address */
1815} ip_header;
1816
1817#define IP_HEADER_VERSION_4 4
1818#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1819#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1820
1821typedef struct tcp_header
1822{
1823 uint16_t th_sport; /* source port */
1824 uint16_t th_dport; /* destination port */
1825 uint32_t th_seq; /* sequence number */
1826 uint32_t th_ack; /* acknowledgement number */
1827 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1828 uint16_t th_win; /* window */
1829 uint16_t th_sum; /* checksum */
1830 uint16_t th_urp; /* urgent pointer */
1831} tcp_header;
1832
1833typedef struct udp_header
1834{
1835 uint16_t uh_sport; /* source port */
1836 uint16_t uh_dport; /* destination port */
1837 uint16_t uh_ulen; /* udp length */
1838 uint16_t uh_sum; /* udp checksum */
1839} udp_header;
1840
1841typedef struct ip_pseudo_header
1842{
1843 uint32_t ip_src;
1844 uint32_t ip_dst;
1845 uint8_t zeros;
1846 uint8_t ip_proto;
1847 uint16_t ip_payload;
1848} ip_pseudo_header;
1849
1850#define IP_PROTO_TCP 6
1851#define IP_PROTO_UDP 17
1852
1853#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1854#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1855#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1856
1857#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1858
1859#define TCP_FLAG_FIN 0x01
1860#define TCP_FLAG_PUSH 0x08
1861
1862/* produces ones' complement sum of data */
1863static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1864{
1865 uint32_t result = 0;
1866
1867 for (; len > 1; data+=2, len-=2)
1868 {
1869 result += *(uint16_t*)data;
1870 }
1871
1872 /* add the remainder byte */
1873 if (len)
1874 {
1875 uint8_t odd[2] = {*data, 0};
1876 result += *(uint16_t*)odd;
1877 }
1878
1879 while (result>>16)
1880 result = (result & 0xffff) + (result >> 16);
1881
1882 return result;
1883}
1884
1885static uint16_t ip_checksum(void *data, size_t len)
1886{
1887 return ~ones_complement_sum((uint8_t*)data, len);
1888}
1889
a41b2ff2
PB		 1890static int rtl8139_cplus_transmit_one(RTL8139State *s)
1891{
1892 if (!rtl8139_transmitter_enabled(s))
1893 {
6cadb320 1894 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1895 return 0;
1896 }
1897
1898 if (!rtl8139_cp_transmitter_enabled(s))
1899 {
6cadb320 1900 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1901 return 0 ;
1902 }
1903
1904 int descriptor = s->currCPlusTxDesc;
1905
c227f099 1906 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1907 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1908
1909 /* Normal priority ring */
1910 cplus_tx_ring_desc += 16 * descriptor;
1911
6cadb320
FB		 1912 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1913 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1914
1915 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1916
1917 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1918 txdw0 = le32_to_cpu(val);
4ef1a3d3 1919 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 1920 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1921 txdw1 = le32_to_cpu(val);
1922 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1923 txbufLO = le32_to_cpu(val);
1924 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1925 txbufHI = le32_to_cpu(val);
1926
6cadb320 1927 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1928 descriptor,
6cadb320 1929 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2 1930
4ef1a3d3
IK		 1931 /* TODO: the following discard cast should clean clang analyzer output */
1932 (void)txdw1;
1933
a41b2ff2
PB		 1934/* w0 ownership flag */
1935#define CP_TX_OWN (1<<31)
1936/* w0 end of ring flag */
1937#define CP_TX_EOR (1<<30)
1938/* first segment of received packet flag */
1939#define CP_TX_FS (1<<29)
1940/* last segment of received packet flag */
1941#define CP_TX_LS (1<<28)
1942/* large send packet flag */
1943#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1944/* large send MSS mask, bits 16...25 */
1945#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1946
a41b2ff2
PB		 1947/* IP checksum offload flag */
1948#define CP_TX_IPCS (1<<18)
1949/* UDP checksum offload flag */
1950#define CP_TX_UDPCS (1<<17)
1951/* TCP checksum offload flag */
1952#define CP_TX_TCPCS (1<<16)
1953
1954/* w0 bits 0...15 : buffer size */
1955#define CP_TX_BUFFER_SIZE (1<<16)
1956#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1957/* w1 tag available flag */
1958#define CP_RX_TAGC (1<<17)
1959/* w1 bits 0...15 : VLAN tag */
1960#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1961/* w2 low 32bit of Rx buffer ptr */
1962/* w3 high 32bit of Rx buffer ptr */
1963
1964/* set after transmission */
1965/* FIFO underrun flag */
1966#define CP_TX_STATUS_UNF (1<<25)
1967/* transmit error summary flag, valid if set any of three below */
1968#define CP_TX_STATUS_TES (1<<23)
1969/* out-of-window collision flag */
1970#define CP_TX_STATUS_OWC (1<<22)
1971/* link failure flag */
1972#define CP_TX_STATUS_LNKF (1<<21)
1973/* excessive collisions flag */
1974#define CP_TX_STATUS_EXC (1<<20)
1975
1976 if (!(txdw0 & CP_TX_OWN))
1977 {
6cadb320 1978 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1979 return 0 ;
1980 }
1981
6cadb320
FB		 1982 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1983
1984 if (txdw0 & CP_TX_FS)
1985 {
1986 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1987
1988 /* reset internal buffer offset */
1989 s->cplus_txbuffer_offset = 0;
1990 }
a41b2ff2
PB		 1991
1992 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 1993 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 1994
6cadb320
FB		 1995 /* make sure we have enough space to assemble the packet */
1996 if (!s->cplus_txbuffer)
1997 {
1998 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 1999 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 2000 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 2001
2002 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 2003 }
2004
2005 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2006 {
2007 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2008 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2009
6cadb320
FB		 2010 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2011 }
2012
2013 if (!s->cplus_txbuffer)
2014 {
2015 /* out of memory */
a41b2ff2 2016
6cadb320
FB		 2017 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2018
2019 /* update tally counter */
2020 ++s->tally_counters.TxERR;
2021 ++s->tally_counters.TxAbt;
2022
2023 return 0;
2024 }
2025
2026 /* append more data to the packet */
2027
2028 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2029 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2030
2031 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2032 s->cplus_txbuffer_offset += txsize;
2033
2034 /* seek to next Rx descriptor */
2035 if (txdw0 & CP_TX_EOR)
2036 {
2037 s->currCPlusTxDesc = 0;
2038 }
2039 else
2040 {
2041 ++s->currCPlusTxDesc;
2042 if (s->currCPlusTxDesc >= 64)
2043 s->currCPlusTxDesc = 0;
2044 }
a41b2ff2
PB		 2045
2046 /* transfer ownership to target */
2047 txdw0 &= ~CP_RX_OWN;
2048
2049 /* reset error indicator bits */
2050 txdw0 &= ~CP_TX_STATUS_UNF;
2051 txdw0 &= ~CP_TX_STATUS_TES;
2052 txdw0 &= ~CP_TX_STATUS_OWC;
2053 txdw0 &= ~CP_TX_STATUS_LNKF;
2054 txdw0 &= ~CP_TX_STATUS_EXC;
2055
2056 /* update ring data */
2057 val = cpu_to_le32(txdw0);
2058 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
4ef1a3d3 2059 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 2060// val = cpu_to_le32(txdw1);
2061// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2062
6cadb320
FB		 2063 /* Now decide if descriptor being processed is holding the last segment of packet */
2064 if (txdw0 & CP_TX_LS)
a41b2ff2 2065 {
6cadb320
FB		 2066 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2067
2068 /* can transfer fully assembled packet */
2069
2070 uint8_t *saved_buffer = s->cplus_txbuffer;
2071 int saved_size = s->cplus_txbuffer_offset;
2072 int saved_buffer_len = s->cplus_txbuffer_len;
2073
2074 /* reset the card space to protect from recursive call */
2075 s->cplus_txbuffer = NULL;
2076 s->cplus_txbuffer_offset = 0;
2077 s->cplus_txbuffer_len = 0;
2078
718da2b9 2079 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2080 {
2081 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2082
2083 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2084 #define ETH_HLEN 14
718da2b9 2085 #define ETH_MTU 1500
6cadb320
FB		 2086
2087 /* ip packet header */
660f11be 2088 ip_header *ip = NULL;
6cadb320 2089 int hlen = 0;
718da2b9
FB		 2090 uint8_t ip_protocol = 0;
2091 uint16_t ip_data_len = 0;
6cadb320 2092
660f11be 2093 uint8_t *eth_payload_data = NULL;
718da2b9 2094 size_t eth_payload_len = 0;
6cadb320 2095
718da2b9 2096 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2097 if (proto == ETH_P_IP)
2098 {
2099 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2100
2101 /* not aligned */
718da2b9
FB		 2102 eth_payload_data = saved_buffer + ETH_HLEN;
2103 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2104
718da2b9 2105 ip = (ip_header*)eth_payload_data;
6cadb320 2106
718da2b9
FB		 2107 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2108 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2109 ip = NULL;
2110 } else {
718da2b9
FB		 2111 hlen = IP_HEADER_LENGTH(ip);
2112 ip_protocol = ip->ip_p;
2113 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2114 }
2115 }
2116
2117 if (ip)
2118 {
2119 if (txdw0 & CP_TX_IPCS)
2120 {
2121 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2122
718da2b9 2123 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2124 /* bad packet header len */
2125 /* or packet too short */
2126 }
2127 else
2128 {
2129 ip->ip_sum = 0;
718da2b9 2130 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2131 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2132 }
2133 }
2134
718da2b9 2135 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2136 {
718da2b9
FB		 2137#if defined (DEBUG_RTL8139)
2138 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2139#endif
2140 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2141 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2142
718da2b9
FB		 2143 int tcp_send_offset = 0;
2144 int send_count = 0;
6cadb320
FB		 2145
2146 /* maximum IP header length is 60 bytes */
2147 uint8_t saved_ip_header[60];
6cadb320 2148
718da2b9
FB		 2149 /* save IP header template; data area is used in tcp checksum calculation */
2150 memcpy(saved_ip_header, eth_payload_data, hlen);
2151
2152 /* a placeholder for checksum calculation routine in tcp case */
2153 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2154 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2155
2156 /* pointer to TCP header */
2157 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2158
2159 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2160
2161 /* ETH_MTU = ip header len + tcp header len + payload */
2162 int tcp_data_len = ip_data_len - tcp_hlen;
2163 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2164
2165 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2166 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2167
2168 /* note the cycle below overwrites IP header data,
2169 but restores it from saved_ip_header before sending packet */
2170
2171 int is_last_frame = 0;
2172
2173 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2174 {
2175 uint16_t chunk_size = tcp_chunk_size;
2176
2177 /* check if this is the last frame */
2178 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2179 {
2180 is_last_frame = 1;
2181 chunk_size = tcp_data_len - tcp_send_offset;
2182 }
2183
2184 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2185
2186 /* add 4 TCP pseudoheader fields */
2187 /* copy IP source and destination fields */
2188 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2189
2190 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2191
2192 if (tcp_send_offset)
2193 {
2194 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2195 }
2196
2197 /* keep PUSH and FIN flags only for the last frame */
2198 if (!is_last_frame)
2199 {
2200 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2201 }
6cadb320 2202
718da2b9
FB		 2203 /* recalculate TCP checksum */
2204 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2205 p_tcpip_hdr->zeros = 0;
2206 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2207 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2208
2209 p_tcp_hdr->th_sum = 0;
2210
2211 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2212 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2213
2214 p_tcp_hdr->th_sum = tcp_checksum;
2215
2216 /* restore IP header */
2217 memcpy(eth_payload_data, saved_ip_header, hlen);
2218
2219 /* set IP data length and recalculate IP checksum */
2220 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2221
2222 /* increment IP id for subsequent frames */
2223 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2224
2225 ip->ip_sum = 0;
2226 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2227 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2228
2229 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2230 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2231 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2232
2233 /* add transferred count to TCP sequence number */
2234 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2235 ++send_count;
2236 }
2237
2238 /* Stop sending this frame */
2239 saved_size = 0;
2240 }
2241 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2242 {
2243 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2244
2245 /* maximum IP header length is 60 bytes */
2246 uint8_t saved_ip_header[60];
2247 memcpy(saved_ip_header, eth_payload_data, hlen);
2248
2249 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2250 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2251
2252 /* add 4 TCP pseudoheader fields */
2253 /* copy IP source and destination fields */
718da2b9 2254 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2255
718da2b9 2256 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2257 {
2258 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2259
718da2b9
FB		 2260 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2261 p_tcpip_hdr->zeros = 0;
2262 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2263 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2264
718da2b9 2265 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2266
2267 p_tcp_hdr->th_sum = 0;
2268
718da2b9 2269 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2270 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2271
2272 p_tcp_hdr->th_sum = tcp_checksum;
2273 }
718da2b9 2274 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2275 {
2276 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2277
718da2b9
FB		 2278 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2279 p_udpip_hdr->zeros = 0;
2280 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2281 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2282
718da2b9 2283 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2284
6cadb320
FB		 2285 p_udp_hdr->uh_sum = 0;
2286
718da2b9 2287 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2288 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2289
6cadb320
FB		 2290 p_udp_hdr->uh_sum = udp_checksum;
2291 }
2292
2293 /* restore IP header */
718da2b9 2294 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2295 }
2296 }
2297 }
2298
2299 /* update tally counter */
2300 ++s->tally_counters.TxOk;
2301
2302 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2303
718da2b9 2304 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2305
2306 /* restore card space if there was no recursion and reset offset */
2307 if (!s->cplus_txbuffer)
2308 {
2309 s->cplus_txbuffer = saved_buffer;
2310 s->cplus_txbuffer_len = saved_buffer_len;
2311 s->cplus_txbuffer_offset = 0;
2312 }
2313 else
2314 {
2bc6f59b 2315 qemu_free(saved_buffer);
6cadb320 2316 }
a41b2ff2
PB		 2317 }
2318 else
2319 {
6cadb320 2320 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2321 }
2322
a41b2ff2
PB		 2323 return 1;
2324}
2325
2326static void rtl8139_cplus_transmit(RTL8139State *s)
2327{
2328 int txcount = 0;
2329
2330 while (rtl8139_cplus_transmit_one(s))
2331 {
2332 ++txcount;
2333 }
2334
2335 /* Mark transfer completed */
2336 if (!txcount)
2337 {
6cadb320
FB		 2338 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2339 s->currCPlusTxDesc));
a41b2ff2
PB		 2340 }
2341 else
2342 {
2343 /* update interrupt status */
2344 s->IntrStatus |= TxOK;
2345 rtl8139_update_irq(s);
2346 }
2347}
2348
2349static void rtl8139_transmit(RTL8139State *s)
2350{
2351 int descriptor = s->currTxDesc, txcount = 0;
2352
2353 /*while*/
2354 if (rtl8139_transmit_one(s, descriptor))
2355 {
2356 ++s->currTxDesc;
2357 s->currTxDesc %= 4;
2358 ++txcount;
2359 }
2360
2361 /* Mark transfer completed */
2362 if (!txcount)
2363 {
6cadb320 2364 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2365 }
2366}
2367
2368static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2369{
2370
2371 int descriptor = txRegOffset/4;
6cadb320
FB		 2372
2373 /* handle C+ transmit mode register configuration */
2374
2c3891ab 2375 if (s->cplus_enabled)
6cadb320
FB		 2376 {
2377 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2378
2379 /* handle Dump Tally Counters command */
2380 s->TxStatus[descriptor] = val;
2381
2382 if (descriptor == 0 && (val & 0x8))
2383 {
c227f099 2384 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2385
2386 /* dump tally counters to specified memory location */
2387 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2388
2389 /* mark dump completed */
2390 s->TxStatus[0] &= ~0x8;
2391 }
2392
2393 return;
2394 }
2395
2396 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2397
2398 /* mask only reserved bits */
2399 val &= ~0xff00c000; /* these bits are reset on write */
2400 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2401
2402 s->TxStatus[descriptor] = val;
2403
2404 /* attempt to start transmission */
2405 rtl8139_transmit(s);
2406}
2407
2408static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2409{
2410 uint32_t ret = s->TxStatus[txRegOffset/4];
2411
6cadb320 2412 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2413
2414 return ret;
2415}
2416
2417static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2418{
2419 uint16_t ret = 0;
2420
2421 /* Simulate TSAD, it is read only anyway */
2422
2423 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2424 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2425 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2426 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2427
2428 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2429 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2430 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2431 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2432
a41b2ff2
PB		 2433 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2434 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2435 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2436 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2437
a41b2ff2
PB		 2438 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2439 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2440 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2441 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2442
a41b2ff2 2443
6cadb320 2444 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2445
2446 return ret;
2447}
2448
2449static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2450{
2451 uint16_t ret = s->CSCR;
2452
6cadb320 2453 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2454
2455 return ret;
2456}
2457
2458static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2459{
6cadb320 2460 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2461
290a0933 2462 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2463}
2464
2465static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2466{
290a0933 2467 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2468
6cadb320 2469 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2470
2471 return ret;
2472}
2473
2474static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2475{
6cadb320 2476 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2477
2478 /* this value is off by 16 */
2479 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2480
6cadb320
FB		 2481 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2482 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2483}
2484
2485static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2486{
2487 /* this value is off by 16 */
2488 uint32_t ret = s->RxBufPtr - 0x10;
2489
6cadb320
FB		 2490 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2491
2492 return ret;
2493}
2494
2495static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2496{
2497 /* this value is NOT off by 16 */
2498 uint32_t ret = s->RxBufAddr;
2499
2500 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2501
2502 return ret;
2503}
2504
2505static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2506{
6cadb320 2507 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2508
2509 s->RxBuf = val;
2510
2511 /* may need to reset rxring here */
2512}
2513
2514static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2515{
2516 uint32_t ret = s->RxBuf;
2517
6cadb320 2518 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2519
2520 return ret;
2521}
2522
2523static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2524{
6cadb320 2525 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2526
2527 /* mask unwriteable bits */
2528 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2529
2530 s->IntrMask = val;
2531
05447803 2532 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
a41b2ff2 2533 rtl8139_update_irq(s);
05447803 2534
a41b2ff2
PB		 2535}
2536
2537static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2538{
2539 uint32_t ret = s->IntrMask;
2540
6cadb320 2541 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2542
2543 return ret;
2544}
2545
2546static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2547{
6cadb320 2548 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2549
2550#if 0
2551
2552 /* writing to ISR has no effect */
2553
2554 return;
2555
2556#else
2557 uint16_t newStatus = s->IntrStatus & ~val;
2558
2559 /* mask unwriteable bits */
2560 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2561
2562 /* writing 1 to interrupt status register bit clears it */
2563 s->IntrStatus = 0;
2564 rtl8139_update_irq(s);
2565
2566 s->IntrStatus = newStatus;
05447803
FZ		 2567 /*
2568 * Computing if we miss an interrupt here is not that correct but
2569 * considered that we should have had already an interrupt
2570 * and probably emulated is slower is better to assume this resetting was
2571 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2572 */
2573 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
a41b2ff2 2574 rtl8139_update_irq(s);
05447803 2575
a41b2ff2
PB		 2576#endif
2577}
2578
2579static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2580{
05447803
FZ		 2581 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2582
a41b2ff2
PB		 2583 uint32_t ret = s->IntrStatus;
2584
6cadb320 2585 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2586
2587#if 0
2588
2589 /* reading ISR clears all interrupts */
2590 s->IntrStatus = 0;
2591
2592 rtl8139_update_irq(s);
2593
2594#endif
2595
2596 return ret;
2597}
2598
2599static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2600{
6cadb320 2601 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2602
2603 /* mask unwriteable bits */
2604 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2605
2606 s->MultiIntr = val;
2607}
2608
2609static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2610{
2611 uint32_t ret = s->MultiIntr;
2612
6cadb320 2613 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2614
2615 return ret;
2616}
2617
2618static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2619{
2620 RTL8139State *s = opaque;
2621
2622 addr &= 0xff;
2623
2624 switch (addr)
2625 {
2626 case MAC0 ... MAC0+5:
2627 s->phys[addr - MAC0] = val;
2628 break;
2629 case MAC0+6 ... MAC0+7:
2630 /* reserved */
2631 break;
2632 case MAR0 ... MAR0+7:
2633 s->mult[addr - MAR0] = val;
2634 break;
2635 case ChipCmd:
2636 rtl8139_ChipCmd_write(s, val);
2637 break;
2638 case Cfg9346:
2639 rtl8139_Cfg9346_write(s, val);
2640 break;
2641 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2642 rtl8139_TxConfig_writeb(s, val);
2643 break;
2644 case Config0:
2645 rtl8139_Config0_write(s, val);
2646 break;
2647 case Config1:
2648 rtl8139_Config1_write(s, val);
2649 break;
2650 case Config3:
2651 rtl8139_Config3_write(s, val);
2652 break;
2653 case Config4:
2654 rtl8139_Config4_write(s, val);
2655 break;
2656 case Config5:
2657 rtl8139_Config5_write(s, val);
2658 break;
2659 case MediaStatus:
2660 /* ignore */
6cadb320 2661 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2662 break;
2663
2664 case HltClk:
6cadb320 2665 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2666 if (val == 'R')
2667 {
2668 s->clock_enabled = 1;
2669 }
2670 else if (val == 'H')
2671 {
2672 s->clock_enabled = 0;
2673 }
2674 break;
2675
2676 case TxThresh:
6cadb320 2677 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2678 s->TxThresh = val;
2679 break;
2680
2681 case TxPoll:
6cadb320 2682 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2683 if (val & (1 << 7))
2684 {
6cadb320 2685 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2686 //rtl8139_cplus_transmit(s);
2687 }
2688 if (val & (1 << 6))
2689 {
6cadb320 2690 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2691 rtl8139_cplus_transmit(s);
2692 }
2693
2694 break;
2695
2696 default:
6cadb320 2697 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2698 break;
2699 }
2700}
2701
2702static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2703{
2704 RTL8139State *s = opaque;
2705
2706 addr &= 0xfe;
2707
2708 switch (addr)
2709 {
2710 case IntrMask:
2711 rtl8139_IntrMask_write(s, val);
2712 break;
2713
2714 case IntrStatus:
2715 rtl8139_IntrStatus_write(s, val);
2716 break;
2717
2718 case MultiIntr:
2719 rtl8139_MultiIntr_write(s, val);
2720 break;
2721
2722 case RxBufPtr:
2723 rtl8139_RxBufPtr_write(s, val);
2724 break;
2725
2726 case BasicModeCtrl:
2727 rtl8139_BasicModeCtrl_write(s, val);
2728 break;
2729 case BasicModeStatus:
2730 rtl8139_BasicModeStatus_write(s, val);
2731 break;
2732 case NWayAdvert:
6cadb320 2733 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2734 s->NWayAdvert = val;
2735 break;
2736 case NWayLPAR:
6cadb320 2737 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2738 break;
2739 case NWayExpansion:
6cadb320 2740 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2741 s->NWayExpansion = val;
2742 break;
2743
2744 case CpCmd:
2745 rtl8139_CpCmd_write(s, val);
2746 break;
2747
6cadb320
FB		 2748 case IntrMitigate:
2749 rtl8139_IntrMitigate_write(s, val);
2750 break;
2751
a41b2ff2 2752 default:
6cadb320 2753 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2 2754
a41b2ff2
PB		 2755 rtl8139_io_writeb(opaque, addr, val & 0xff);
2756 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2757 break;
2758 }
2759}
2760
05447803
FZ		 2761static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2762{
2763 int64_t pci_time, next_time;
2764 uint32_t low_pci;
2765
2766 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2767
2768 if (s->TimerExpire && current_time >= s->TimerExpire) {
2769 s->IntrStatus |= PCSTimeout;
2770 rtl8139_update_irq(s);
2771 }
2772
2773 /* Set QEMU timer only if needed that is
2774 * - TimerInt <> 0 (we have a timer)
2775 * - mask = 1 (we want an interrupt timer)
2776 * - irq = 0 (irq is not already active)
2777 * If any of above change we need to compute timer again
2778 * Also we must check if timer is passed without QEMU timer
2779 */
2780 s->TimerExpire = 0;
2781 if (!s->TimerInt) {
2782 return;
2783 }
2784
2785 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2786 get_ticks_per_sec());
2787 low_pci = pci_time & 0xffffffff;
2788 pci_time = pci_time - low_pci + s->TimerInt;
2789 if (low_pci >= s->TimerInt) {
2790 pci_time += 0x100000000LL;
2791 }
2792 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2793 PCI_FREQUENCY);
2794 s->TimerExpire = next_time;
2795
2796 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2797 qemu_mod_timer(s->timer, next_time);
2798 }
2799}
2800
a41b2ff2
PB		 2801static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2802{
2803 RTL8139State *s = opaque;
2804
2805 addr &= 0xfc;
2806
2807 switch (addr)
2808 {
2809 case RxMissed:
6cadb320 2810 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2811 s->RxMissed = 0;
2812 break;
2813
2814 case TxConfig:
2815 rtl8139_TxConfig_write(s, val);
2816 break;
2817
2818 case RxConfig:
2819 rtl8139_RxConfig_write(s, val);
2820 break;
2821
2822 case TxStatus0 ... TxStatus0+4*4-1:
2823 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2824 break;
2825
2826 case TxAddr0 ... TxAddr0+4*4-1:
2827 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2828 break;
2829
2830 case RxBuf:
2831 rtl8139_RxBuf_write(s, val);
2832 break;
2833
2834 case RxRingAddrLO:
6cadb320 2835 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2836 s->RxRingAddrLO = val;
2837 break;
2838
2839 case RxRingAddrHI:
6cadb320 2840 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2841 s->RxRingAddrHI = val;
2842 break;
2843
6cadb320
FB		 2844 case Timer:
2845 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
6cadb320 2846 s->TCTR_base = qemu_get_clock(vm_clock);
05447803 2847 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2848 break;
2849
2850 case FlashReg:
2851 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
05447803
FZ		 2852 if (s->TimerInt != val) {
2853 s->TimerInt = val;
2854 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2855 }
6cadb320
FB		 2856 break;
2857
a41b2ff2 2858 default:
6cadb320 2859 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2860 rtl8139_io_writeb(opaque, addr, val & 0xff);
2861 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2862 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2863 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2864 break;
2865 }
2866}
2867
2868static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2869{
2870 RTL8139State *s = opaque;
2871 int ret;
2872
2873 addr &= 0xff;
2874
2875 switch (addr)
2876 {
2877 case MAC0 ... MAC0+5:
2878 ret = s->phys[addr - MAC0];
2879 break;
2880 case MAC0+6 ... MAC0+7:
2881 ret = 0;
2882 break;
2883 case MAR0 ... MAR0+7:
2884 ret = s->mult[addr - MAR0];
2885 break;
2886 case ChipCmd:
2887 ret = rtl8139_ChipCmd_read(s);
2888 break;
2889 case Cfg9346:
2890 ret = rtl8139_Cfg9346_read(s);
2891 break;
2892 case Config0:
2893 ret = rtl8139_Config0_read(s);
2894 break;
2895 case Config1:
2896 ret = rtl8139_Config1_read(s);
2897 break;
2898 case Config3:
2899 ret = rtl8139_Config3_read(s);
2900 break;
2901 case Config4:
2902 ret = rtl8139_Config4_read(s);
2903 break;
2904 case Config5:
2905 ret = rtl8139_Config5_read(s);
2906 break;
2907
2908 case MediaStatus:
2909 ret = 0xd0;
6cadb320 2910 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2911 break;
2912
2913 case HltClk:
2914 ret = s->clock_enabled;
6cadb320 2915 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2916 break;
2917
2918 case PCIRevisionID:
6cadb320
FB		 2919 ret = RTL8139_PCI_REVID;
2920 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2921 break;
2922
2923 case TxThresh:
2924 ret = s->TxThresh;
6cadb320 2925 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2926 break;
2927
2928 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2929 ret = s->TxConfig >> 24;
6cadb320 2930 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2931 break;
2932
2933 default:
6cadb320 2934 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2935 ret = 0;
2936 break;
2937 }
2938
2939 return ret;
2940}
2941
2942static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2943{
2944 RTL8139State *s = opaque;
2945 uint32_t ret;
2946
2947 addr &= 0xfe; /* mask lower bit */
2948
2949 switch (addr)
2950 {
2951 case IntrMask:
2952 ret = rtl8139_IntrMask_read(s);
2953 break;
2954
2955 case IntrStatus:
2956 ret = rtl8139_IntrStatus_read(s);
2957 break;
2958
2959 case MultiIntr:
2960 ret = rtl8139_MultiIntr_read(s);
2961 break;
2962
2963 case RxBufPtr:
2964 ret = rtl8139_RxBufPtr_read(s);
2965 break;
2966
6cadb320
FB		 2967 case RxBufAddr:
2968 ret = rtl8139_RxBufAddr_read(s);
2969 break;
2970
a41b2ff2
PB		 2971 case BasicModeCtrl:
2972 ret = rtl8139_BasicModeCtrl_read(s);
2973 break;
2974 case BasicModeStatus:
2975 ret = rtl8139_BasicModeStatus_read(s);
2976 break;
2977 case NWayAdvert:
2978 ret = s->NWayAdvert;
6cadb320 2979 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2980 break;
2981 case NWayLPAR:
2982 ret = s->NWayLPAR;
6cadb320 2983 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2984 break;
2985 case NWayExpansion:
2986 ret = s->NWayExpansion;
6cadb320 2987 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2988 break;
2989
2990 case CpCmd:
2991 ret = rtl8139_CpCmd_read(s);
2992 break;
2993
6cadb320
FB		 2994 case IntrMitigate:
2995 ret = rtl8139_IntrMitigate_read(s);
2996 break;
2997
a41b2ff2
PB		 2998 case TxSummary:
2999 ret = rtl8139_TSAD_read(s);
3000 break;
3001
3002 case CSCR:
3003 ret = rtl8139_CSCR_read(s);
3004 break;
3005
3006 default:
6cadb320 3007 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2 3008
a41b2ff2
PB		 3009 ret = rtl8139_io_readb(opaque, addr);
3010 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3011
6cadb320 3012 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 3013 break;
3014 }
3015
3016 return ret;
3017}
3018
3019static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3020{
3021 RTL8139State *s = opaque;
3022 uint32_t ret;
3023
3024 addr &= 0xfc; /* also mask low 2 bits */
3025
3026 switch (addr)
3027 {
3028 case RxMissed:
3029 ret = s->RxMissed;
3030
6cadb320 3031 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 3032 break;
3033
3034 case TxConfig:
3035 ret = rtl8139_TxConfig_read(s);
3036 break;
3037
3038 case RxConfig:
3039 ret = rtl8139_RxConfig_read(s);
3040 break;
3041
3042 case TxStatus0 ... TxStatus0+4*4-1:
3043 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3044 break;
3045
3046 case TxAddr0 ... TxAddr0+4*4-1:
3047 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3048 break;
3049
3050 case RxBuf:
3051 ret = rtl8139_RxBuf_read(s);
3052 break;
3053
3054 case RxRingAddrLO:
3055 ret = s->RxRingAddrLO;
6cadb320 3056 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3057 break;
3058
3059 case RxRingAddrHI:
3060 ret = s->RxRingAddrHI;
6cadb320
FB		 3061 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3062 break;
3063
3064 case Timer:
05447803
FZ		 3065 ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base,
3066 PCI_FREQUENCY, get_ticks_per_sec());
6cadb320
FB		 3067 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3068 break;
3069
3070 case FlashReg:
3071 ret = s->TimerInt;
3072 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3073 break;
3074
3075 default:
6cadb320 3076 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2 3077
a41b2ff2
PB		 3078 ret = rtl8139_io_readb(opaque, addr);
3079 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3080 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3081 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3082
6cadb320 3083 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3084 break;
3085 }
3086
3087 return ret;
3088}
3089
3090/* */
3091
3092static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3093{
3094 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3095}
3096
3097static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3098{
3099 rtl8139_io_writew(opaque, addr & 0xFF, val);
3100}
3101
3102static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3103{
3104 rtl8139_io_writel(opaque, addr & 0xFF, val);
3105}
3106
3107static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3108{
3109 return rtl8139_io_readb(opaque, addr & 0xFF);
3110}
3111
3112static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3113{
3114 return rtl8139_io_readw(opaque, addr & 0xFF);
3115}
3116
3117static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3118{
3119 return rtl8139_io_readl(opaque, addr & 0xFF);
3120}
3121
3122/* */
3123
c227f099 3124static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3125{
3126 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3127}
3128
c227f099 3129static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3130{
3131 rtl8139_io_writew(opaque, addr & 0xFF, val);
3132}
3133
c227f099 3134static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3135{
3136 rtl8139_io_writel(opaque, addr & 0xFF, val);
3137}
3138
c227f099 3139static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3140{
3141 return rtl8139_io_readb(opaque, addr & 0xFF);
3142}
3143
c227f099 3144static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3145{
5fedc612 3146 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3147 return val;
a41b2ff2
PB		 3148}
3149
c227f099 3150static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3151{
5fedc612 3152 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3153 return val;
a41b2ff2
PB		 3154}
3155
060110c3 3156static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3157{
6597ebbb 3158 RTL8139State* s = opaque;
05447803 3159 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
060110c3 3160 if (version_id < 4) {
2c3891ab
AL		 3161 s->cplus_enabled = s->CpCmd != 0;
3162 }
3163
a41b2ff2
PB		 3164 return 0;
3165}
3166
c574ba5a
AW		 3167static bool rtl8139_hotplug_ready_needed(void *opaque)
3168{
3169 return qdev_machine_modified();
3170}
3171
3172static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3173 .name = "rtl8139/hotplug_ready",
3174 .version_id = 1,
3175 .minimum_version_id = 1,
3176 .minimum_version_id_old = 1,
3177 .fields = (VMStateField []) {
3178 VMSTATE_END_OF_LIST()
3179 }
3180};
3181
05447803
FZ		 3182static void rtl8139_pre_save(void *opaque)
3183{
3184 RTL8139State* s = opaque;
3185 int64_t current_time = qemu_get_clock(vm_clock);
3186
3187 /* set IntrStatus correctly */
3188 rtl8139_set_next_tctr_time(s, current_time);
3189 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3190 get_ticks_per_sec());
c574ba5a 3191 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
05447803
FZ		 3192}
3193
060110c3
JQ		 3194static const VMStateDescription vmstate_rtl8139 = {
3195 .name = "rtl8139",
3196 .version_id = 4,
3197 .minimum_version_id = 3,
3198 .minimum_version_id_old = 3,
3199 .post_load = rtl8139_post_load,
05447803 3200 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3201 .fields = (VMStateField []) {
3202 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3203 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3204 VMSTATE_BUFFER(mult, RTL8139State),
3205 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3206 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3207
3208 VMSTATE_UINT32(RxBuf, RTL8139State),
3209 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3210 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3211 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3212
3213 VMSTATE_UINT16(IntrStatus, RTL8139State),
3214 VMSTATE_UINT16(IntrMask, RTL8139State),
3215
3216 VMSTATE_UINT32(TxConfig, RTL8139State),
3217 VMSTATE_UINT32(RxConfig, RTL8139State),
3218 VMSTATE_UINT32(RxMissed, RTL8139State),
3219 VMSTATE_UINT16(CSCR, RTL8139State),
3220
3221 VMSTATE_UINT8(Cfg9346, RTL8139State),
3222 VMSTATE_UINT8(Config0, RTL8139State),
3223 VMSTATE_UINT8(Config1, RTL8139State),
3224 VMSTATE_UINT8(Config3, RTL8139State),
3225 VMSTATE_UINT8(Config4, RTL8139State),
3226 VMSTATE_UINT8(Config5, RTL8139State),
3227
3228 VMSTATE_UINT8(clock_enabled, RTL8139State),
3229 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3230
3231 VMSTATE_UINT16(MultiIntr, RTL8139State),
3232
3233 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3234 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3235 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3236 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3237 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3238
3239 VMSTATE_UINT16(CpCmd, RTL8139State),
3240 VMSTATE_UINT8(TxThresh, RTL8139State),
3241
3242 VMSTATE_UNUSED(4),
3243 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3244 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3245
3246 VMSTATE_UINT32(currTxDesc, RTL8139State),
3247 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3248 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3249 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3250 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3251
3252 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3253 VMSTATE_INT32(eeprom.mode, RTL8139State),
3254 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3255 VMSTATE_UINT8(eeprom.address, RTL8139State),
3256 VMSTATE_UINT16(eeprom.input, RTL8139State),
3257 VMSTATE_UINT16(eeprom.output, RTL8139State),
3258
3259 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3260 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3261 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3262 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3263
3264 VMSTATE_UINT32(TCTR, RTL8139State),
3265 VMSTATE_UINT32(TimerInt, RTL8139State),
3266 VMSTATE_INT64(TCTR_base, RTL8139State),
3267
3268 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3269 vmstate_tally_counters, RTL8139TallyCounters),
3270
3271 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3272 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3273 },
3274 .subsections = (VMStateSubsection []) {
3275 {
3276 .vmsd = &vmstate_rtl8139_hotplug_ready,
3277 .needed = rtl8139_hotplug_ready_needed,
3278 }, {
3279 /* empty */
3280 }
060110c3
JQ		 3281 }
3282};
3283
a41b2ff2
PB		 3284/***********************************************************/
3285/* PCI RTL8139 definitions */
3286
5fafdf24 3287static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3288 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3289{
efd6dd45 3290 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3291
3292 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3293}
3294
5fafdf24 3295static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3296 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3297{
efd6dd45 3298 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3299
3300 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3301 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3302
3303 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3304 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3305
3306 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3307 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3308}
3309
d60efc6b 3310static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3311 rtl8139_mmio_readb,
3312 rtl8139_mmio_readw,
3313 rtl8139_mmio_readl,
3314};
3315
d60efc6b 3316static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3317 rtl8139_mmio_writeb,
3318 rtl8139_mmio_writew,
3319 rtl8139_mmio_writel,
3320};
3321
6cadb320
FB		 3322static void rtl8139_timer(void *opaque)
3323{
3324 RTL8139State *s = opaque;
3325
6cadb320
FB		 3326 if (!s->clock_enabled)
3327 {
3328 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3329 return;
3330 }
3331
05447803
FZ		 3332 s->IntrStatus |= PCSTimeout;
3333 rtl8139_update_irq(s);
3334 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
6cadb320 3335}
6cadb320 3336
1673ad51 3337static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3338{
1673ad51 3339 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3340
1673ad51 3341 s->nic = NULL;
254111ec
GH		 3342}
3343
3344static int pci_rtl8139_uninit(PCIDevice *dev)
3345{
3346 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3347
3348 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3349 if (s->cplus_txbuffer) {
3350 qemu_free(s->cplus_txbuffer);
3351 s->cplus_txbuffer = NULL;
3352 }
b946a153
AL		 3353 qemu_del_timer(s->timer);
3354 qemu_free_timer(s->timer);
1673ad51 3355 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3356 return 0;
3357}
3358
1673ad51
MM		 3359static NetClientInfo net_rtl8139_info = {
3360 .type = NET_CLIENT_TYPE_NIC,
3361 .size = sizeof(NICState),
3362 .can_receive = rtl8139_can_receive,
3363 .receive = rtl8139_receive,
3364 .cleanup = rtl8139_cleanup,
3365};
3366
81a322d4 3367static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3368{
efd6dd45 3369 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3370 uint8_t *pci_conf;
3b46e624 3371
efd6dd45 3372 pci_conf = s->dev.config;
deb54399
AL		 3373 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3374 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547 3375 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3376 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3377 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3378 /* TODO: start of capability list, but no capability
3379 * list bit in status register, and offset 0xdc seems unused. */
3380 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3381
a41b2ff2
PB		 3382 /* I/O handler for memory-mapped I/O */
3383 s->rtl8139_mmio_io_addr =
2507c12a 3384 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
5cf7a3ca 3385 DEVICE_LITTLE_ENDIAN);
a41b2ff2 3386
efd6dd45 3387 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3388 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3389
efd6dd45 3390 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3391 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3392
254111ec 3393 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3394
1673ad51
MM		 3395 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3396 dev->qdev.info->name, dev->qdev.id, s);
3397 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3398
3399 s->cplus_txbuffer = NULL;
3400 s->cplus_txbuffer_len = 0;
3401 s->cplus_txbuffer_offset = 0;
3b46e624 3402
05447803 3403 s->TimerExpire = 0;
6cadb320 3404 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
05447803 3405 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
1ca4d09a
GN		 3406
3407 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3408
81a322d4 3409 return 0;
a41b2ff2 3410}
9d07d757 3411
0aab0d3a 3412static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3413 .qdev.name = "rtl8139",
3414 .qdev.size = sizeof(RTL8139State),
3415 .qdev.reset = rtl8139_reset,
be73cfe2 3416 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3417 .init = pci_rtl8139_init,
e3936fa5 3418 .exit = pci_rtl8139_uninit,
8c52c8f3 3419 .romfile = "pxe-rtl8139.bin",
254111ec
GH		 3420 .qdev.props = (Property[]) {
3421 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3422 DEFINE_PROP_END_OF_LIST(),
3423 }
0aab0d3a
GH		 3424};
3425
9d07d757
PB		 3426static void rtl8139_register_devices(void)
3427{
0aab0d3a 3428 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3429}
3430
3431device_init(rtl8139_register_devices)
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