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47d05a86 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 PB |
30 | #include "qemu-common.h" |
31 | #include "cpu.h" | |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
47d05a86 | 35 | #include "elf.h" |
022c62cb PB |
36 | #include "exec/memory.h" |
37 | #include "exec/address-spaces.h" | |
8488ab02 | 38 | #include "qemu/error-report.h" |
47d05a86 | 39 | |
b68755c1 MF |
40 | static void xtensa_create_memory_regions(const XtensaMemory *memory, |
41 | const char *name) | |
42 | { | |
43 | unsigned i; | |
bb0b6f39 | 44 | GString *num_name = g_string_new(NULL); |
b68755c1 MF |
45 | |
46 | for (i = 0; i < memory->num; ++i) { | |
47 | MemoryRegion *m; | |
48 | ||
bb0b6f39 MF |
49 | g_string_printf(num_name, "%s%u", name, i); |
50 | m = g_new(MemoryRegion, 1); | |
51 | memory_region_init_ram(m, NULL, num_name->str, | |
b68755c1 MF |
52 | memory->location[i].size, |
53 | &error_fatal); | |
54 | vmstate_register_ram_global(m); | |
55 | memory_region_add_subregion(get_system_memory(), | |
56 | memory->location[i].addr, m); | |
57 | } | |
bb0b6f39 | 58 | g_string_free(num_name, true); |
b68755c1 MF |
59 | } |
60 | ||
00b941e5 | 61 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
47d05a86 | 62 | { |
00b941e5 AF |
63 | XtensaCPU *cpu = opaque; |
64 | ||
65 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
47d05a86 MF |
66 | } |
67 | ||
11e7bfd7 | 68 | static void sim_reset(void *opaque) |
47d05a86 | 69 | { |
11e7bfd7 AF |
70 | XtensaCPU *cpu = opaque; |
71 | ||
72 | cpu_reset(CPU(cpu)); | |
47d05a86 MF |
73 | } |
74 | ||
3ef96221 | 75 | static void xtensa_sim_init(MachineState *machine) |
47d05a86 | 76 | { |
06d26274 | 77 | XtensaCPU *cpu = NULL; |
5bfcb36e | 78 | CPUXtensaState *env = NULL; |
3ef96221 MA |
79 | ram_addr_t ram_size = machine->ram_size; |
80 | const char *cpu_model = machine->cpu_model; | |
81 | const char *kernel_filename = machine->kernel_filename; | |
47d05a86 MF |
82 | int n; |
83 | ||
50cd7214 MF |
84 | if (!cpu_model) { |
85 | cpu_model = XTENSA_DEFAULT_CPU_MODEL; | |
86 | } | |
87 | ||
47d05a86 | 88 | for (n = 0; n < smp_cpus; n++) { |
06d26274 AF |
89 | cpu = cpu_xtensa_init(cpu_model); |
90 | if (cpu == NULL) { | |
ebbb419a | 91 | error_report("unable to find CPU definition '%s'", |
8488ab02 MF |
92 | cpu_model); |
93 | exit(EXIT_FAILURE); | |
47d05a86 | 94 | } |
06d26274 AF |
95 | env = &cpu->env; |
96 | ||
47d05a86 | 97 | env->sregs[PRID] = n; |
11e7bfd7 | 98 | qemu_register_reset(sim_reset, cpu); |
47d05a86 MF |
99 | /* Need MMU initialized prior to ELF loading, |
100 | * so that ELF gets loaded into virtual addresses | |
101 | */ | |
11e7bfd7 | 102 | sim_reset(cpu); |
47d05a86 MF |
103 | } |
104 | ||
b68755c1 MF |
105 | if (env) { |
106 | XtensaMemory sysram = env->config->sysram; | |
47d05a86 | 107 | |
b68755c1 MF |
108 | sysram.location[0].size = ram_size; |
109 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom"); | |
110 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram"); | |
111 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom"); | |
112 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram"); | |
113 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom"); | |
114 | xtensa_create_memory_regions(&sysram, "xtensa.sysram"); | |
115 | } | |
47d05a86 MF |
116 | |
117 | if (kernel_filename) { | |
118 | uint64_t elf_entry; | |
119 | uint64_t elf_lowaddr; | |
120 | #ifdef TARGET_WORDS_BIGENDIAN | |
00b941e5 | 121 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
7ef295ea | 122 | &elf_entry, &elf_lowaddr, NULL, 1, EM_XTENSA, 0, 0); |
47d05a86 | 123 | #else |
00b941e5 | 124 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
7ef295ea | 125 | &elf_entry, &elf_lowaddr, NULL, 0, EM_XTENSA, 0, 0); |
47d05a86 MF |
126 | #endif |
127 | if (success > 0) { | |
128 | env->pc = elf_entry; | |
129 | } | |
130 | } | |
131 | } | |
132 | ||
e264d29d | 133 | static void xtensa_sim_machine_init(MachineClass *mc) |
47d05a86 | 134 | { |
e264d29d EH |
135 | mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")"; |
136 | mc->is_default = true; | |
137 | mc->init = xtensa_sim_init; | |
138 | mc->max_cpus = 4; | |
47d05a86 MF |
139 | } |
140 | ||
e264d29d | 141 | DEFINE_MACHINE("sim", xtensa_sim_machine_init) |