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47d05a86 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
9c17d615 | 28 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
29 | #include "hw/boards.h" |
30 | #include "hw/loader.h" | |
47d05a86 | 31 | #include "elf.h" |
022c62cb PB |
32 | #include "exec/memory.h" |
33 | #include "exec/address-spaces.h" | |
47d05a86 | 34 | |
00b941e5 | 35 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
47d05a86 | 36 | { |
00b941e5 AF |
37 | XtensaCPU *cpu = opaque; |
38 | ||
39 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
47d05a86 MF |
40 | } |
41 | ||
11e7bfd7 | 42 | static void sim_reset(void *opaque) |
47d05a86 | 43 | { |
11e7bfd7 AF |
44 | XtensaCPU *cpu = opaque; |
45 | ||
46 | cpu_reset(CPU(cpu)); | |
47d05a86 MF |
47 | } |
48 | ||
50cd7214 | 49 | static void xtensa_sim_init(QEMUMachineInitArgs *args) |
47d05a86 | 50 | { |
06d26274 | 51 | XtensaCPU *cpu = NULL; |
5bfcb36e | 52 | CPUXtensaState *env = NULL; |
47d05a86 | 53 | MemoryRegion *ram, *rom; |
50cd7214 MF |
54 | ram_addr_t ram_size = args->ram_size; |
55 | const char *cpu_model = args->cpu_model; | |
56 | const char *kernel_filename = args->kernel_filename; | |
47d05a86 MF |
57 | int n; |
58 | ||
50cd7214 MF |
59 | if (!cpu_model) { |
60 | cpu_model = XTENSA_DEFAULT_CPU_MODEL; | |
61 | } | |
62 | ||
47d05a86 | 63 | for (n = 0; n < smp_cpus; n++) { |
06d26274 AF |
64 | cpu = cpu_xtensa_init(cpu_model); |
65 | if (cpu == NULL) { | |
47d05a86 MF |
66 | fprintf(stderr, "Unable to find CPU definition\n"); |
67 | exit(1); | |
68 | } | |
06d26274 AF |
69 | env = &cpu->env; |
70 | ||
47d05a86 | 71 | env->sregs[PRID] = n; |
11e7bfd7 | 72 | qemu_register_reset(sim_reset, cpu); |
47d05a86 MF |
73 | /* Need MMU initialized prior to ELF loading, |
74 | * so that ELF gets loaded into virtual addresses | |
75 | */ | |
11e7bfd7 | 76 | sim_reset(cpu); |
47d05a86 MF |
77 | } |
78 | ||
79 | ram = g_malloc(sizeof(*ram)); | |
2c9b15ca | 80 | memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size); |
c5705a77 | 81 | vmstate_register_ram_global(ram); |
47d05a86 MF |
82 | memory_region_add_subregion(get_system_memory(), 0, ram); |
83 | ||
84 | rom = g_malloc(sizeof(*rom)); | |
2c9b15ca | 85 | memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000); |
c5705a77 | 86 | vmstate_register_ram_global(rom); |
47d05a86 MF |
87 | memory_region_add_subregion(get_system_memory(), 0xfe000000, rom); |
88 | ||
89 | if (kernel_filename) { | |
90 | uint64_t elf_entry; | |
91 | uint64_t elf_lowaddr; | |
92 | #ifdef TARGET_WORDS_BIGENDIAN | |
00b941e5 | 93 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
47d05a86 MF |
94 | &elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); |
95 | #else | |
00b941e5 | 96 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
47d05a86 MF |
97 | &elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0); |
98 | #endif | |
99 | if (success > 0) { | |
100 | env->pc = elf_entry; | |
101 | } | |
102 | } | |
103 | } | |
104 | ||
5e408573 MF |
105 | static QEMUMachine xtensa_sim_machine = { |
106 | .name = "sim", | |
e38077ff | 107 | .desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")", |
82e5d464 | 108 | .is_default = true, |
5e408573 | 109 | .init = xtensa_sim_init, |
47d05a86 MF |
110 | .max_cpus = 4, |
111 | }; | |
112 | ||
5e408573 | 113 | static void xtensa_sim_machine_init(void) |
47d05a86 | 114 | { |
5e408573 | 115 | qemu_register_machine(&xtensa_sim_machine); |
47d05a86 MF |
116 | } |
117 | ||
5e408573 | 118 | machine_init(xtensa_sim_machine_init); |