[qemu.git] / hw / i386 / pc_q35.c

/*
 * Q35 chipset based pc system emulator
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2009, 2010
 *               Isaku Yamahata <yamahata at valinux co jp>
 *               VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <[email protected]>
 *
 * This is based on pc.c, but heavily modified.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/loader.h"
#include "sysemu/arch_init.h"
#include "hw/i2c/smbus.h"
#include "hw/boards.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/xen/xen.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "hw/pci-host/q35.h"
#include "exec/address-spaces.h"
#include "hw/i386/ich9.h"
#include "hw/i386/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/usb.h"
#include "hw/cpu/icc_bus.h"

/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS     6

static bool has_pci_info;
static bool has_acpi_build = true;
static bool smbios_defaults = true;
static bool smbios_legacy_mode;
/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
 * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
 * pages in the host.
 */
static bool gigabyte_align = true;

/* PC hardware initialisation */
static void pc_q35_init(MachineState *machine)
{
    ram_addr_t below_4g_mem_size, above_4g_mem_size;
    Q35PCIHost *q35_host;
    PCIHostState *phb;
    PCIBus *host_bus;
    PCIDevice *lpc;
    BusState *idebus[MAX_SATA_PORTS];
    ISADevice *rtc_state;
    ISADevice *floppy;
    MemoryRegion *pci_memory;
    MemoryRegion *rom_memory;
    MemoryRegion *ram_memory;
    GSIState *gsi_state;
    ISABus *isa_bus;
    int pci_enabled = 1;
    qemu_irq *cpu_irq;
    qemu_irq *gsi;
    qemu_irq *i8259;
    int i;
    ICH9LPCState *ich9_lpc;
    PCIDevice *ahci;
    DeviceState *icc_bridge;
    PcGuestInfo *guest_info;

    if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
        fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
        exit(1);
    }

    icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
    object_property_add_child(qdev_get_machine(), "icc-bridge",
                              OBJECT(icc_bridge), NULL);

    pc_cpus_init(machine->cpu_model, icc_bridge);
    pc_acpi_init("q35-acpi-dsdt.aml");

    kvmclock_create();

    /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
     * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
     * also known as MMCFG).
     * If it doesn't, we need to split it in chunks below and above 4G.
     * In any case, try to make sure that guest addresses aligned at
     * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
     * For old machine types, use whatever split we used historically to avoid
     * breaking migration.
     */
    if (machine->ram_size >= 0xb0000000) {
        ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
        above_4g_mem_size = machine->ram_size - lowmem;
        below_4g_mem_size = lowmem;
    } else {
        above_4g_mem_size = 0;
        below_4g_mem_size = machine->ram_size;
    }

    /* pci enabled */
    if (pci_enabled) {
        pci_memory = g_new(MemoryRegion, 1);
        memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
        rom_memory = pci_memory;
    } else {
        pci_memory = NULL;
        rom_memory = get_system_memory();
    }

    guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
    guest_info->has_pci_info = has_pci_info;
    guest_info->isapc_ram_fw = false;
    guest_info->has_acpi_build = has_acpi_build;

    if (smbios_defaults) {
        MachineClass *mc = MACHINE_GET_CLASS(machine);
        /* These values are guest ABI, do not change */
        smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
                            mc->name, smbios_legacy_mode);
    }

    /* allocate ram and load rom/bios */
    if (!xen_enabled()) {
        pc_memory_init(get_system_memory(),
                       machine->kernel_filename, machine->kernel_cmdline,
                       machine->initrd_filename,
                       below_4g_mem_size, above_4g_mem_size,
                       rom_memory, &ram_memory, guest_info);
    }

    /* irq lines */
    gsi_state = g_malloc0(sizeof(*gsi_state));
    if (kvm_irqchip_in_kernel()) {
        kvm_pc_setup_irq_routing(pci_enabled);
        gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
                                 GSI_NUM_PINS);
    } else {
        gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
    }

    /* create pci host bus */
    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));

    object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
    q35_host->mch.ram_memory = ram_memory;
    q35_host->mch.pci_address_space = pci_memory;
    q35_host->mch.system_memory = get_system_memory();
    q35_host->mch.address_space_io = get_system_io();
    q35_host->mch.below_4g_mem_size = below_4g_mem_size;
    q35_host->mch.above_4g_mem_size = above_4g_mem_size;
    q35_host->mch.guest_info = guest_info;
    /* pci */
    qdev_init_nofail(DEVICE(q35_host));
    phb = PCI_HOST_BRIDGE(q35_host);
    host_bus = phb->bus;
    /* create ISA bus */
    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
                                          ICH9_LPC_FUNC), true,
                                          TYPE_ICH9_LPC_DEVICE);
    ich9_lpc = ICH9_LPC_DEVICE(lpc);
    ich9_lpc->pic = gsi;
    ich9_lpc->ioapic = gsi_state->ioapic_irq;
    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
                 ICH9_LPC_NB_PIRQS);
    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
    isa_bus = ich9_lpc->isa_bus;

    /*end early*/
    isa_bus_irqs(isa_bus, gsi);

    if (kvm_irqchip_in_kernel()) {
        i8259 = kvm_i8259_init(isa_bus);
    } else if (xen_enabled()) {
        i8259 = xen_interrupt_controller_init();
    } else {
        cpu_irq = pc_allocate_cpu_irq();
        i8259 = i8259_init(isa_bus, cpu_irq[0]);
    }

    for (i = 0; i < ISA_NUM_IRQS; i++) {
        gsi_state->i8259_irq[i] = i8259[i];
    }
    if (pci_enabled) {
        ioapic_init_gsi(gsi_state, NULL);
    }
    qdev_init_nofail(icc_bridge);

    pc_register_ferr_irq(gsi[13]);

    /* init basic PC hardware */
    pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);

    /* connect pm stuff to lpc */
    ich9_lpc_pm_init(lpc);

    /* ahci and SATA device, for q35 1 ahci controller is built-in */
    ahci = pci_create_simple_multifunction(host_bus,
                                           PCI_DEVFN(ICH9_SATA1_DEV,
                                                     ICH9_SATA1_FUNC),
                                           true, "ich9-ahci");
    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");

    if (usb_enabled(false)) {
        /* Should we create 6 UHCI according to ich9 spec? */
        ehci_create_ich9_with_companions(host_bus, 0x1d);
    }

    /* TODO: Populate SPD eeprom data.  */
    smbus_eeprom_init(ich9_smb_init(host_bus,
                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
                                    0xb100),
                      8, NULL, 0);

    pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
                 floppy, idebus[0], idebus[1], rtc_state);

    /* the rest devices to which pci devfn is automatically assigned */
    pc_vga_init(isa_bus, host_bus);
    pc_nic_init(isa_bus, host_bus);
    if (pci_enabled) {
        pc_pci_device_init(host_bus);
    }
}

static void pc_compat_2_0(MachineState *machine)
{
    smbios_legacy_mode = true;
}

static void pc_compat_1_7(MachineState *machine)
{
    pc_compat_2_0(machine);
    smbios_defaults = false;
    gigabyte_align = false;
    option_rom_has_mr = true;
    x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC);
}

static void pc_compat_1_6(MachineState *machine)
{
    pc_compat_1_7(machine);
    has_pci_info = false;
    rom_file_has_mr = false;
    has_acpi_build = false;
}

static void pc_compat_1_5(MachineState *machine)
{
    pc_compat_1_6(machine);
}

static void pc_compat_1_4(MachineState *machine)
{
    pc_compat_1_5(machine);
    x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
    x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
}

static void pc_q35_init_2_0(MachineState *machine)
{
    pc_compat_2_0(machine);
    pc_q35_init(machine);
}

static void pc_q35_init_1_7(MachineState *machine)
{
    pc_compat_1_7(machine);
    pc_q35_init(machine);
}

static void pc_q35_init_1_6(MachineState *machine)
{
    pc_compat_1_6(machine);
    pc_q35_init(machine);
}

static void pc_q35_init_1_5(MachineState *machine)
{
    pc_compat_1_5(machine);
    pc_q35_init(machine);
}

static void pc_q35_init_1_4(MachineState *machine)
{
    pc_compat_1_4(machine);
    pc_q35_init(machine);
}

#define PC_Q35_MACHINE_OPTIONS \
    PC_DEFAULT_MACHINE_OPTIONS, \
    .desc = "Standard PC (Q35 + ICH9, 2009)", \
    .hot_add_cpu = pc_hot_add_cpu

#define PC_Q35_2_1_MACHINE_OPTIONS                      \
    PC_Q35_MACHINE_OPTIONS,                             \
    .default_machine_opts = "firmware=bios-256k.bin"

static QEMUMachine pc_q35_machine_v2_1 = {
    PC_Q35_2_1_MACHINE_OPTIONS,
    .name = "pc-q35-2.1",
    .alias = "q35",
    .init = pc_q35_init,
};

#define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v2_0 = {
    PC_Q35_2_0_MACHINE_OPTIONS,
    .name = "pc-q35-2.0",
    .init = pc_q35_init_2_0,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_2_0,
        { /* end of list */ }
    },
};

#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v1_7 = {
    PC_Q35_1_7_MACHINE_OPTIONS,
    .name = "pc-q35-1.7",
    .init = pc_q35_init_1_7,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_7,
        { /* end of list */ }
    },
};

#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v1_6 = {
    PC_Q35_1_6_MACHINE_OPTIONS,
    .name = "pc-q35-1.6",
    .init = pc_q35_init_1_6,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_6,
        { /* end of list */ }
    },
};

static QEMUMachine pc_q35_machine_v1_5 = {
    PC_Q35_1_6_MACHINE_OPTIONS,
    .name = "pc-q35-1.5",
    .init = pc_q35_init_1_5,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_5,
        { /* end of list */ }
    },
};

#define PC_Q35_1_4_MACHINE_OPTIONS \
    PC_Q35_1_6_MACHINE_OPTIONS, \
    .hot_add_cpu = NULL

static QEMUMachine pc_q35_machine_v1_4 = {
    PC_Q35_1_4_MACHINE_OPTIONS,
    .name = "pc-q35-1.4",
    .init = pc_q35_init_1_4,
    .compat_props = (GlobalProperty[]) {
        PC_COMPAT_1_4,
        { /* end of list */ }
    },
};

static void pc_q35_machine_init(void)
{
    qemu_register_machine(&pc_q35_machine_v2_1);
    qemu_register_machine(&pc_q35_machine_v2_0);
    qemu_register_machine(&pc_q35_machine_v1_7);
    qemu_register_machine(&pc_q35_machine_v1_6);
    qemu_register_machine(&pc_q35_machine_v1_5);
    qemu_register_machine(&pc_q35_machine_v1_4);
}

machine_init(pc_q35_machine_init);
Commit	Line	Data
df2d8b3e IY	1	/*
	2	* Q35 chipset based pc system emulator
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2009, 2010
	6	* Isaku Yamahata <yamahata at valinux co jp>
	7	* VA Linux Systems Japan K.K.
	8	* Copyright (C) 2012 Jason Baron <[email protected]>
	9	*
	10	* This is based on pc.c, but heavily modified.
	11	*
	12	* Permission is hereby granted, free of charge, to any person obtaining a copy
	13	* of this software and associated documentation files (the "Software"), to deal
	14	* in the Software without restriction, including without limitation the rights
	15	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	16	* copies of the Software, and to permit persons to whom the Software is
	17	* furnished to do so, subject to the following conditions:
	18	*
	19	* The above copyright notice and this permission notice shall be included in
	20	* all copies or substantial portions of the Software.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	23	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	24	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	25	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	26	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	27	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	28	* THE SOFTWARE.
	29	*/
83c9f4ca	30	#include "hw/hw.h"
04920fc0	31	#include "hw/loader.h"
9c17d615	32	#include "sysemu/arch_init.h"
0d09e41a	33	#include "hw/i2c/smbus.h"
83c9f4ca	34	#include "hw/boards.h"
0d09e41a PB	35	#include "hw/timer/mc146818rtc.h"
0d09e41a PB	36	#include "hw/xen/xen.h"
9c17d615	37	#include "sysemu/kvm.h"
83c9f4ca	38	#include "hw/kvm/clock.h"
0d09e41a	39	#include "hw/pci-host/q35.h"
022c62cb	40	#include "exec/address-spaces.h"
0d09e41a	41	#include "hw/i386/ich9.h"
b29ad07e	42	#include "hw/i386/smbios.h"
df2d8b3e IY	43	#include "hw/ide/pci.h"
	44	#include "hw/ide/ahci.h"
	45	#include "hw/usb.h"
f0513d2c	46	#include "hw/cpu/icc_bus.h"
df2d8b3e IY	47
	48	/* ICH9 AHCI has 6 ports */
	49	#define MAX_SATA_PORTS 6
	50
7f1bb742	51	static bool has_pci_info;
72c194f7	52	static bool has_acpi_build = true;
e6667f71	53	static bool smbios_defaults = true;
c97294ec	54	static bool smbios_legacy_mode;
4e17997d MT	55	/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
	56	* host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
	57	* pages in the host.
	58	*/
9a305c8f	59	static bool gigabyte_align = true;
3ab135f3	60
df2d8b3e	61	/* PC hardware initialisation */
3ef96221	62	static void pc_q35_init(MachineState *machine)
df2d8b3e	63	{
df2d8b3e IY	64	ram_addr_t below_4g_mem_size, above_4g_mem_size;
df2d8b3e IY	65	Q35PCIHost *q35_host;
ce88812f	66	PCIHostState *phb;
df2d8b3e IY	67	PCIBus *host_bus;
	68	PCIDevice *lpc;
	69	BusState *idebus[MAX_SATA_PORTS];
	70	ISADevice *rtc_state;
	71	ISADevice *floppy;
	72	MemoryRegion *pci_memory;
	73	MemoryRegion *rom_memory;
	74	MemoryRegion *ram_memory;
	75	GSIState *gsi_state;
	76	ISABus *isa_bus;
	77	int pci_enabled = 1;
	78	qemu_irq *cpu_irq;
	79	qemu_irq *gsi;
	80	qemu_irq *i8259;
	81	int i;
	82	ICH9LPCState *ich9_lpc;
	83	PCIDevice *ahci;
f0513d2c	84	DeviceState *icc_bridge;
3459a625	85	PcGuestInfo *guest_info;
f0513d2c	86
254c1282 AP	87	if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
	88	fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
	89	exit(1);
	90	}
	91
f0513d2c IM	92	icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
	93	object_property_add_child(qdev_get_machine(), "icc-bridge",
	94	OBJECT(icc_bridge), NULL);
df2d8b3e	95
3ef96221	96	pc_cpus_init(machine->cpu_model, icc_bridge);
f7e4dd6c	97	pc_acpi_init("q35-acpi-dsdt.aml");
df2d8b3e	98
21022c92 JK	99	kvmclock_create();
21022c92 JK	100
4e17997d MT	101	/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
	102	* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
	103	* also known as MMCFG).
	104	* If it doesn't, we need to split it in chunks below and above 4G.
	105	* In any case, try to make sure that guest addresses aligned at
	106	* 1G boundaries get mapped to host addresses aligned at 1G boundaries.
	107	* For old machine types, use whatever split we used historically to avoid
	108	* breaking migration.
	109	*/
3ef96221	110	if (machine->ram_size >= 0xb0000000) {
9a305c8f	111	ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
3ef96221	112	above_4g_mem_size = machine->ram_size - lowmem;
9a305c8f	113	below_4g_mem_size = lowmem;
df2d8b3e IY	114	} else {
df2d8b3e IY	115	above_4g_mem_size = 0;
3ef96221	116	below_4g_mem_size = machine->ram_size;
df2d8b3e IY	117	}
	118
	119	/* pci enabled */
	120	if (pci_enabled) {
	121	pci_memory = g_new(MemoryRegion, 1);
286690e3	122	memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
df2d8b3e IY	123	rom_memory = pci_memory;
	124	} else {
	125	pci_memory = NULL;
	126	rom_memory = get_system_memory();
	127	}
	128
3459a625	129	guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
f8c457b8	130	guest_info->has_pci_info = has_pci_info;
6dd2a5c9	131	guest_info->isapc_ram_fw = false;
72c194f7	132	guest_info->has_acpi_build = has_acpi_build;
3459a625	133
e6667f71	134	if (smbios_defaults) {
3ef96221	135	MachineClass *mc = MACHINE_GET_CLASS(machine);
b29ad07e	136	/* These values are guest ABI, do not change */
e6667f71	137	smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
3ef96221	138	mc->name, smbios_legacy_mode);
b29ad07e MA	139	}
b29ad07e MA	140
df2d8b3e IY	141	/* allocate ram and load rom/bios */
df2d8b3e IY	142	if (!xen_enabled()) {
3b6fb9ca	143	pc_memory_init(get_system_memory(),
3ef96221 MA	144	machine->kernel_filename, machine->kernel_cmdline,
3ef96221 MA	145	machine->initrd_filename,
3b6fb9ca	146	below_4g_mem_size, above_4g_mem_size,
3459a625	147	rom_memory, &ram_memory, guest_info);
df2d8b3e IY	148	}
	149
	150	/* irq lines */
	151	gsi_state = g_malloc0(sizeof(*gsi_state));
	152	if (kvm_irqchip_in_kernel()) {
	153	kvm_pc_setup_irq_routing(pci_enabled);
	154	gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
	155	GSI_NUM_PINS);
	156	} else {
	157	gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
	158	}
	159
	160	/* create pci host bus */
	161	q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
	162
c52dc697	163	object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
df2d8b3e IY	164	q35_host->mch.ram_memory = ram_memory;
	165	q35_host->mch.pci_address_space = pci_memory;
	166	q35_host->mch.system_memory = get_system_memory();
c7e775e4	167	q35_host->mch.address_space_io = get_system_io();
df2d8b3e IY	168	q35_host->mch.below_4g_mem_size = below_4g_mem_size;
df2d8b3e IY	169	q35_host->mch.above_4g_mem_size = above_4g_mem_size;
3459a625	170	q35_host->mch.guest_info = guest_info;
df2d8b3e IY	171	/* pci */
df2d8b3e IY	172	qdev_init_nofail(DEVICE(q35_host));
ce88812f HT	173	phb = PCI_HOST_BRIDGE(q35_host);
ce88812f HT	174	host_bus = phb->bus;
df2d8b3e IY	175	/* create ISA bus */
	176	lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
	177	ICH9_LPC_FUNC), true,
	178	TYPE_ICH9_LPC_DEVICE);
	179	ich9_lpc = ICH9_LPC_DEVICE(lpc);
	180	ich9_lpc->pic = gsi;
	181	ich9_lpc->ioapic = gsi_state->ioapic_irq;
	182	pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
	183	ICH9_LPC_NB_PIRQS);
91c3f2f0	184	pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
df2d8b3e IY	185	isa_bus = ich9_lpc->isa_bus;
	186
	187	/end early/
	188	isa_bus_irqs(isa_bus, gsi);
	189
	190	if (kvm_irqchip_in_kernel()) {
	191	i8259 = kvm_i8259_init(isa_bus);
	192	} else if (xen_enabled()) {
	193	i8259 = xen_interrupt_controller_init();
	194	} else {
	195	cpu_irq = pc_allocate_cpu_irq();
	196	i8259 = i8259_init(isa_bus, cpu_irq[0]);
	197	}
	198
	199	for (i = 0; i < ISA_NUM_IRQS; i++) {
	200	gsi_state->i8259_irq[i] = i8259[i];
	201	}
	202	if (pci_enabled) {
	203	ioapic_init_gsi(gsi_state, NULL);
	204	}
f0513d2c	205	qdev_init_nofail(icc_bridge);
df2d8b3e IY	206
	207	pc_register_ferr_irq(gsi[13]);
	208
	209	/* init basic PC hardware */
7a10ef51	210	pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);
df2d8b3e IY	211
df2d8b3e IY	212	/* connect pm stuff to lpc */
a3ac6b53	213	ich9_lpc_pm_init(lpc);
df2d8b3e IY	214
	215	/* ahci and SATA device, for q35 1 ahci controller is built-in */
	216	ahci = pci_create_simple_multifunction(host_bus,
	217	PCI_DEVFN(ICH9_SATA1_DEV,
	218	ICH9_SATA1_FUNC),
	219	true, "ich9-ahci");
	220	idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
	221	idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
	222
	223	if (usb_enabled(false)) {
	224	/* Should we create 6 UHCI according to ich9 spec? */
	225	ehci_create_ich9_with_companions(host_bus, 0x1d);
	226	}
	227
	228	/* TODO: Populate SPD eeprom data. */
	229	smbus_eeprom_init(ich9_smb_init(host_bus,
	230	PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
	231	0xb100),
	232	8, NULL, 0);
	233
3ef96221	234	pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
df2d8b3e IY	235	floppy, idebus[0], idebus[1], rtc_state);
	236
	237	/* the rest devices to which pci devfn is automatically assigned */
	238	pc_vga_init(isa_bus, host_bus);
df2d8b3e IY	239	pc_nic_init(isa_bus, host_bus);
	240	if (pci_enabled) {
	241	pc_pci_device_init(host_bus);
	242	}
	243	}
	244
3ef96221	245	static void pc_compat_2_0(MachineState *machine)
3458b2b0	246	{
c97294ec	247	smbios_legacy_mode = true;
3458b2b0 MT	248	}
3458b2b0 MT	249
3ef96221	250	static void pc_compat_1_7(MachineState *machine)
b29ad07e	251	{
3ef96221	252	pc_compat_2_0(machine);
e6667f71	253	smbios_defaults = false;
9a305c8f	254	gigabyte_align = false;
ac41881b	255	option_rom_has_mr = true;
ef02ef5f	256	x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC);
b29ad07e MA	257	}
b29ad07e MA	258
3ef96221	259	static void pc_compat_1_6(MachineState *machine)
f8c457b8	260	{
3ef96221	261	pc_compat_1_7(machine);
f8c457b8	262	has_pci_info = false;
98bc3ab0	263	rom_file_has_mr = false;
72c194f7	264	has_acpi_build = false;
f8c457b8 MT	265	}
f8c457b8 MT	266
3ef96221	267	static void pc_compat_1_5(MachineState *machine)
9604f70f	268	{
3ef96221	269	pc_compat_1_6(machine);
9604f70f MT	270	}
9604f70f MT	271
3ef96221	272	static void pc_compat_1_4(MachineState *machine)
9953f882	273	{
3ef96221	274	pc_compat_1_5(machine);
4458c236	275	x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
56383703	276	x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
89b439f3 EH	277	}
89b439f3 EH	278
3ef96221	279	static void pc_q35_init_2_0(MachineState *machine)
3458b2b0	280	{
3ef96221 MA	281	pc_compat_2_0(machine);
3ef96221 MA	282	pc_q35_init(machine);
3458b2b0 MT	283	}
3458b2b0 MT	284
3ef96221	285	static void pc_q35_init_1_7(MachineState *machine)
b29ad07e	286	{
3ef96221 MA	287	pc_compat_1_7(machine);
3ef96221 MA	288	pc_q35_init(machine);
b29ad07e MA	289	}
b29ad07e MA	290
3ef96221	291	static void pc_q35_init_1_6(MachineState *machine)
89b439f3	292	{
3ef96221 MA	293	pc_compat_1_6(machine);
3ef96221 MA	294	pc_q35_init(machine);
89b439f3 EH	295	}
89b439f3 EH	296
3ef96221	297	static void pc_q35_init_1_5(MachineState *machine)
89b439f3	298	{
3ef96221 MA	299	pc_compat_1_5(machine);
3ef96221 MA	300	pc_q35_init(machine);
89b439f3 EH	301	}
89b439f3 EH	302
3ef96221	303	static void pc_q35_init_1_4(MachineState *machine)
89b439f3	304	{
3ef96221 MA	305	pc_compat_1_4(machine);
3ef96221 MA	306	pc_q35_init(machine);
9953f882 MA	307	}
9953f882 MA	308
a0dba644 MT	309	#define PC_Q35_MACHINE_OPTIONS \
	310	PC_DEFAULT_MACHINE_OPTIONS, \
	311	.desc = "Standard PC (Q35 + ICH9, 2009)", \
	312	.hot_add_cpu = pc_hot_add_cpu
	313
3458b2b0	314	#define PC_Q35_2_1_MACHINE_OPTIONS \
bcf2b7d2 GH	315	PC_Q35_MACHINE_OPTIONS, \
bcf2b7d2 GH	316	.default_machine_opts = "firmware=bios-256k.bin"
aeca6e8d	317
3458b2b0 MT	318	static QEMUMachine pc_q35_machine_v2_1 = {
	319	PC_Q35_2_1_MACHINE_OPTIONS,
	320	.name = "pc-q35-2.1",
	321	.alias = "q35",
	322	.init = pc_q35_init,
	323	};
	324
	325	#define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
	326
aeca6e8d GH	327	static QEMUMachine pc_q35_machine_v2_0 = {
	328	PC_Q35_2_0_MACHINE_OPTIONS,
	329	.name = "pc-q35-2.0",
3458b2b0	330	.init = pc_q35_init_2_0,
9df11c9f GS	331	.compat_props = (GlobalProperty[]) {
	332	PC_Q35_COMPAT_2_0,
	333	{ /* end of list */ }
	334	},
aeca6e8d GH	335	};
aeca6e8d GH	336
e9845f09 VM	337	#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
	338
	339	static QEMUMachine pc_q35_machine_v1_7 = {
	340	PC_Q35_1_7_MACHINE_OPTIONS,
	341	.name = "pc-q35-1.7",
7a10ef51 LPF	342	.init = pc_q35_init_1_7,
	343	.compat_props = (GlobalProperty[]) {
	344	PC_Q35_COMPAT_1_7,
	345	{ /* end of list */ }
	346	},
e9845f09 VM	347	};
e9845f09 VM	348
a0dba644 MT	349	#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
a0dba644 MT	350
45053fde	351	static QEMUMachine pc_q35_machine_v1_6 = {
a0dba644	352	PC_Q35_1_6_MACHINE_OPTIONS,
45053fde	353	.name = "pc-q35-1.6",
9604f70f	354	.init = pc_q35_init_1_6,
e9845f09	355	.compat_props = (GlobalProperty[]) {
7a10ef51	356	PC_Q35_COMPAT_1_6,
e9845f09 VM	357	{ /* end of list */ }
e9845f09 VM	358	},
45053fde EH	359	};
45053fde EH	360
bf3caa3d	361	static QEMUMachine pc_q35_machine_v1_5 = {
a0dba644	362	PC_Q35_1_6_MACHINE_OPTIONS,
bf3caa3d	363	.name = "pc-q35-1.5",
f8c457b8	364	.init = pc_q35_init_1_5,
ffce9ebb	365	.compat_props = (GlobalProperty[]) {
7a10ef51	366	PC_Q35_COMPAT_1_5,
ffce9ebb EH	367	{ /* end of list */ }
ffce9ebb EH	368	},
df2d8b3e IY	369	};
df2d8b3e IY	370
a0dba644 MT	371	#define PC_Q35_1_4_MACHINE_OPTIONS \
	372	PC_Q35_1_6_MACHINE_OPTIONS, \
	373	.hot_add_cpu = NULL
	374
bf3caa3d	375	static QEMUMachine pc_q35_machine_v1_4 = {
a0dba644	376	PC_Q35_1_4_MACHINE_OPTIONS,
bf3caa3d	377	.name = "pc-q35-1.4",
9953f882	378	.init = pc_q35_init_1_4,
bf3caa3d PB	379	.compat_props = (GlobalProperty[]) {
	380	PC_COMPAT_1_4,
	381	{ /* end of list */ }
	382	},
bf3caa3d PB	383	};
bf3caa3d PB	384
df2d8b3e IY	385	static void pc_q35_machine_init(void)
df2d8b3e IY	386	{
3458b2b0	387	qemu_register_machine(&pc_q35_machine_v2_1);
aeca6e8d	388	qemu_register_machine(&pc_q35_machine_v2_0);
e9845f09	389	qemu_register_machine(&pc_q35_machine_v1_7);
45053fde	390	qemu_register_machine(&pc_q35_machine_v1_6);
bf3caa3d PB	391	qemu_register_machine(&pc_q35_machine_v1_5);
bf3caa3d PB	392	qemu_register_machine(&pc_q35_machine_v1_4);
df2d8b3e IY	393	}
	394
	395	machine_init(pc_q35_machine_init);