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5fafdf24 1/*
16406950
PB
2 * ARM kernel loader.
3 *
9ee6e8bb 4 * Copyright (c) 2006-2007 CodeSourcery.
16406950
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
16406950
PB
8 */
9
412beee6 10#include "config.h"
83c9f4ca 11#include "hw/hw.h"
bd2be150 12#include "hw/arm/arm.h"
d8b1ae42 13#include "hw/arm/linux-boot-if.h"
9c17d615 14#include "sysemu/sysemu.h"
83c9f4ca
PB
15#include "hw/boards.h"
16#include "hw/loader.h"
ca20cf32 17#include "elf.h"
9c17d615 18#include "sysemu/device_tree.h"
1de7afc9 19#include "qemu/config-file.h"
2198a121 20#include "exec/address-spaces.h"
16406950 21
4d9ebf75
MH
22/* Kernel boot protocol is specified in the kernel docs
23 * Documentation/arm/Booting and Documentation/arm64/booting.txt
24 * They have different preferred image load offsets from system RAM base.
25 */
16406950
PB
26#define KERNEL_ARGS_ADDR 0x100
27#define KERNEL_LOAD_ADDR 0x00010000
4d9ebf75 28#define KERNEL64_LOAD_ADDR 0x00080000
16406950 29
47b1da81
PM
30typedef enum {
31 FIXUP_NONE = 0, /* do nothing */
32 FIXUP_TERMINATOR, /* end of insns */
33 FIXUP_BOARDID, /* overwrite with board ID number */
34 FIXUP_ARGPTR, /* overwrite with pointer to kernel args */
35 FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */
36 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
37 FIXUP_BOOTREG, /* overwrite with boot register address */
38 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
39 FIXUP_MAX,
40} FixupType;
41
42typedef struct ARMInsnFixup {
43 uint32_t insn;
44 FixupType fixup;
45} ARMInsnFixup;
46
4d9ebf75
MH
47static const ARMInsnFixup bootloader_aarch64[] = {
48 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
49 { 0xaa1f03e1 }, /* mov x1, xzr */
50 { 0xaa1f03e2 }, /* mov x2, xzr */
51 { 0xaa1f03e3 }, /* mov x3, xzr */
52 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
53 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
54 { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */
55 { 0 }, /* .word @DTB Higher 32-bits */
56 { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */
57 { 0 }, /* .word @Kernel Entry Higher 32-bits */
58 { 0, FIXUP_TERMINATOR }
59};
60
16406950 61/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
47b1da81
PM
62static const ARMInsnFixup bootloader[] = {
63 { 0xe3a00000 }, /* mov r0, #0 */
64 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
65 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
66 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
67 { 0, FIXUP_BOARDID },
68 { 0, FIXUP_ARGPTR },
69 { 0, FIXUP_ENTRYPOINT },
70 { 0, FIXUP_TERMINATOR }
16406950
PB
71};
72
9d5ba9bf
ML
73/* Handling for secondary CPU boot in a multicore system.
74 * Unlike the uniprocessor/primary CPU boot, this is platform
75 * dependent. The default code here is based on the secondary
76 * CPU boot protocol used on realview/vexpress boards, with
77 * some parameterisation to increase its flexibility.
78 * QEMU platform models for which this code is not appropriate
79 * should override write_secondary_boot and secondary_cpu_reset_hook
80 * instead.
81 *
82 * This code enables the interrupt controllers for the secondary
83 * CPUs and then puts all the secondary CPUs into a loop waiting
84 * for an interprocessor interrupt and polling a configurable
85 * location for the kernel secondary CPU entry point.
86 */
bf471f79
PM
87#define DSB_INSN 0xf57ff04f
88#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
89
47b1da81
PM
90static const ARMInsnFixup smpboot[] = {
91 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
92 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
93 { 0xe3a01001 }, /* mov r1, #1 */
94 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
95 { 0xe3a010ff }, /* mov r1, #0xff */
96 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
97 { 0, FIXUP_DSB }, /* dsb */
98 { 0xe320f003 }, /* wfi */
99 { 0xe5901000 }, /* ldr r1, [r0] */
100 { 0xe1110001 }, /* tst r1, r1 */
101 { 0x0afffffb }, /* beq <wfi> */
102 { 0xe12fff11 }, /* bx r1 */
103 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
104 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
105 { 0, FIXUP_TERMINATOR }
9ee6e8bb
PB
106};
107
47b1da81
PM
108static void write_bootloader(const char *name, hwaddr addr,
109 const ARMInsnFixup *insns, uint32_t *fixupcontext)
110{
111 /* Fix up the specified bootloader fragment and write it into
112 * guest memory using rom_add_blob_fixed(). fixupcontext is
113 * an array giving the values to write in for the fixup types
114 * which write a value into the code array.
115 */
116 int i, len;
117 uint32_t *code;
118
119 len = 0;
120 while (insns[len].fixup != FIXUP_TERMINATOR) {
121 len++;
122 }
123
124 code = g_new0(uint32_t, len);
125
126 for (i = 0; i < len; i++) {
127 uint32_t insn = insns[i].insn;
128 FixupType fixup = insns[i].fixup;
129
130 switch (fixup) {
131 case FIXUP_NONE:
132 break;
133 case FIXUP_BOARDID:
134 case FIXUP_ARGPTR:
135 case FIXUP_ENTRYPOINT:
136 case FIXUP_GIC_CPU_IF:
137 case FIXUP_BOOTREG:
138 case FIXUP_DSB:
139 insn = fixupcontext[fixup];
140 break;
141 default:
142 abort();
143 }
144 code[i] = tswap32(insn);
145 }
146
147 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr);
148
149 g_free(code);
150}
151
9543b0cd 152static void default_write_secondary(ARMCPU *cpu,
9d5ba9bf
ML
153 const struct arm_boot_info *info)
154{
47b1da81
PM
155 uint32_t fixupcontext[FIXUP_MAX];
156
157 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
158 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
159 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
160 fixupcontext[FIXUP_DSB] = DSB_INSN;
161 } else {
162 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
9d5ba9bf 163 }
47b1da81
PM
164
165 write_bootloader("smpboot", info->smp_loader_start,
166 smpboot, fixupcontext);
9d5ba9bf
ML
167}
168
5d309320 169static void default_reset_secondary(ARMCPU *cpu,
9d5ba9bf
ML
170 const struct arm_boot_info *info)
171{
4df81c6e 172 CPUState *cs = CPU(cpu);
5d309320 173
42874d3a
PM
174 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr,
175 0, MEMTXATTRS_UNSPECIFIED, NULL);
4df81c6e 176 cpu_set_pc(cs, info->smp_loader_start);
9d5ba9bf
ML
177}
178
83bfffec
PM
179static inline bool have_dtb(const struct arm_boot_info *info)
180{
181 return info->dtb_filename || info->get_dtb;
182}
183
52b43737 184#define WRITE_WORD(p, value) do { \
42874d3a
PM
185 address_space_stl_notdirty(&address_space_memory, p, value, \
186 MEMTXATTRS_UNSPECIFIED, NULL); \
52b43737
PB
187 p += 4; \
188} while (0)
189
761c9eb0 190static void set_kernel_args(const struct arm_boot_info *info)
16406950 191{
761c9eb0 192 int initrd_size = info->initrd_size;
a8170e5e
AK
193 hwaddr base = info->loader_start;
194 hwaddr p;
16406950 195
52b43737 196 p = base + KERNEL_ARGS_ADDR;
16406950 197 /* ATAG_CORE */
52b43737
PB
198 WRITE_WORD(p, 5);
199 WRITE_WORD(p, 0x54410001);
200 WRITE_WORD(p, 1);
201 WRITE_WORD(p, 0x1000);
202 WRITE_WORD(p, 0);
16406950 203 /* ATAG_MEM */
f93eb9ff 204 /* TODO: handle multiple chips on one ATAG list */
52b43737
PB
205 WRITE_WORD(p, 4);
206 WRITE_WORD(p, 0x54410002);
207 WRITE_WORD(p, info->ram_size);
208 WRITE_WORD(p, info->loader_start);
16406950
PB
209 if (initrd_size) {
210 /* ATAG_INITRD2 */
52b43737
PB
211 WRITE_WORD(p, 4);
212 WRITE_WORD(p, 0x54420005);
fc53b7d4 213 WRITE_WORD(p, info->initrd_start);
52b43737 214 WRITE_WORD(p, initrd_size);
16406950 215 }
f93eb9ff 216 if (info->kernel_cmdline && *info->kernel_cmdline) {
16406950
PB
217 /* ATAG_CMDLINE */
218 int cmdline_size;
219
f93eb9ff 220 cmdline_size = strlen(info->kernel_cmdline);
e1fe50dc 221 cpu_physical_memory_write(p + 8, info->kernel_cmdline,
52b43737 222 cmdline_size + 1);
16406950 223 cmdline_size = (cmdline_size >> 2) + 1;
52b43737
PB
224 WRITE_WORD(p, cmdline_size + 2);
225 WRITE_WORD(p, 0x54410009);
226 p += cmdline_size * 4;
16406950 227 }
f93eb9ff
AZ
228 if (info->atag_board) {
229 /* ATAG_BOARD */
230 int atag_board_len;
52b43737 231 uint8_t atag_board_buf[0x1000];
f93eb9ff 232
52b43737
PB
233 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
234 WRITE_WORD(p, (atag_board_len + 8) >> 2);
235 WRITE_WORD(p, 0x414f4d50);
236 cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
f93eb9ff
AZ
237 p += atag_board_len;
238 }
16406950 239 /* ATAG_END */
52b43737
PB
240 WRITE_WORD(p, 0);
241 WRITE_WORD(p, 0);
16406950
PB
242}
243
761c9eb0 244static void set_kernel_args_old(const struct arm_boot_info *info)
2b8f2d41 245{
a8170e5e 246 hwaddr p;
52b43737 247 const char *s;
761c9eb0 248 int initrd_size = info->initrd_size;
a8170e5e 249 hwaddr base = info->loader_start;
2b8f2d41
AZ
250
251 /* see linux/include/asm-arm/setup.h */
52b43737 252 p = base + KERNEL_ARGS_ADDR;
2b8f2d41 253 /* page_size */
52b43737 254 WRITE_WORD(p, 4096);
2b8f2d41 255 /* nr_pages */
52b43737 256 WRITE_WORD(p, info->ram_size / 4096);
2b8f2d41 257 /* ramdisk_size */
52b43737 258 WRITE_WORD(p, 0);
2b8f2d41
AZ
259#define FLAG_READONLY 1
260#define FLAG_RDLOAD 4
261#define FLAG_RDPROMPT 8
262 /* flags */
52b43737 263 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
2b8f2d41 264 /* rootdev */
52b43737 265 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
2b8f2d41 266 /* video_num_cols */
52b43737 267 WRITE_WORD(p, 0);
2b8f2d41 268 /* video_num_rows */
52b43737 269 WRITE_WORD(p, 0);
2b8f2d41 270 /* video_x */
52b43737 271 WRITE_WORD(p, 0);
2b8f2d41 272 /* video_y */
52b43737 273 WRITE_WORD(p, 0);
2b8f2d41 274 /* memc_control_reg */
52b43737 275 WRITE_WORD(p, 0);
2b8f2d41
AZ
276 /* unsigned char sounddefault */
277 /* unsigned char adfsdrives */
278 /* unsigned char bytes_per_char_h */
279 /* unsigned char bytes_per_char_v */
52b43737 280 WRITE_WORD(p, 0);
2b8f2d41 281 /* pages_in_bank[4] */
52b43737
PB
282 WRITE_WORD(p, 0);
283 WRITE_WORD(p, 0);
284 WRITE_WORD(p, 0);
285 WRITE_WORD(p, 0);
2b8f2d41 286 /* pages_in_vram */
52b43737 287 WRITE_WORD(p, 0);
2b8f2d41 288 /* initrd_start */
fc53b7d4
PM
289 if (initrd_size) {
290 WRITE_WORD(p, info->initrd_start);
291 } else {
52b43737 292 WRITE_WORD(p, 0);
fc53b7d4 293 }
2b8f2d41 294 /* initrd_size */
52b43737 295 WRITE_WORD(p, initrd_size);
2b8f2d41 296 /* rd_start */
52b43737 297 WRITE_WORD(p, 0);
2b8f2d41 298 /* system_rev */
52b43737 299 WRITE_WORD(p, 0);
2b8f2d41 300 /* system_serial_low */
52b43737 301 WRITE_WORD(p, 0);
2b8f2d41 302 /* system_serial_high */
52b43737 303 WRITE_WORD(p, 0);
2b8f2d41 304 /* mem_fclk_21285 */
52b43737 305 WRITE_WORD(p, 0);
2b8f2d41 306 /* zero unused fields */
52b43737
PB
307 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
308 WRITE_WORD(p, 0);
309 }
310 s = info->kernel_cmdline;
311 if (s) {
e1fe50dc 312 cpu_physical_memory_write(p, s, strlen(s) + 1);
52b43737
PB
313 } else {
314 WRITE_WORD(p, 0);
315 }
2b8f2d41
AZ
316}
317
fee8ea12
AB
318/**
319 * load_dtb() - load a device tree binary image into memory
320 * @addr: the address to load the image at
321 * @binfo: struct describing the boot environment
322 * @addr_limit: upper limit of the available memory area at @addr
323 *
324 * Load a device tree supplied by the machine or by the user with the
325 * '-dtb' command line option, and put it at offset @addr in target
326 * memory.
327 *
328 * If @addr_limit contains a meaningful value (i.e., it is strictly greater
329 * than @addr), the device tree is only loaded if its size does not exceed
330 * the limit.
331 *
332 * Returns: the size of the device tree image on success,
333 * 0 if the image size exceeds the limit,
334 * -1 on errors.
a554ecb4
HZ
335 *
336 * Note: Must not be called unless have_dtb(binfo) is true.
fee8ea12
AB
337 */
338static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
339 hwaddr addr_limit)
412beee6 340{
412beee6 341 void *fdt = NULL;
412beee6 342 int size, rc;
70976c41 343 uint32_t acells, scells;
412beee6 344
0fb79851
JR
345 if (binfo->dtb_filename) {
346 char *filename;
347 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
348 if (!filename) {
349 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
350 goto fail;
351 }
412beee6 352
0fb79851
JR
353 fdt = load_device_tree(filename, &size);
354 if (!fdt) {
355 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
356 g_free(filename);
357 goto fail;
358 }
412beee6 359 g_free(filename);
a554ecb4 360 } else {
0fb79851
JR
361 fdt = binfo->get_dtb(binfo, &size);
362 if (!fdt) {
363 fprintf(stderr, "Board was unable to create a dtb blob\n");
364 goto fail;
365 }
412beee6 366 }
412beee6 367
fee8ea12
AB
368 if (addr_limit > addr && size > (addr_limit - addr)) {
369 /* Installing the device tree blob at addr would exceed addr_limit.
370 * Whether this constitutes failure is up to the caller to decide,
371 * so just return 0 as size, i.e., no error.
372 */
373 g_free(fdt);
374 return 0;
375 }
376
5a4348d1
PC
377 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells");
378 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells");
9bfa659e
PM
379 if (acells == 0 || scells == 0) {
380 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
c23045de 381 goto fail;
9bfa659e
PM
382 }
383
70976c41
PM
384 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
385 /* This is user error so deserves a friendlier error message
386 * than the failure of setprop_sized_cells would provide
387 */
9bfa659e
PM
388 fprintf(stderr, "qemu: dtb file not compatible with "
389 "RAM size > 4GB\n");
c23045de 390 goto fail;
9bfa659e
PM
391 }
392
5a4348d1
PC
393 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
394 acells, binfo->loader_start,
395 scells, binfo->ram_size);
412beee6
GL
396 if (rc < 0) {
397 fprintf(stderr, "couldn't set /memory/reg\n");
c23045de 398 goto fail;
412beee6
GL
399 }
400
5e87975c 401 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
5a4348d1
PC
402 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
403 binfo->kernel_cmdline);
5e87975c
PC
404 if (rc < 0) {
405 fprintf(stderr, "couldn't set /chosen/bootargs\n");
c23045de 406 goto fail;
5e87975c 407 }
412beee6
GL
408 }
409
410 if (binfo->initrd_size) {
5a4348d1
PC
411 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
412 binfo->initrd_start);
412beee6
GL
413 if (rc < 0) {
414 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
c23045de 415 goto fail;
412beee6
GL
416 }
417
5a4348d1
PC
418 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
419 binfo->initrd_start + binfo->initrd_size);
412beee6
GL
420 if (rc < 0) {
421 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
c23045de 422 goto fail;
412beee6
GL
423 }
424 }
3b1cceb8
PM
425
426 if (binfo->modify_dtb) {
427 binfo->modify_dtb(binfo, fdt);
428 }
429
5a4348d1 430 qemu_fdt_dumpdtb(fdt, size);
412beee6 431
4c4bf654
AB
432 /* Put the DTB into the memory map as a ROM image: this will ensure
433 * the DTB is copied again upon reset, even if addr points into RAM.
434 */
435 rom_add_blob_fixed("dtb", fdt, size, addr);
412beee6 436
c23045de
PM
437 g_free(fdt);
438
fee8ea12 439 return size;
c23045de
PM
440
441fail:
442 g_free(fdt);
443 return -1;
412beee6
GL
444}
445
6ed221b6 446static void do_cpu_reset(void *opaque)
f2d74978 447{
351d5666 448 ARMCPU *cpu = opaque;
4df81c6e 449 CPUState *cs = CPU(cpu);
351d5666 450 CPUARMState *env = &cpu->env;
462a8bc6 451 const struct arm_boot_info *info = env->boot_info;
f2d74978 452
4df81c6e 453 cpu_reset(cs);
f2d74978
PB
454 if (info) {
455 if (!info->is_linux) {
456 /* Jump to the entry point. */
4df81c6e
PC
457 uint64_t entry = info->entry;
458
459 if (!env->aarch64) {
a9047ec3 460 env->thumb = info->entry & 1;
4df81c6e 461 entry &= 0xfffffffe;
a9047ec3 462 }
4df81c6e 463 cpu_set_pc(cs, entry);
f2d74978 464 } else {
c8e829b7
GB
465 /* If we are booting Linux then we need to check whether we are
466 * booting into secure or non-secure state and adjust the state
467 * accordingly. Out of reset, ARM is defined to be in secure state
468 * (SCR.NS = 0), we change that here if non-secure boot has been
469 * requested.
470 */
5097227c
GB
471 if (arm_feature(env, ARM_FEATURE_EL3)) {
472 /* AArch64 is defined to come out of reset into EL3 if enabled.
473 * If we are booting Linux then we need to adjust our EL as
474 * Linux expects us to be in EL2 or EL1. AArch32 resets into
475 * SVC, which Linux expects, so no privilege/exception level to
476 * adjust.
477 */
478 if (env->aarch64) {
479 if (arm_feature(env, ARM_FEATURE_EL2)) {
480 env->pstate = PSTATE_MODE_EL2h;
481 } else {
482 env->pstate = PSTATE_MODE_EL1h;
483 }
484 }
485
486 /* Set to non-secure if not a secure boot */
487 if (!info->secure_boot) {
488 /* Linux expects non-secure state */
489 env->cp15.scr_el3 |= SCR_NS;
490 }
c8e829b7
GB
491 }
492
4df81c6e
PC
493 if (cs == first_cpu) {
494 cpu_set_pc(cs, info->loader_start);
4d9ebf75 495
83bfffec 496 if (!have_dtb(info)) {
412beee6
GL
497 if (old_param) {
498 set_kernel_args_old(info);
499 } else {
500 set_kernel_args(info);
501 }
6ed221b6 502 }
f2d74978 503 } else {
5d309320 504 info->secondary_cpu_reset_hook(cpu, info);
f2d74978
PB
505 }
506 }
507 }
f2d74978
PB
508}
509
07abe45c
LE
510/**
511 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
512 * by key.
513 * @fw_cfg: The firmware config instance to store the data in.
514 * @size_key: The firmware config key to store the size of the loaded
515 * data under, with fw_cfg_add_i32().
516 * @data_key: The firmware config key to store the loaded data under,
517 * with fw_cfg_add_bytes().
518 * @image_name: The name of the image file to load. If it is NULL, the
519 * function returns without doing anything.
520 * @try_decompress: Whether the image should be decompressed (gunzipped) before
521 * adding it to fw_cfg. If decompression fails, the image is
522 * loaded as-is.
523 *
524 * In case of failure, the function prints an error message to stderr and the
525 * process exits with status 1.
526 */
527static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
528 uint16_t data_key, const char *image_name,
529 bool try_decompress)
530{
531 size_t size = -1;
532 uint8_t *data;
533
534 if (image_name == NULL) {
535 return;
536 }
537
538 if (try_decompress) {
539 size = load_image_gzipped_buffer(image_name,
540 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
541 }
542
543 if (size == (size_t)-1) {
544 gchar *contents;
545 gsize length;
546
547 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
548 fprintf(stderr, "failed to load \"%s\"\n", image_name);
549 exit(1);
550 }
551 size = length;
552 data = (uint8_t *)contents;
553 }
554
555 fw_cfg_add_i32(fw_cfg, size_key, size);
556 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
557}
558
d8b1ae42
PM
559static int do_arm_linux_init(Object *obj, void *opaque)
560{
561 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
562 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
563 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
564 struct arm_boot_info *info = opaque;
565
566 if (albifc->arm_linux_init) {
567 albifc->arm_linux_init(albif, info->secure_boot);
568 }
569 }
570 return 0;
571}
572
ac9d32e3 573static void arm_load_kernel_notify(Notifier *notifier, void *data)
16406950 574{
c6faa758 575 CPUState *cs;
16406950
PB
576 int kernel_size;
577 int initrd_size;
1c7b3754 578 int is_linux = 0;
92df8450 579 uint64_t elf_entry, elf_low_addr, elf_high_addr;
da0af40d 580 int elf_machine;
4d9ebf75 581 hwaddr entry, kernel_load_offset;
ca20cf32 582 int big_endian;
4d9ebf75 583 static const ARMInsnFixup *primary_loader;
ac9d32e3
EA
584 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
585 notifier, notifier);
586 ARMCPU *cpu = n->cpu;
587 struct arm_boot_info *info =
588 container_of(n, struct arm_boot_info, load_kernel_notifier);
16406950
PB
589
590 /* Load the kernel. */
07abe45c 591 if (!info->kernel_filename || info->firmware_loaded) {
69e7f76f
AB
592
593 if (have_dtb(info)) {
07abe45c
LE
594 /* If we have a device tree blob, but no kernel to supply it to (or
595 * the kernel is supposed to be loaded by the bootloader), copy the
596 * DTB to the base of RAM for the bootloader to pick up.
69e7f76f
AB
597 */
598 if (load_dtb(info->loader_start, info, 0) < 0) {
599 exit(1);
600 }
601 }
602
07abe45c
LE
603 if (info->kernel_filename) {
604 FWCfgState *fw_cfg;
605 bool try_decompressing_kernel;
606
607 fw_cfg = fw_cfg_find();
608 try_decompressing_kernel = arm_feature(&cpu->env,
609 ARM_FEATURE_AARCH64);
610
611 /* Expose the kernel, the command line, and the initrd in fw_cfg.
612 * We don't process them here at all, it's all left to the
613 * firmware.
614 */
615 load_image_to_fw_cfg(fw_cfg,
616 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
617 info->kernel_filename,
618 try_decompressing_kernel);
619 load_image_to_fw_cfg(fw_cfg,
620 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
621 info->initrd_filename, false);
622
623 if (info->kernel_cmdline) {
624 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
625 strlen(info->kernel_cmdline) + 1);
626 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
627 info->kernel_cmdline);
628 }
629 }
630
631 /* We will start from address 0 (typically a boot ROM image) in the
632 * same way as hardware.
9546dbab
PM
633 */
634 return;
16406950 635 }
daf90626 636
4d9ebf75
MH
637 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
638 primary_loader = bootloader_aarch64;
639 kernel_load_offset = KERNEL64_LOAD_ADDR;
da0af40d 640 elf_machine = EM_AARCH64;
4d9ebf75
MH
641 } else {
642 primary_loader = bootloader;
643 kernel_load_offset = KERNEL_LOAD_ADDR;
da0af40d 644 elf_machine = EM_ARM;
4d9ebf75
MH
645 }
646
2ff3de68 647 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
412beee6 648
9d5ba9bf
ML
649 if (!info->secondary_cpu_reset_hook) {
650 info->secondary_cpu_reset_hook = default_reset_secondary;
651 }
652 if (!info->write_secondary_boot) {
653 info->write_secondary_boot = default_write_secondary;
654 }
655
f2d74978
PB
656 if (info->nb_cpus == 0)
657 info->nb_cpus = 1;
f93eb9ff 658
ca20cf32
BS
659#ifdef TARGET_WORDS_BIGENDIAN
660 big_endian = 1;
661#else
662 big_endian = 0;
663#endif
664
fc53b7d4
PM
665 /* We want to put the initrd far enough into RAM that when the
666 * kernel is uncompressed it will not clobber the initrd. However
667 * on boards without much RAM we must ensure that we still leave
668 * enough room for a decent sized initrd, and on boards with large
669 * amounts of RAM we must avoid the initrd being so far up in RAM
670 * that it is outside lowmem and inaccessible to the kernel.
671 * So for boards with less than 256MB of RAM we put the initrd
672 * halfway into RAM, and for boards with 256MB of RAM or more we put
673 * the initrd at 128MB.
674 */
675 info->initrd_start = info->loader_start +
676 MIN(info->ram_size / 2, 128 * 1024 * 1024);
677
1c7b3754 678 /* Assume that raw images are linux kernels, and ELF images are not. */
409dbce5 679 kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
92df8450
AB
680 &elf_low_addr, &elf_high_addr, big_endian,
681 elf_machine, 1);
682 if (kernel_size > 0 && have_dtb(info)) {
683 /* If there is still some room left at the base of RAM, try and put
684 * the DTB there like we do for images loaded with -bios or -pflash.
685 */
686 if (elf_low_addr > info->loader_start
687 || elf_high_addr < info->loader_start) {
688 /* Pass elf_low_addr as address limit to load_dtb if it may be
689 * pointing into RAM, otherwise pass '0' (no limit)
690 */
691 if (elf_low_addr < info->loader_start) {
692 elf_low_addr = 0;
693 }
694 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) {
695 exit(1);
696 }
697 }
698 }
1c7b3754
PB
699 entry = elf_entry;
700 if (kernel_size < 0) {
5a9154e0 701 kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
25bda50a 702 &is_linux, NULL, NULL);
1c7b3754 703 }
6f5d3cbe
RJ
704 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
705 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
706 entry = info->loader_start + kernel_load_offset;
707 kernel_size = load_image_gzipped(info->kernel_filename, entry,
708 info->ram_size - kernel_load_offset);
709 is_linux = 1;
710 }
1c7b3754 711 if (kernel_size < 0) {
4d9ebf75 712 entry = info->loader_start + kernel_load_offset;
3b760e04 713 kernel_size = load_image_targphys(info->kernel_filename, entry,
4d9ebf75 714 info->ram_size - kernel_load_offset);
1c7b3754
PB
715 is_linux = 1;
716 }
717 if (kernel_size < 0) {
f93eb9ff
AZ
718 fprintf(stderr, "qemu: could not load kernel '%s'\n",
719 info->kernel_filename);
1c7b3754
PB
720 exit(1);
721 }
f2d74978
PB
722 info->entry = entry;
723 if (is_linux) {
47b1da81
PM
724 uint32_t fixupcontext[FIXUP_MAX];
725
f93eb9ff 726 if (info->initrd_filename) {
fd76663e
SB
727 initrd_size = load_ramdisk(info->initrd_filename,
728 info->initrd_start,
729 info->ram_size -
730 info->initrd_start);
731 if (initrd_size < 0) {
732 initrd_size = load_image_targphys(info->initrd_filename,
733 info->initrd_start,
734 info->ram_size -
735 info->initrd_start);
736 }
daf90626
PB
737 if (initrd_size < 0) {
738 fprintf(stderr, "qemu: could not load initrd '%s'\n",
f93eb9ff 739 info->initrd_filename);
daf90626
PB
740 exit(1);
741 }
742 } else {
743 initrd_size = 0;
744 }
412beee6
GL
745 info->initrd_size = initrd_size;
746
47b1da81 747 fixupcontext[FIXUP_BOARDID] = info->board_id;
412beee6
GL
748
749 /* for device tree boot, we pass the DTB directly in r2. Otherwise
750 * we point to the kernel args.
751 */
83bfffec 752 if (have_dtb(info)) {
76e2aef3
AG
753 hwaddr align;
754 hwaddr dtb_start;
755
756 if (elf_machine == EM_AARCH64) {
757 /*
758 * Some AArch64 kernels on early bootup map the fdt region as
759 *
760 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
761 *
762 * Let's play safe and prealign it to 2MB to give us some space.
763 */
764 align = 2 * 1024 * 1024;
765 } else {
766 /*
767 * Some 32bit kernels will trash anything in the 4K page the
768 * initrd ends in, so make sure the DTB isn't caught up in that.
769 */
770 align = 4096;
771 }
772
773 /* Place the DTB after the initrd in memory with alignment. */
774 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align);
fee8ea12 775 if (load_dtb(dtb_start, info, 0) < 0) {
412beee6
GL
776 exit(1);
777 }
47b1da81 778 fixupcontext[FIXUP_ARGPTR] = dtb_start;
412beee6 779 } else {
47b1da81 780 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
3871481c
PM
781 if (info->ram_size >= (1ULL << 32)) {
782 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
783 " Linux kernel using ATAGS (try passing a device tree"
784 " using -dtb)\n");
785 exit(1);
786 }
412beee6 787 }
47b1da81
PM
788 fixupcontext[FIXUP_ENTRYPOINT] = entry;
789
790 write_bootloader("bootloader", info->loader_start,
4d9ebf75 791 primary_loader, fixupcontext);
47b1da81 792
52b43737 793 if (info->nb_cpus > 1) {
9543b0cd 794 info->write_secondary_boot(cpu, info);
52b43737 795 }
d8b1ae42
PM
796
797 /* Notify devices which need to fake up firmware initialization
798 * that we're doing a direct kernel boot.
799 */
800 object_child_foreach_recursive(object_get_root(),
801 do_arm_linux_init, info);
16406950 802 }
f2d74978 803 info->is_linux = is_linux;
6ed221b6 804
c6faa758
AB
805 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
806 ARM_CPU(cs)->env.boot_info = info;
6ed221b6 807 }
16406950 808}
ac9d32e3
EA
809
810void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
811{
63a183ed
EA
812 CPUState *cs;
813
ac9d32e3
EA
814 info->load_kernel_notifier.cpu = cpu;
815 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify;
816 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier);
63a183ed
EA
817
818 /* CPU objects (unlike devices) are not automatically reset on system
819 * reset, so we must always register a handler to do so. If we're
820 * actually loading a kernel, the handler is also responsible for
821 * arranging that we start it correctly.
822 */
823 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
824 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
825 }
ac9d32e3 826}
d8b1ae42
PM
827
828static const TypeInfo arm_linux_boot_if_info = {
829 .name = TYPE_ARM_LINUX_BOOT_IF,
830 .parent = TYPE_INTERFACE,
831 .class_size = sizeof(ARMLinuxBootIfClass),
832};
833
834static void arm_linux_boot_register_types(void)
835{
836 type_register_static(&arm_linux_boot_if_info);
837}
838
839type_init(arm_linux_boot_register_types)
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