[qemu.git] / hw / stellaris_enet.c

/*
 * Luminary Micro Stellaris Ethernet Controller
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */
#include "sysbus.h"
#include "net.h"
#include <zlib.h>

//#define DEBUG_STELLARIS_ENET 1

#ifdef DEBUG_STELLARIS_ENET
#define DPRINTF(fmt, ...) \
do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

#define SE_INT_RX       0x01
#define SE_INT_TXER     0x02
#define SE_INT_TXEMP    0x04
#define SE_INT_FOV      0x08
#define SE_INT_RXER     0x10
#define SE_INT_MD       0x20
#define SE_INT_PHY      0x40

#define SE_RCTL_RXEN    0x01
#define SE_RCTL_AMUL    0x02
#define SE_RCTL_PRMS    0x04
#define SE_RCTL_BADCRC  0x08
#define SE_RCTL_RSTFIFO 0x10

#define SE_TCTL_TXEN    0x01
#define SE_TCTL_PADEN   0x02
#define SE_TCTL_CRC     0x04
#define SE_TCTL_DUPLEX  0x08

typedef struct {
    SysBusDevice busdev;
    uint32_t ris;
    uint32_t im;
    uint32_t rctl;
    uint32_t tctl;
    uint32_t thr;
    uint32_t mctl;
    uint32_t mdv;
    uint32_t mtxd;
    uint32_t mrxd;
    uint32_t np;
    int tx_frame_len;
    int tx_fifo_len;
    uint8_t tx_fifo[2048];
    /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
       We implement a full 31 packet fifo.  */
    struct {
        uint8_t data[2048];
        int len;
    } rx[31];
    uint8_t *rx_fifo;
    int rx_fifo_len;
    int next_packet;
    NICState *nic;
    NICConf conf;
    qemu_irq irq;
    int mmio_index;
} stellaris_enet_state;

static void stellaris_enet_update(stellaris_enet_state *s)
{
    qemu_set_irq(s->irq, (s->ris & s->im) != 0);
}

/* TODO: Implement MAC address filtering.  */
static ssize_t stellaris_enet_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
{
    stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
    int n;
    uint8_t *p;
    uint32_t crc;

    if ((s->rctl & SE_RCTL_RXEN) == 0)
        return -1;
    if (s->np >= 31) {
        DPRINTF("Packet dropped\n");
        return -1;
    }

    DPRINTF("Received packet len=%d\n", size);
    n = s->next_packet + s->np;
    if (n >= 31)
        n -= 31;
    s->np++;

    s->rx[n].len = size + 6;
    p = s->rx[n].data;
    *(p++) = (size + 6);
    *(p++) = (size + 6) >> 8;
    memcpy (p, buf, size);
    p += size;
    crc = crc32(~0, buf, size);
    *(p++) = crc;
    *(p++) = crc >> 8;
    *(p++) = crc >> 16;
    *(p++) = crc >> 24;
    /* Clear the remaining bytes in the last word.  */
    if ((size & 3) != 2) {
        memset(p, 0, (6 - size) & 3);
    }

    s->ris |= SE_INT_RX;
    stellaris_enet_update(s);

    return size;
}

static int stellaris_enet_can_receive(VLANClientState *nc)
{
    stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;

    if ((s->rctl & SE_RCTL_RXEN) == 0)
        return 1;

    return (s->np < 31);
}

static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
    uint32_t val;

    switch (offset) {
    case 0x00: /* RIS */
        DPRINTF("IRQ status %02x\n", s->ris);
        return s->ris;
    case 0x04: /* IM */
        return s->im;
    case 0x08: /* RCTL */
        return s->rctl;
    case 0x0c: /* TCTL */
        return s->tctl;
    case 0x10: /* DATA */
        if (s->rx_fifo_len == 0) {
            if (s->np == 0) {
                BADF("RX underflow\n");
                return 0;
            }
            s->rx_fifo_len = s->rx[s->next_packet].len;
            s->rx_fifo = s->rx[s->next_packet].data;
            DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
        }
        val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
              | (s->rx_fifo[3] << 24);
        s->rx_fifo += 4;
        s->rx_fifo_len -= 4;
        if (s->rx_fifo_len <= 0) {
            s->rx_fifo_len = 0;
            s->next_packet++;
            if (s->next_packet >= 31)
                s->next_packet = 0;
            s->np--;
            DPRINTF("RX done np=%d\n", s->np);
        }
        return val;
    case 0x14: /* IA0 */
        return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
               | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
    case 0x18: /* IA1 */
        return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
    case 0x1c: /* THR */
        return s->thr;
    case 0x20: /* MCTL */
        return s->mctl;
    case 0x24: /* MDV */
        return s->mdv;
    case 0x28: /* MADD */
        return 0;
    case 0x2c: /* MTXD */
        return s->mtxd;
    case 0x30: /* MRXD */
        return s->mrxd;
    case 0x34: /* NP */
        return s->np;
    case 0x38: /* TR */
        return 0;
    case 0x3c: /* Undocuented: Timestamp? */
        return 0;
    default:
        hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;

    switch (offset) {
    case 0x00: /* IACK */
        s->ris &= ~value;
        DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
        stellaris_enet_update(s);
        /* Clearing TXER also resets the TX fifo.  */
        if (value & SE_INT_TXER)
            s->tx_frame_len = -1;
        break;
    case 0x04: /* IM */
        DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
        s->im = value;
        stellaris_enet_update(s);
        break;
    case 0x08: /* RCTL */
        s->rctl = value;
        if (value & SE_RCTL_RSTFIFO) {
            s->rx_fifo_len = 0;
            s->np = 0;
            stellaris_enet_update(s);
        }
        break;
    case 0x0c: /* TCTL */
        s->tctl = value;
        break;
    case 0x10: /* DATA */
        if (s->tx_frame_len == -1) {
            s->tx_frame_len = value & 0xffff;
            if (s->tx_frame_len > 2032) {
                DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
                s->tx_frame_len = 0;
                s->ris |= SE_INT_TXER;
                stellaris_enet_update(s);
            } else {
                DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
                /* The value written does not include the ethernet header.  */
                s->tx_frame_len += 14;
                if ((s->tctl & SE_TCTL_CRC) == 0)
                    s->tx_frame_len += 4;
                s->tx_fifo_len = 0;
                s->tx_fifo[s->tx_fifo_len++] = value >> 16;
                s->tx_fifo[s->tx_fifo_len++] = value >> 24;
            }
        } else {
            s->tx_fifo[s->tx_fifo_len++] = value;
            s->tx_fifo[s->tx_fifo_len++] = value >> 8;
            s->tx_fifo[s->tx_fifo_len++] = value >> 16;
            s->tx_fifo[s->tx_fifo_len++] = value >> 24;
            if (s->tx_fifo_len >= s->tx_frame_len) {
                /* We don't implement explicit CRC, so just chop it off.  */
                if ((s->tctl & SE_TCTL_CRC) == 0)
                    s->tx_frame_len -= 4;
                if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
                    memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
                    s->tx_fifo_len = 60;
                }
                qemu_send_packet(&s->nic->nc, s->tx_fifo, s->tx_frame_len);
                s->tx_frame_len = -1;
                s->ris |= SE_INT_TXEMP;
                stellaris_enet_update(s);
                DPRINTF("Done TX\n");
            }
        }
        break;
    case 0x14: /* IA0 */
        s->conf.macaddr.a[0] = value;
        s->conf.macaddr.a[1] = value >> 8;
        s->conf.macaddr.a[2] = value >> 16;
        s->conf.macaddr.a[3] = value >> 24;
        break;
    case 0x18: /* IA1 */
        s->conf.macaddr.a[4] = value;
        s->conf.macaddr.a[5] = value >> 8;
        break;
    case 0x1c: /* THR */
        s->thr = value;
        break;
    case 0x20: /* MCTL */
        s->mctl = value;
        break;
    case 0x24: /* MDV */
        s->mdv = value;
        break;
    case 0x28: /* MADD */
        /* ignored.  */
        break;
    case 0x2c: /* MTXD */
        s->mtxd = value & 0xff;
        break;
    case 0x30: /* MRXD */
    case 0x34: /* NP */
    case 0x38: /* TR */
        /* Ignored.  */
    case 0x3c: /* Undocuented: Timestamp? */
        /* Ignored.  */
        break;
    default:
        hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
    }
}

static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
   stellaris_enet_read,
   stellaris_enet_read,
   stellaris_enet_read
};

static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
   stellaris_enet_write,
   stellaris_enet_write,
   stellaris_enet_write
};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
    s->mdv = 0x80;
    s->rctl = SE_RCTL_BADCRC;
    s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
            | SE_INT_TXER | SE_INT_RX;
    s->thr = 0x3f;
    s->tx_frame_len = -1;
}

static void stellaris_enet_save(QEMUFile *f, void *opaque)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
    int i;

    qemu_put_be32(f, s->ris);
    qemu_put_be32(f, s->im);
    qemu_put_be32(f, s->rctl);
    qemu_put_be32(f, s->tctl);
    qemu_put_be32(f, s->thr);
    qemu_put_be32(f, s->mctl);
    qemu_put_be32(f, s->mdv);
    qemu_put_be32(f, s->mtxd);
    qemu_put_be32(f, s->mrxd);
    qemu_put_be32(f, s->np);
    qemu_put_be32(f, s->tx_frame_len);
    qemu_put_be32(f, s->tx_fifo_len);
    qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
    for (i = 0; i < 31; i++) {
        qemu_put_be32(f, s->rx[i].len);
        qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));

    }
    qemu_put_be32(f, s->next_packet);
    qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
    qemu_put_be32(f, s->rx_fifo_len);
}

static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    s->ris = qemu_get_be32(f);
    s->im = qemu_get_be32(f);
    s->rctl = qemu_get_be32(f);
    s->tctl = qemu_get_be32(f);
    s->thr = qemu_get_be32(f);
    s->mctl = qemu_get_be32(f);
    s->mdv = qemu_get_be32(f);
    s->mtxd = qemu_get_be32(f);
    s->mrxd = qemu_get_be32(f);
    s->np = qemu_get_be32(f);
    s->tx_frame_len = qemu_get_be32(f);
    s->tx_fifo_len = qemu_get_be32(f);
    qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
    for (i = 0; i < 31; i++) {
        s->rx[i].len = qemu_get_be32(f);
        qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));

    }
    s->next_packet = qemu_get_be32(f);
    s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
    s->rx_fifo_len = qemu_get_be32(f);

    return 0;
}

static void stellaris_enet_cleanup(VLANClientState *nc)
{
    stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;

    unregister_savevm("stellaris_enet", s);

    cpu_unregister_io_memory(s->mmio_index);

    qemu_free(s);
}

static NetClientInfo net_stellaris_enet_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = stellaris_enet_can_receive,
    .receive = stellaris_enet_receive,
    .cleanup = stellaris_enet_cleanup,
};

static int stellaris_enet_init(SysBusDevice *dev)
{
    stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);

    s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
                                           stellaris_enet_writefn, s);
    sysbus_init_mmio(dev, 0x1000, s->mmio_index);
    sysbus_init_irq(dev, &s->irq);
    qemu_macaddr_default_if_unset(&s->conf.macaddr);

    s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
                          dev->qdev.info->name, dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);

    stellaris_enet_reset(s);
    register_savevm("stellaris_enet", -1, 1,
                    stellaris_enet_save, stellaris_enet_load, s);
    return 0;
}

static SysBusDeviceInfo stellaris_enet_info = {
    .init = stellaris_enet_init,
    .qdev.name  = "stellaris_enet",
    .qdev.size  = sizeof(stellaris_enet_state),
    .qdev.props = (Property[]) {
        DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void stellaris_enet_register_devices(void)
{
    sysbus_register_withprop(&stellaris_enet_info);
}

device_init(stellaris_enet_register_devices)
Commit	Line	Data
eea589cc PB	1	/*
	2	* Luminary Micro Stellaris Ethernet Controller
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
a5580466	9	#include "sysbus.h"
eea589cc PB	10	#include "net.h"
	11	#include <zlib.h>
	12
	13	//#define DEBUG_STELLARIS_ENET 1
	14
	15	#ifdef DEBUG_STELLARIS_ENET
001faf32 BS	16	#define DPRINTF(fmt, ...) \
	17	do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
	18	#define BADF(fmt, ...) \
	19	do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
eea589cc	20	#else
001faf32 BS	21	#define DPRINTF(fmt, ...) do {} while(0)
	22	#define BADF(fmt, ...) \
	23	do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
eea589cc PB	24	#endif
	25
	26	#define SE_INT_RX 0x01
	27	#define SE_INT_TXER 0x02
	28	#define SE_INT_TXEMP 0x04
	29	#define SE_INT_FOV 0x08
	30	#define SE_INT_RXER 0x10
	31	#define SE_INT_MD 0x20
	32	#define SE_INT_PHY 0x40
	33
	34	#define SE_RCTL_RXEN 0x01
	35	#define SE_RCTL_AMUL 0x02
	36	#define SE_RCTL_PRMS 0x04
	37	#define SE_RCTL_BADCRC 0x08
	38	#define SE_RCTL_RSTFIFO 0x10
	39
	40	#define SE_TCTL_TXEN 0x01
	41	#define SE_TCTL_PADEN 0x02
	42	#define SE_TCTL_CRC 0x04
	43	#define SE_TCTL_DUPLEX 0x08
	44
	45	typedef struct {
a5580466	46	SysBusDevice busdev;
eea589cc PB	47	uint32_t ris;
	48	uint32_t im;
	49	uint32_t rctl;
	50	uint32_t tctl;
	51	uint32_t thr;
	52	uint32_t mctl;
	53	uint32_t mdv;
	54	uint32_t mtxd;
	55	uint32_t mrxd;
	56	uint32_t np;
	57	int tx_frame_len;
	58	int tx_fifo_len;
	59	uint8_t tx_fifo[2048];
	60	/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
	61	We implement a full 31 packet fifo. */
	62	struct {
	63	uint8_t data[2048];
	64	int len;
	65	} rx[31];
	66	uint8_t *rx_fifo;
	67	int rx_fifo_len;
	68	int next_packet;
8c9b63b9	69	NICState *nic;
540f006a	70	NICConf conf;
eea589cc	71	qemu_irq irq;
b946a153	72	int mmio_index;
eea589cc PB	73	} stellaris_enet_state;
	74
	75	static void stellaris_enet_update(stellaris_enet_state *s)
	76	{
	77	qemu_set_irq(s->irq, (s->ris & s->im) != 0);
	78	}
	79
	80	/* TODO: Implement MAC address filtering. */
8c9b63b9	81	static ssize_t stellaris_enet_receive(VLANClientState nc, const uint8_t buf, size_t size)
eea589cc	82	{
8c9b63b9	83	stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
eea589cc PB	84	int n;
	85	uint8_t *p;
	86	uint32_t crc;
	87
	88	if ((s->rctl & SE_RCTL_RXEN) == 0)
4f1c942b	89	return -1;
eea589cc PB	90	if (s->np >= 31) {
eea589cc PB	91	DPRINTF("Packet dropped\n");
4f1c942b	92	return -1;
eea589cc PB	93	}
	94
	95	DPRINTF("Received packet len=%d\n", size);
	96	n = s->next_packet + s->np;
	97	if (n >= 31)
	98	n -= 31;
	99	s->np++;
	100
	101	s->rx[n].len = size + 6;
	102	p = s->rx[n].data;
	103	*(p++) = (size + 6);
	104	*(p++) = (size + 6) >> 8;
	105	memcpy (p, buf, size);
	106	p += size;
	107	crc = crc32(~0, buf, size);
	108	*(p++) = crc;
	109	*(p++) = crc >> 8;
	110	*(p++) = crc >> 16;
	111	*(p++) = crc >> 24;
	112	/* Clear the remaining bytes in the last word. */
	113	if ((size & 3) != 2) {
	114	memset(p, 0, (6 - size) & 3);
	115	}
	116
	117	s->ris \|= SE_INT_RX;
	118	stellaris_enet_update(s);
4f1c942b MM	119
4f1c942b MM	120	return size;
eea589cc PB	121	}
eea589cc PB	122
8c9b63b9	123	static int stellaris_enet_can_receive(VLANClientState *nc)
eea589cc	124	{
8c9b63b9	125	stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
eea589cc PB	126
	127	if ((s->rctl & SE_RCTL_RXEN) == 0)
	128	return 1;
	129
	130	return (s->np < 31);
	131	}
	132
c227f099	133	static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
eea589cc	134	{
57b452a8	135	stellaris_enet_state s = (stellaris_enet_state )opaque;
eea589cc PB	136	uint32_t val;
eea589cc PB	137
eea589cc PB	138	switch (offset) {
	139	case 0x00: /* RIS */
	140	DPRINTF("IRQ status %02x\n", s->ris);
	141	return s->ris;
	142	case 0x04: /* IM */
	143	return s->im;
	144	case 0x08: /* RCTL */
	145	return s->rctl;
	146	case 0x0c: /* TCTL */
	147	return s->tctl;
	148	case 0x10: /* DATA */
	149	if (s->rx_fifo_len == 0) {
	150	if (s->np == 0) {
	151	BADF("RX underflow\n");
	152	return 0;
	153	}
	154	s->rx_fifo_len = s->rx[s->next_packet].len;
	155	s->rx_fifo = s->rx[s->next_packet].data;
	156	DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
	157	}
	158	val = s->rx_fifo[0] \| (s->rx_fifo[1] << 8) \| (s->rx_fifo[2] << 16)
	159	\| (s->rx_fifo[3] << 24);
	160	s->rx_fifo += 4;
	161	s->rx_fifo_len -= 4;
	162	if (s->rx_fifo_len <= 0) {
	163	s->rx_fifo_len = 0;
	164	s->next_packet++;
	165	if (s->next_packet >= 31)
	166	s->next_packet = 0;
	167	s->np--;
	168	DPRINTF("RX done np=%d\n", s->np);
	169	}
	170	return val;
	171	case 0x14: /* IA0 */
540f006a GH	172	return s->conf.macaddr.a[0] \| (s->conf.macaddr.a[1] << 8)
540f006a GH	173	\| (s->conf.macaddr.a[2] << 16) \| (s->conf.macaddr.a[3] << 24);
eea589cc	174	case 0x18: /* IA1 */
540f006a	175	return s->conf.macaddr.a[4] \| (s->conf.macaddr.a[5] << 8);
eea589cc PB	176	case 0x1c: /* THR */
	177	return s->thr;
	178	case 0x20: /* MCTL */
	179	return s->mctl;
	180	case 0x24: /* MDV */
	181	return s->mdv;
	182	case 0x28: /* MADD */
	183	return 0;
	184	case 0x2c: /* MTXD */
	185	return s->mtxd;
	186	case 0x30: /* MRXD */
	187	return s->mrxd;
	188	case 0x34: /* NP */
	189	return s->np;
	190	case 0x38: /* TR */
	191	return 0;
	192	case 0x3c: /* Undocuented: Timestamp? */
	193	return 0;
	194	default:
2ac71179	195	hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
eea589cc PB	196	return 0;
	197	}
	198	}
	199
c227f099	200	static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
eea589cc PB	201	uint32_t value)
	202	{
	203	stellaris_enet_state s = (stellaris_enet_state )opaque;
	204
eea589cc PB	205	switch (offset) {
	206	case 0x00: /* IACK */
	207	s->ris &= ~value;
	208	DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
	209	stellaris_enet_update(s);
	210	/* Clearing TXER also resets the TX fifo. */
	211	if (value & SE_INT_TXER)
	212	s->tx_frame_len = -1;
	213	break;
	214	case 0x04: /* IM */
	215	DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
	216	s->im = value;
	217	stellaris_enet_update(s);
	218	break;
	219	case 0x08: /* RCTL */
	220	s->rctl = value;
	221	if (value & SE_RCTL_RSTFIFO) {
	222	s->rx_fifo_len = 0;
	223	s->np = 0;
	224	stellaris_enet_update(s);
	225	}
	226	break;
	227	case 0x0c: /* TCTL */
	228	s->tctl = value;
	229	break;
	230	case 0x10: /* DATA */
	231	if (s->tx_frame_len == -1) {
	232	s->tx_frame_len = value & 0xffff;
	233	if (s->tx_frame_len > 2032) {
	234	DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
	235	s->tx_frame_len = 0;
	236	s->ris \|= SE_INT_TXER;
	237	stellaris_enet_update(s);
	238	} else {
	239	DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
	240	/* The value written does not include the ethernet header. */
	241	s->tx_frame_len += 14;
	242	if ((s->tctl & SE_TCTL_CRC) == 0)
	243	s->tx_frame_len += 4;
	244	s->tx_fifo_len = 0;
	245	s->tx_fifo[s->tx_fifo_len++] = value >> 16;
	246	s->tx_fifo[s->tx_fifo_len++] = value >> 24;
	247	}
	248	} else {
	249	s->tx_fifo[s->tx_fifo_len++] = value;
	250	s->tx_fifo[s->tx_fifo_len++] = value >> 8;
	251	s->tx_fifo[s->tx_fifo_len++] = value >> 16;
	252	s->tx_fifo[s->tx_fifo_len++] = value >> 24;
	253	if (s->tx_fifo_len >= s->tx_frame_len) {
	254	/* We don't implement explicit CRC, so just chop it off. */
	255	if ((s->tctl & SE_TCTL_CRC) == 0)
	256	s->tx_frame_len -= 4;
	257	if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
	258	memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
	259	s->tx_fifo_len = 60;
	260	}
8c9b63b9	261	qemu_send_packet(&s->nic->nc, s->tx_fifo, s->tx_frame_len);
eea589cc PB	262	s->tx_frame_len = -1;
	263	s->ris \|= SE_INT_TXEMP;
	264	stellaris_enet_update(s);
	265	DPRINTF("Done TX\n");
	266	}
	267	}
	268	break;
	269	case 0x14: /* IA0 */
540f006a GH	270	s->conf.macaddr.a[0] = value;
	271	s->conf.macaddr.a[1] = value >> 8;
	272	s->conf.macaddr.a[2] = value >> 16;
	273	s->conf.macaddr.a[3] = value >> 24;
eea589cc PB	274	break;
eea589cc PB	275	case 0x18: /* IA1 */
540f006a GH	276	s->conf.macaddr.a[4] = value;
540f006a GH	277	s->conf.macaddr.a[5] = value >> 8;
eea589cc PB	278	break;
	279	case 0x1c: /* THR */
	280	s->thr = value;
	281	break;
	282	case 0x20: /* MCTL */
	283	s->mctl = value;
	284	break;
	285	case 0x24: /* MDV */
	286	s->mdv = value;
	287	break;
	288	case 0x28: /* MADD */
	289	/* ignored. */
	290	break;
	291	case 0x2c: /* MTXD */
	292	s->mtxd = value & 0xff;
	293	break;
	294	case 0x30: /* MRXD */
	295	case 0x34: /* NP */
	296	case 0x38: /* TR */
	297	/* Ignored. */
	298	case 0x3c: /* Undocuented: Timestamp? */
	299	/* Ignored. */
	300	break;
	301	default:
2ac71179	302	hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
eea589cc PB	303	}
	304	}
	305
d60efc6b	306	static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
eea589cc PB	307	stellaris_enet_read,
	308	stellaris_enet_read,
	309	stellaris_enet_read
	310	};
	311
d60efc6b	312	static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
eea589cc PB	313	stellaris_enet_write,
	314	stellaris_enet_write,
	315	stellaris_enet_write
	316	};
	317	static void stellaris_enet_reset(stellaris_enet_state *s)
	318	{
	319	s->mdv = 0x80;
	320	s->rctl = SE_RCTL_BADCRC;
	321	s->im = SE_INT_PHY \| SE_INT_MD \| SE_INT_RXER \| SE_INT_FOV \| SE_INT_TXEMP
	322	\| SE_INT_TXER \| SE_INT_RX;
	323	s->thr = 0x3f;
	324	s->tx_frame_len = -1;
	325	}
	326
23e39294 PB	327	static void stellaris_enet_save(QEMUFile f, void opaque)
	328	{
	329	stellaris_enet_state s = (stellaris_enet_state )opaque;
	330	int i;
	331
	332	qemu_put_be32(f, s->ris);
	333	qemu_put_be32(f, s->im);
	334	qemu_put_be32(f, s->rctl);
	335	qemu_put_be32(f, s->tctl);
	336	qemu_put_be32(f, s->thr);
	337	qemu_put_be32(f, s->mctl);
	338	qemu_put_be32(f, s->mdv);
	339	qemu_put_be32(f, s->mtxd);
	340	qemu_put_be32(f, s->mrxd);
	341	qemu_put_be32(f, s->np);
	342	qemu_put_be32(f, s->tx_frame_len);
	343	qemu_put_be32(f, s->tx_fifo_len);
	344	qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
	345	for (i = 0; i < 31; i++) {
	346	qemu_put_be32(f, s->rx[i].len);
	347	qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
	348
	349	}
	350	qemu_put_be32(f, s->next_packet);
	351	qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
	352	qemu_put_be32(f, s->rx_fifo_len);
	353	}
	354
	355	static int stellaris_enet_load(QEMUFile f, void opaque, int version_id)
	356	{
	357	stellaris_enet_state s = (stellaris_enet_state )opaque;
	358	int i;
	359
	360	if (version_id != 1)
	361	return -EINVAL;
	362
	363	s->ris = qemu_get_be32(f);
	364	s->im = qemu_get_be32(f);
	365	s->rctl = qemu_get_be32(f);
	366	s->tctl = qemu_get_be32(f);
	367	s->thr = qemu_get_be32(f);
	368	s->mctl = qemu_get_be32(f);
	369	s->mdv = qemu_get_be32(f);
	370	s->mtxd = qemu_get_be32(f);
	371	s->mrxd = qemu_get_be32(f);
	372	s->np = qemu_get_be32(f);
	373	s->tx_frame_len = qemu_get_be32(f);
	374	s->tx_fifo_len = qemu_get_be32(f);
	375	qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
	376	for (i = 0; i < 31; i++) {
	377	s->rx[i].len = qemu_get_be32(f);
	378	qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
	379
	380	}
	381	s->next_packet = qemu_get_be32(f);
	382	s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
	383	s->rx_fifo_len = qemu_get_be32(f);
	384
	385	return 0;
	386	}
	387
8c9b63b9	388	static void stellaris_enet_cleanup(VLANClientState *nc)
b946a153	389	{
8c9b63b9	390	stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 AL	391
	392	unregister_savevm("stellaris_enet", s);
	393
	394	cpu_unregister_io_memory(s->mmio_index);
	395
	396	qemu_free(s);
	397	}
	398
8c9b63b9 MM	399	static NetClientInfo net_stellaris_enet_info = {
	400	.type = NET_CLIENT_TYPE_NIC,
	401	.size = sizeof(NICState),
	402	.can_receive = stellaris_enet_can_receive,
	403	.receive = stellaris_enet_receive,
	404	.cleanup = stellaris_enet_cleanup,
	405	};
	406
81a322d4	407	static int stellaris_enet_init(SysBusDevice *dev)
eea589cc	408	{
a5580466	409	stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
eea589cc	410
1eed09cb	411	s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
b946a153	412	stellaris_enet_writefn, s);
a5580466 PB	413	sysbus_init_mmio(dev, 0x1000, s->mmio_index);
a5580466 PB	414	sysbus_init_irq(dev, &s->irq);
540f006a	415	qemu_macaddr_default_if_unset(&s->conf.macaddr);
a5580466	416
8c9b63b9 MM	417	s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
	418	dev->qdev.info->name, dev->qdev.id, s);
	419	qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
eea589cc PB	420
eea589cc PB	421	stellaris_enet_reset(s);
23e39294 PB	422	register_savevm("stellaris_enet", -1, 1,
23e39294 PB	423	stellaris_enet_save, stellaris_enet_load, s);
81a322d4	424	return 0;
eea589cc	425	}
a5580466	426
540f006a GH	427	static SysBusDeviceInfo stellaris_enet_info = {
	428	.init = stellaris_enet_init,
	429	.qdev.name = "stellaris_enet",
	430	.qdev.size = sizeof(stellaris_enet_state),
	431	.qdev.props = (Property[]) {
	432	DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
	433	DEFINE_PROP_END_OF_LIST(),
	434	}
	435	};
	436
a5580466 PB	437	static void stellaris_enet_register_devices(void)
a5580466 PB	438	{
540f006a	439	sysbus_register_withprop(&stellaris_enet_info);
a5580466 PB	440	}
	441
	442	device_init(stellaris_enet_register_devices)