[qemu.git] / hw / stellaris_enet.c

/*
 * Luminary Micro Stellaris Ethernet Controller
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */
#include "sysbus.h"
#include "net.h"
#include <zlib.h>

//#define DEBUG_STELLARIS_ENET 1

#ifdef DEBUG_STELLARIS_ENET
#define DPRINTF(fmt, ...) \
do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

#define SE_INT_RX       0x01
#define SE_INT_TXER     0x02
#define SE_INT_TXEMP    0x04
#define SE_INT_FOV      0x08
#define SE_INT_RXER     0x10
#define SE_INT_MD       0x20
#define SE_INT_PHY      0x40

#define SE_RCTL_RXEN    0x01
#define SE_RCTL_AMUL    0x02
#define SE_RCTL_PRMS    0x04
#define SE_RCTL_BADCRC  0x08
#define SE_RCTL_RSTFIFO 0x10

#define SE_TCTL_TXEN    0x01
#define SE_TCTL_PADEN   0x02
#define SE_TCTL_CRC     0x04
#define SE_TCTL_DUPLEX  0x08

typedef struct {
    SysBusDevice busdev;
    uint32_t ris;
    uint32_t im;
    uint32_t rctl;
    uint32_t tctl;
    uint32_t thr;
    uint32_t mctl;
    uint32_t mdv;
    uint32_t mtxd;
    uint32_t mrxd;
    uint32_t np;
    int tx_frame_len;
    int tx_fifo_len;
    uint8_t tx_fifo[2048];
    /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
       We implement a full 31 packet fifo.  */
    struct {
        uint8_t data[2048];
        int len;
    } rx[31];
    uint8_t *rx_fifo;
    int rx_fifo_len;
    int next_packet;
    VLANClientState *vc;
    qemu_irq irq;
    uint8_t macaddr[6];
    int mmio_index;
} stellaris_enet_state;

static void stellaris_enet_update(stellaris_enet_state *s)
{
    qemu_set_irq(s->irq, (s->ris & s->im) != 0);
}

/* TODO: Implement MAC address filtering.  */
static void stellaris_enet_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
    stellaris_enet_state *s = vc->opaque;
    int n;
    uint8_t *p;
    uint32_t crc;

    if ((s->rctl & SE_RCTL_RXEN) == 0)
        return;
    if (s->np >= 31) {
        DPRINTF("Packet dropped\n");
        return;
    }

    DPRINTF("Received packet len=%d\n", size);
    n = s->next_packet + s->np;
    if (n >= 31)
        n -= 31;
    s->np++;

    s->rx[n].len = size + 6;
    p = s->rx[n].data;
    *(p++) = (size + 6);
    *(p++) = (size + 6) >> 8;
    memcpy (p, buf, size);
    p += size;
    crc = crc32(~0, buf, size);
    *(p++) = crc;
    *(p++) = crc >> 8;
    *(p++) = crc >> 16;
    *(p++) = crc >> 24;
    /* Clear the remaining bytes in the last word.  */
    if ((size & 3) != 2) {
        memset(p, 0, (6 - size) & 3);
    }

    s->ris |= SE_INT_RX;
    stellaris_enet_update(s);
}

static int stellaris_enet_can_receive(VLANClientState *vc)
{
    stellaris_enet_state *s = vc->opaque;

    if ((s->rctl & SE_RCTL_RXEN) == 0)
        return 1;

    return (s->np < 31);
}

static uint32_t stellaris_enet_read(VLANClientState *vc, target_phys_addr_t offset)
{
    stellaris_enet_state *s = vc->opaque;
    uint32_t val;

    switch (offset) {
    case 0x00: /* RIS */
        DPRINTF("IRQ status %02x\n", s->ris);
        return s->ris;
    case 0x04: /* IM */
        return s->im;
    case 0x08: /* RCTL */
        return s->rctl;
    case 0x0c: /* TCTL */
        return s->tctl;
    case 0x10: /* DATA */
        if (s->rx_fifo_len == 0) {
            if (s->np == 0) {
                BADF("RX underflow\n");
                return 0;
            }
            s->rx_fifo_len = s->rx[s->next_packet].len;
            s->rx_fifo = s->rx[s->next_packet].data;
            DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
        }
        val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
              | (s->rx_fifo[3] << 24);
        s->rx_fifo += 4;
        s->rx_fifo_len -= 4;
        if (s->rx_fifo_len <= 0) {
            s->rx_fifo_len = 0;
            s->next_packet++;
            if (s->next_packet >= 31)
                s->next_packet = 0;
            s->np--;
            DPRINTF("RX done np=%d\n", s->np);
        }
        return val;
    case 0x14: /* IA0 */
        return s->macaddr[0] | (s->macaddr[1] << 8)
               | (s->macaddr[2] << 16) | (s->macaddr[3] << 24);
    case 0x18: /* IA1 */
        return s->macaddr[4] | (s->macaddr[5] << 8);
    case 0x1c: /* THR */
        return s->thr;
    case 0x20: /* MCTL */
        return s->mctl;
    case 0x24: /* MDV */
        return s->mdv;
    case 0x28: /* MADD */
        return 0;
    case 0x2c: /* MTXD */
        return s->mtxd;
    case 0x30: /* MRXD */
        return s->mrxd;
    case 0x34: /* NP */
        return s->np;
    case 0x38: /* TR */
        return 0;
    case 0x3c: /* Undocuented: Timestamp? */
        return 0;
    default:
        hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;

    switch (offset) {
    case 0x00: /* IACK */
        s->ris &= ~value;
        DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
        stellaris_enet_update(s);
        /* Clearing TXER also resets the TX fifo.  */
        if (value & SE_INT_TXER)
            s->tx_frame_len = -1;
        break;
    case 0x04: /* IM */
        DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
        s->im = value;
        stellaris_enet_update(s);
        break;
    case 0x08: /* RCTL */
        s->rctl = value;
        if (value & SE_RCTL_RSTFIFO) {
            s->rx_fifo_len = 0;
            s->np = 0;
            stellaris_enet_update(s);
        }
        break;
    case 0x0c: /* TCTL */
        s->tctl = value;
        break;
    case 0x10: /* DATA */
        if (s->tx_frame_len == -1) {
            s->tx_frame_len = value & 0xffff;
            if (s->tx_frame_len > 2032) {
                DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
                s->tx_frame_len = 0;
                s->ris |= SE_INT_TXER;
                stellaris_enet_update(s);
            } else {
                DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
                /* The value written does not include the ethernet header.  */
                s->tx_frame_len += 14;
                if ((s->tctl & SE_TCTL_CRC) == 0)
                    s->tx_frame_len += 4;
                s->tx_fifo_len = 0;
                s->tx_fifo[s->tx_fifo_len++] = value >> 16;
                s->tx_fifo[s->tx_fifo_len++] = value >> 24;
            }
        } else {
            s->tx_fifo[s->tx_fifo_len++] = value;
            s->tx_fifo[s->tx_fifo_len++] = value >> 8;
            s->tx_fifo[s->tx_fifo_len++] = value >> 16;
            s->tx_fifo[s->tx_fifo_len++] = value >> 24;
            if (s->tx_fifo_len >= s->tx_frame_len) {
                /* We don't implement explicit CRC, so just chop it off.  */
                if ((s->tctl & SE_TCTL_CRC) == 0)
                    s->tx_frame_len -= 4;
                if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
                    memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
                    s->tx_fifo_len = 60;
                }
                qemu_send_packet(s->vc, s->tx_fifo, s->tx_frame_len);
                s->tx_frame_len = -1;
                s->ris |= SE_INT_TXEMP;
                stellaris_enet_update(s);
                DPRINTF("Done TX\n");
            }
        }
        break;
    case 0x14: /* IA0 */
        s->macaddr[0] = value;
        s->macaddr[1] = value >> 8;
        s->macaddr[2] = value >> 16;
        s->macaddr[3] = value >> 24;
        break;
    case 0x18: /* IA1 */
        s->macaddr[4] = value;
        s->macaddr[5] = value >> 8;
        break;
    case 0x1c: /* THR */
        s->thr = value;
        break;
    case 0x20: /* MCTL */
        s->mctl = value;
        break;
    case 0x24: /* MDV */
        s->mdv = value;
        break;
    case 0x28: /* MADD */
        /* ignored.  */
        break;
    case 0x2c: /* MTXD */
        s->mtxd = value & 0xff;
        break;
    case 0x30: /* MRXD */
    case 0x34: /* NP */
    case 0x38: /* TR */
        /* Ignored.  */
    case 0x3c: /* Undocuented: Timestamp? */
        /* Ignored.  */
        break;
    default:
        hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
    }
}

static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
   stellaris_enet_read,
   stellaris_enet_read,
   stellaris_enet_read
};

static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
   stellaris_enet_write,
   stellaris_enet_write,
   stellaris_enet_write
};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
    s->mdv = 0x80;
    s->rctl = SE_RCTL_BADCRC;
    s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
            | SE_INT_TXER | SE_INT_RX;
    s->thr = 0x3f;
    s->tx_frame_len = -1;
}

static void stellaris_enet_save(QEMUFile *f, void *opaque)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
    int i;

    qemu_put_be32(f, s->ris);
    qemu_put_be32(f, s->im);
    qemu_put_be32(f, s->rctl);
    qemu_put_be32(f, s->tctl);
    qemu_put_be32(f, s->thr);
    qemu_put_be32(f, s->mctl);
    qemu_put_be32(f, s->mdv);
    qemu_put_be32(f, s->mtxd);
    qemu_put_be32(f, s->mrxd);
    qemu_put_be32(f, s->np);
    qemu_put_be32(f, s->tx_frame_len);
    qemu_put_be32(f, s->tx_fifo_len);
    qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
    for (i = 0; i < 31; i++) {
        qemu_put_be32(f, s->rx[i].len);
        qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));

    }
    qemu_put_be32(f, s->next_packet);
    qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
    qemu_put_be32(f, s->rx_fifo_len);
}

static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
{
    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    s->ris = qemu_get_be32(f);
    s->im = qemu_get_be32(f);
    s->rctl = qemu_get_be32(f);
    s->tctl = qemu_get_be32(f);
    s->thr = qemu_get_be32(f);
    s->mctl = qemu_get_be32(f);
    s->mdv = qemu_get_be32(f);
    s->mtxd = qemu_get_be32(f);
    s->mrxd = qemu_get_be32(f);
    s->np = qemu_get_be32(f);
    s->tx_frame_len = qemu_get_be32(f);
    s->tx_fifo_len = qemu_get_be32(f);
    qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
    for (i = 0; i < 31; i++) {
        s->rx[i].len = qemu_get_be32(f);
        qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));

    }
    s->next_packet = qemu_get_be32(f);
    s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
    s->rx_fifo_len = qemu_get_be32(f);

    return 0;
}

static void stellaris_enet_cleanup(VLANClientState *vc)
{
    stellaris_enet_state *s = vc->opaque;

    unregister_savevm("stellaris_enet", s);

    cpu_unregister_io_memory(s->mmio_index);

    qemu_free(s);
}

static void stellaris_enet_init(SysBusDevice *dev)
{
    stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);

    s->mmio_index = cpu_register_io_memory(0, stellaris_enet_readfn,
                                           stellaris_enet_writefn, s);
    sysbus_init_mmio(dev, 0x1000, s->mmio_index);
    sysbus_init_irq(dev, &s->irq);
    qdev_get_macaddr(&dev->qdev, s->macaddr);

    s->vc = qdev_get_vlan_client(&dev->qdev,
                                 stellaris_enet_can_receive,
                                 stellaris_enet_receive, NULL,
                                 stellaris_enet_cleanup, s);
    qemu_format_nic_info_str(s->vc, s->macaddr);

    stellaris_enet_reset(s);
    register_savevm("stellaris_enet", -1, 1,
                    stellaris_enet_save, stellaris_enet_load, s);
}

static void stellaris_enet_register_devices(void)
{
    sysbus_register_dev("stellaris_enet", sizeof(stellaris_enet_state),
                        stellaris_enet_init);
}

device_init(stellaris_enet_register_devices)
Commit	Line	Data
eea589cc PB	1	/*
	2	* Luminary Micro Stellaris Ethernet Controller
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
a5580466	9	#include "sysbus.h"
eea589cc PB	10	#include "net.h"
	11	#include <zlib.h>
	12
	13	//#define DEBUG_STELLARIS_ENET 1
	14
	15	#ifdef DEBUG_STELLARIS_ENET
001faf32 BS	16	#define DPRINTF(fmt, ...) \
	17	do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
	18	#define BADF(fmt, ...) \
	19	do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
eea589cc	20	#else
001faf32 BS	21	#define DPRINTF(fmt, ...) do {} while(0)
	22	#define BADF(fmt, ...) \
	23	do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
eea589cc PB	24	#endif
	25
	26	#define SE_INT_RX 0x01
	27	#define SE_INT_TXER 0x02
	28	#define SE_INT_TXEMP 0x04
	29	#define SE_INT_FOV 0x08
	30	#define SE_INT_RXER 0x10
	31	#define SE_INT_MD 0x20
	32	#define SE_INT_PHY 0x40
	33
	34	#define SE_RCTL_RXEN 0x01
	35	#define SE_RCTL_AMUL 0x02
	36	#define SE_RCTL_PRMS 0x04
	37	#define SE_RCTL_BADCRC 0x08
	38	#define SE_RCTL_RSTFIFO 0x10
	39
	40	#define SE_TCTL_TXEN 0x01
	41	#define SE_TCTL_PADEN 0x02
	42	#define SE_TCTL_CRC 0x04
	43	#define SE_TCTL_DUPLEX 0x08
	44
	45	typedef struct {
a5580466	46	SysBusDevice busdev;
eea589cc PB	47	uint32_t ris;
	48	uint32_t im;
	49	uint32_t rctl;
	50	uint32_t tctl;
	51	uint32_t thr;
	52	uint32_t mctl;
	53	uint32_t mdv;
	54	uint32_t mtxd;
	55	uint32_t mrxd;
	56	uint32_t np;
	57	int tx_frame_len;
	58	int tx_fifo_len;
	59	uint8_t tx_fifo[2048];
	60	/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
	61	We implement a full 31 packet fifo. */
	62	struct {
	63	uint8_t data[2048];
	64	int len;
	65	} rx[31];
	66	uint8_t *rx_fifo;
	67	int rx_fifo_len;
	68	int next_packet;
	69	VLANClientState *vc;
	70	qemu_irq irq;
	71	uint8_t macaddr[6];
b946a153	72	int mmio_index;
eea589cc PB	73	} stellaris_enet_state;
	74
	75	static void stellaris_enet_update(stellaris_enet_state *s)
	76	{
	77	qemu_set_irq(s->irq, (s->ris & s->im) != 0);
	78	}
	79
	80	/* TODO: Implement MAC address filtering. */
e3f5ec2b	81	static void stellaris_enet_receive(VLANClientState vc, const uint8_t buf, size_t size)
eea589cc	82	{
e3f5ec2b	83	stellaris_enet_state *s = vc->opaque;
eea589cc PB	84	int n;
	85	uint8_t *p;
	86	uint32_t crc;
	87
	88	if ((s->rctl & SE_RCTL_RXEN) == 0)
	89	return;
	90	if (s->np >= 31) {
	91	DPRINTF("Packet dropped\n");
	92	return;
	93	}
	94
	95	DPRINTF("Received packet len=%d\n", size);
	96	n = s->next_packet + s->np;
	97	if (n >= 31)
	98	n -= 31;
	99	s->np++;
	100
	101	s->rx[n].len = size + 6;
	102	p = s->rx[n].data;
	103	*(p++) = (size + 6);
	104	*(p++) = (size + 6) >> 8;
	105	memcpy (p, buf, size);
	106	p += size;
	107	crc = crc32(~0, buf, size);
	108	*(p++) = crc;
	109	*(p++) = crc >> 8;
	110	*(p++) = crc >> 16;
	111	*(p++) = crc >> 24;
	112	/* Clear the remaining bytes in the last word. */
	113	if ((size & 3) != 2) {
	114	memset(p, 0, (6 - size) & 3);
	115	}
	116
	117	s->ris \|= SE_INT_RX;
	118	stellaris_enet_update(s);
	119	}
	120
e3f5ec2b	121	static int stellaris_enet_can_receive(VLANClientState *vc)
eea589cc	122	{
e3f5ec2b	123	stellaris_enet_state *s = vc->opaque;
eea589cc PB	124
	125	if ((s->rctl & SE_RCTL_RXEN) == 0)
	126	return 1;
	127
	128	return (s->np < 31);
	129	}
	130
e3f5ec2b	131	static uint32_t stellaris_enet_read(VLANClientState *vc, target_phys_addr_t offset)
eea589cc	132	{
e3f5ec2b	133	stellaris_enet_state *s = vc->opaque;
eea589cc PB	134	uint32_t val;
eea589cc PB	135
eea589cc PB	136	switch (offset) {
	137	case 0x00: /* RIS */
	138	DPRINTF("IRQ status %02x\n", s->ris);
	139	return s->ris;
	140	case 0x04: /* IM */
	141	return s->im;
	142	case 0x08: /* RCTL */
	143	return s->rctl;
	144	case 0x0c: /* TCTL */
	145	return s->tctl;
	146	case 0x10: /* DATA */
	147	if (s->rx_fifo_len == 0) {
	148	if (s->np == 0) {
	149	BADF("RX underflow\n");
	150	return 0;
	151	}
	152	s->rx_fifo_len = s->rx[s->next_packet].len;
	153	s->rx_fifo = s->rx[s->next_packet].data;
	154	DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
	155	}
	156	val = s->rx_fifo[0] \| (s->rx_fifo[1] << 8) \| (s->rx_fifo[2] << 16)
	157	\| (s->rx_fifo[3] << 24);
	158	s->rx_fifo += 4;
	159	s->rx_fifo_len -= 4;
	160	if (s->rx_fifo_len <= 0) {
	161	s->rx_fifo_len = 0;
	162	s->next_packet++;
	163	if (s->next_packet >= 31)
	164	s->next_packet = 0;
	165	s->np--;
	166	DPRINTF("RX done np=%d\n", s->np);
	167	}
	168	return val;
	169	case 0x14: /* IA0 */
	170	return s->macaddr[0] \| (s->macaddr[1] << 8)
	171	\| (s->macaddr[2] << 16) \| (s->macaddr[3] << 24);
	172	case 0x18: /* IA1 */
	173	return s->macaddr[4] \| (s->macaddr[5] << 8);
	174	case 0x1c: /* THR */
	175	return s->thr;
	176	case 0x20: /* MCTL */
	177	return s->mctl;
	178	case 0x24: /* MDV */
	179	return s->mdv;
	180	case 0x28: /* MADD */
	181	return 0;
	182	case 0x2c: /* MTXD */
	183	return s->mtxd;
	184	case 0x30: /* MRXD */
	185	return s->mrxd;
	186	case 0x34: /* NP */
	187	return s->np;
	188	case 0x38: /* TR */
	189	return 0;
	190	case 0x3c: /* Undocuented: Timestamp? */
	191	return 0;
	192	default:
2ac71179	193	hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
eea589cc PB	194	return 0;
	195	}
	196	}
	197
	198	static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
	199	uint32_t value)
	200	{
	201	stellaris_enet_state s = (stellaris_enet_state )opaque;
	202
eea589cc PB	203	switch (offset) {
	204	case 0x00: /* IACK */
	205	s->ris &= ~value;
	206	DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
	207	stellaris_enet_update(s);
	208	/* Clearing TXER also resets the TX fifo. */
	209	if (value & SE_INT_TXER)
	210	s->tx_frame_len = -1;
	211	break;
	212	case 0x04: /* IM */
	213	DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
	214	s->im = value;
	215	stellaris_enet_update(s);
	216	break;
	217	case 0x08: /* RCTL */
	218	s->rctl = value;
	219	if (value & SE_RCTL_RSTFIFO) {
	220	s->rx_fifo_len = 0;
	221	s->np = 0;
	222	stellaris_enet_update(s);
	223	}
	224	break;
	225	case 0x0c: /* TCTL */
	226	s->tctl = value;
	227	break;
	228	case 0x10: /* DATA */
	229	if (s->tx_frame_len == -1) {
	230	s->tx_frame_len = value & 0xffff;
	231	if (s->tx_frame_len > 2032) {
	232	DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
	233	s->tx_frame_len = 0;
	234	s->ris \|= SE_INT_TXER;
	235	stellaris_enet_update(s);
	236	} else {
	237	DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
	238	/* The value written does not include the ethernet header. */
	239	s->tx_frame_len += 14;
	240	if ((s->tctl & SE_TCTL_CRC) == 0)
	241	s->tx_frame_len += 4;
	242	s->tx_fifo_len = 0;
	243	s->tx_fifo[s->tx_fifo_len++] = value >> 16;
	244	s->tx_fifo[s->tx_fifo_len++] = value >> 24;
	245	}
	246	} else {
	247	s->tx_fifo[s->tx_fifo_len++] = value;
	248	s->tx_fifo[s->tx_fifo_len++] = value >> 8;
	249	s->tx_fifo[s->tx_fifo_len++] = value >> 16;
	250	s->tx_fifo[s->tx_fifo_len++] = value >> 24;
	251	if (s->tx_fifo_len >= s->tx_frame_len) {
	252	/* We don't implement explicit CRC, so just chop it off. */
	253	if ((s->tctl & SE_TCTL_CRC) == 0)
	254	s->tx_frame_len -= 4;
	255	if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
	256	memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
	257	s->tx_fifo_len = 60;
	258	}
	259	qemu_send_packet(s->vc, s->tx_fifo, s->tx_frame_len);
	260	s->tx_frame_len = -1;
	261	s->ris \|= SE_INT_TXEMP;
	262	stellaris_enet_update(s);
	263	DPRINTF("Done TX\n");
	264	}
	265	}
	266	break;
267	case 0x14: /* IA0 */
268	s->macaddr[0] = value;
269	s->macaddr[1] = value >> 8;
270	s->macaddr[2] = value >> 16;
271	s->macaddr[3] = value >> 24;
272	break;
273	case 0x18: /* IA1 */
274	s->macaddr[4] = value;
275	s->macaddr[5] = value >> 8;
276	break;
277	case 0x1c: /* THR */
278	s->thr = value;
279	break;
280	case 0x20: /* MCTL */
281	s->mctl = value;
282	break;
283	case 0x24: /* MDV */
284	s->mdv = value;
285	break;
286	case 0x28: /* MADD */
287	/* ignored. */
288	break;
289	case 0x2c: /* MTXD */
290	s->mtxd = value & 0xff;
291	break;
292	case 0x30: /* MRXD */
293	case 0x34: /* NP */
294	case 0x38: /* TR */
295	/* Ignored. */
296	case 0x3c: /* Undocuented: Timestamp? */
297	/* Ignored. */
298	break;
299	default:
2ac71179	300	hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
eea589cc PB	301	}
	302	}
	303
	304	static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
	305	stellaris_enet_read,
	306	stellaris_enet_read,
	307	stellaris_enet_read
	308	};
	309
	310	static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
	311	stellaris_enet_write,
	312	stellaris_enet_write,
	313	stellaris_enet_write
	314	};
	315	static void stellaris_enet_reset(stellaris_enet_state *s)
	316	{
	317	s->mdv = 0x80;
	318	s->rctl = SE_RCTL_BADCRC;
	319	s->im = SE_INT_PHY \| SE_INT_MD \| SE_INT_RXER \| SE_INT_FOV \| SE_INT_TXEMP
	320	\| SE_INT_TXER \| SE_INT_RX;
	321	s->thr = 0x3f;
	322	s->tx_frame_len = -1;
	323	}
	324
23e39294 PB	325	static void stellaris_enet_save(QEMUFile f, void opaque)
	326	{
	327	stellaris_enet_state s = (stellaris_enet_state )opaque;
	328	int i;
	329
	330	qemu_put_be32(f, s->ris);
	331	qemu_put_be32(f, s->im);
	332	qemu_put_be32(f, s->rctl);
	333	qemu_put_be32(f, s->tctl);
	334	qemu_put_be32(f, s->thr);
	335	qemu_put_be32(f, s->mctl);
	336	qemu_put_be32(f, s->mdv);
	337	qemu_put_be32(f, s->mtxd);
	338	qemu_put_be32(f, s->mrxd);
	339	qemu_put_be32(f, s->np);
	340	qemu_put_be32(f, s->tx_frame_len);
	341	qemu_put_be32(f, s->tx_fifo_len);
	342	qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
	343	for (i = 0; i < 31; i++) {
	344	qemu_put_be32(f, s->rx[i].len);
	345	qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
	346
	347	}
	348	qemu_put_be32(f, s->next_packet);
	349	qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
	350	qemu_put_be32(f, s->rx_fifo_len);
	351	}
	352
	353	static int stellaris_enet_load(QEMUFile f, void opaque, int version_id)
	354	{
	355	stellaris_enet_state s = (stellaris_enet_state )opaque;
	356	int i;
	357
	358	if (version_id != 1)
	359	return -EINVAL;
	360
	361	s->ris = qemu_get_be32(f);
	362	s->im = qemu_get_be32(f);
	363	s->rctl = qemu_get_be32(f);
	364	s->tctl = qemu_get_be32(f);
	365	s->thr = qemu_get_be32(f);
	366	s->mctl = qemu_get_be32(f);
	367	s->mdv = qemu_get_be32(f);
	368	s->mtxd = qemu_get_be32(f);
	369	s->mrxd = qemu_get_be32(f);
	370	s->np = qemu_get_be32(f);
	371	s->tx_frame_len = qemu_get_be32(f);
	372	s->tx_fifo_len = qemu_get_be32(f);
	373	qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
	374	for (i = 0; i < 31; i++) {
	375	s->rx[i].len = qemu_get_be32(f);
	376	qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
	377
	378	}
	379	s->next_packet = qemu_get_be32(f);
	380	s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
	381	s->rx_fifo_len = qemu_get_be32(f);
	382
	383	return 0;
	384	}
	385
b946a153 AL	386	static void stellaris_enet_cleanup(VLANClientState *vc)
	387	{
	388	stellaris_enet_state *s = vc->opaque;
	389
	390	unregister_savevm("stellaris_enet", s);
	391
	392	cpu_unregister_io_memory(s->mmio_index);
	393
	394	qemu_free(s);
	395	}
	396
a5580466	397	static void stellaris_enet_init(SysBusDevice *dev)
eea589cc	398	{
a5580466	399	stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
eea589cc	400
b946a153 AL	401	s->mmio_index = cpu_register_io_memory(0, stellaris_enet_readfn,
b946a153 AL	402	stellaris_enet_writefn, s);
a5580466 PB	403	sysbus_init_mmio(dev, 0x1000, s->mmio_index);
	404	sysbus_init_irq(dev, &s->irq);
	405	qdev_get_macaddr(&dev->qdev, s->macaddr);
	406
	407	s->vc = qdev_get_vlan_client(&dev->qdev,
a5580466	408	stellaris_enet_can_receive,
463af534	409	stellaris_enet_receive, NULL,
a5580466 PB	410	stellaris_enet_cleanup, s);
a5580466 PB	411	qemu_format_nic_info_str(s->vc, s->macaddr);
eea589cc PB	412
eea589cc PB	413	stellaris_enet_reset(s);
23e39294 PB	414	register_savevm("stellaris_enet", -1, 1,
23e39294 PB	415	stellaris_enet_save, stellaris_enet_load, s);
eea589cc	416	}
a5580466 PB	417
	418	static void stellaris_enet_register_devices(void)
	419	{
	420	sysbus_register_dev("stellaris_enet", sizeof(stellaris_enet_state),
	421	stellaris_enet_init);
	422	}
	423
	424	device_init(stellaris_enet_register_devices)