[qemu.git] / hw / pl110.c

/*
 * Arm PrimeCell PL110 Color LCD Controller
 *
 * Copyright (c) 2005-2009 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GNU LGPL
 */

#include "sysbus.h"
#include "console.h"
#include "framebuffer.h"

#define PL110_CR_EN   0x001
#define PL110_CR_BGR  0x100
#define PL110_CR_BEBO 0x200
#define PL110_CR_BEPO 0x400
#define PL110_CR_PWR  0x800

enum pl110_bppmode
{
    BPP_1,
    BPP_2,
    BPP_4,
    BPP_8,
    BPP_16,
    BPP_32,
    BPP_16_565, /* PL111 only */
    BPP_12      /* PL111 only */
};


/* The Versatile/PB uses a slightly modified PL110 controller.  */
enum pl110_version
{
    PL110,
    PL110_VERSATILE,
    PL111
};

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    DisplayState *ds;

    int version;
    uint32_t timing[4];
    uint32_t cr;
    uint32_t upbase;
    uint32_t lpbase;
    uint32_t int_status;
    uint32_t int_mask;
    int cols;
    int rows;
    enum pl110_bppmode bpp;
    int invalidate;
    uint32_t mux_ctrl;
    uint32_t pallette[256];
    uint32_t raw_pallette[128];
    qemu_irq irq;
} pl110_state;

static int vmstate_pl110_post_load(void *opaque, int version_id);

static const VMStateDescription vmstate_pl110 = {
    .name = "pl110",
    .version_id = 2,
    .minimum_version_id = 1,
    .post_load = vmstate_pl110_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(version, pl110_state),
        VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
        VMSTATE_UINT32(cr, pl110_state),
        VMSTATE_UINT32(upbase, pl110_state),
        VMSTATE_UINT32(lpbase, pl110_state),
        VMSTATE_UINT32(int_status, pl110_state),
        VMSTATE_UINT32(int_mask, pl110_state),
        VMSTATE_INT32(cols, pl110_state),
        VMSTATE_INT32(rows, pl110_state),
        VMSTATE_UINT32(bpp, pl110_state),
        VMSTATE_INT32(invalidate, pl110_state),
        VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
        VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
        VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
   has a different ID.  However Linux only looks for the normal ID.  */
#if 0
static const unsigned char pl110_versatile_id[] =
{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#else
#define pl110_versatile_id pl110_id
#endif

static const unsigned char pl111_id[] = {
    0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};

/* Indexed by pl110_version */
static const unsigned char *idregs[] = {
    pl110_id,
    pl110_versatile_id,
    pl111_id
};

#include "pixel_ops.h"

#define BITS 8
#include "pl110_template.h"
#define BITS 15
#include "pl110_template.h"
#define BITS 16
#include "pl110_template.h"
#define BITS 24
#include "pl110_template.h"
#define BITS 32
#include "pl110_template.h"

static int pl110_enabled(pl110_state *s)
{
  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}

static void pl110_update_display(void *opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    drawfn* fntable;
    drawfn fn;
    int dest_width;
    int src_width;
    int bpp_offset;
    int first;
    int last;

    if (!pl110_enabled(s))
        return;

    switch (ds_get_bits_per_pixel(s->ds)) {
    case 0:
        return;
    case 8:
        fntable = pl110_draw_fn_8;
        dest_width = 1;
        break;
    case 15:
        fntable = pl110_draw_fn_15;
        dest_width = 2;
        break;
    case 16:
        fntable = pl110_draw_fn_16;
        dest_width = 2;
        break;
    case 24:
        fntable = pl110_draw_fn_24;
        dest_width = 3;
        break;
    case 32:
        fntable = pl110_draw_fn_32;
        dest_width = 4;
        break;
    default:
        fprintf(stderr, "pl110: Bad color depth\n");
        exit(1);
    }
    if (s->cr & PL110_CR_BGR)
        bpp_offset = 0;
    else
        bpp_offset = 24;

    if ((s->version != PL111) && (s->bpp == BPP_16)) {
        /* The PL110's native 16 bit mode is 5551; however
         * most boards with a PL110 implement an external
         * mux which allows bits to be reshuffled to give
         * 565 format. The mux is typically controlled by
         * an external system register.
         * This is controlled by a GPIO input pin
         * so boards can wire it up to their register.
         *
         * The PL111 straightforwardly implements both
         * 5551 and 565 under control of the bpp field
         * in the LCDControl register.
         */
        switch (s->mux_ctrl) {
        case 3: /* 565 BGR */
            bpp_offset = (BPP_16_565 - BPP_16);
            break;
        case 1: /* 5551 */
            break;
        case 0: /* 888; also if we have loaded vmstate from an old version */
        case 2: /* 565 RGB */
        default:
            /* treat as 565 but honour BGR bit */
            bpp_offset += (BPP_16_565 - BPP_16);
            break;
        }
    }

    if (s->cr & PL110_CR_BEBO)
        fn = fntable[s->bpp + 8 + bpp_offset];
    else if (s->cr & PL110_CR_BEPO)
        fn = fntable[s->bpp + 16 + bpp_offset];
    else
        fn = fntable[s->bpp + bpp_offset];

    src_width = s->cols;
    switch (s->bpp) {
    case BPP_1:
        src_width >>= 3;
        break;
    case BPP_2:
        src_width >>= 2;
        break;
    case BPP_4:
        src_width >>= 1;
        break;
    case BPP_8:
        break;
    case BPP_16:
    case BPP_16_565:
    case BPP_12:
        src_width <<= 1;
        break;
    case BPP_32:
        src_width <<= 2;
        break;
    }
    dest_width *= s->cols;
    first = 0;
    framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
                               s->upbase, s->cols, s->rows,
                               src_width, dest_width, 0,
                               s->invalidate,
                               fn, s->pallette,
                               &first, &last);
    if (first >= 0) {
        dpy_update(s->ds, 0, first, s->cols, last - first + 1);
    }
    s->invalidate = 0;
}

static void pl110_invalidate_display(void * opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    s->invalidate = 1;
    if (pl110_enabled(s)) {
        qemu_console_resize(s->ds, s->cols, s->rows);
    }
}

static void pl110_update_pallette(pl110_state *s, int n)
{
    int i;
    uint32_t raw;
    unsigned int r, g, b;

    raw = s->raw_pallette[n];
    n <<= 1;
    for (i = 0; i < 2; i++) {
        r = (raw & 0x1f) << 3;
        raw >>= 5;
        g = (raw & 0x1f) << 3;
        raw >>= 5;
        b = (raw & 0x1f) << 3;
        /* The I bit is ignored.  */
        raw >>= 6;
        switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            s->pallette[n] = rgb_to_pixel8(r, g, b);
            break;
        case 15:
            s->pallette[n] = rgb_to_pixel15(r, g, b);
            break;
        case 16:
            s->pallette[n] = rgb_to_pixel16(r, g, b);
            break;
        case 24:
        case 32:
            s->pallette[n] = rgb_to_pixel32(r, g, b);
            break;
        }
        n++;
    }
}

static void pl110_resize(pl110_state *s, int width, int height)
{
    if (width != s->cols || height != s->rows) {
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, width, height);
        }
    }
    s->cols = width;
    s->rows = height;
}

/* Update interrupts.  */
static void pl110_update(pl110_state *s)
{
  /* TODO: Implement interrupts.  */
}

static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
                           unsigned size)
{
    pl110_state *s = (pl110_state *)opaque;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return idregs[s->version][(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x200 && offset < 0x400) {
        return s->raw_pallette[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        return s->timing[0];
    case 1: /* LCDTiming1 */
        return s->timing[1];
    case 2: /* LCDTiming2 */
        return s->timing[2];
    case 3: /* LCDTiming3 */
        return s->timing[3];
    case 4: /* LCDUPBASE */
        return s->upbase;
    case 5: /* LCDLPBASE */
        return s->lpbase;
    case 6: /* LCDIMSC */
        if (s->version != PL110) {
            return s->cr;
        }
        return s->int_mask;
    case 7: /* LCDControl */
        if (s->version != PL110) {
            return s->int_mask;
        }
        return s->cr;
    case 8: /* LCDRIS */
        return s->int_status;
    case 9: /* LCDMIS */
        return s->int_status & s->int_mask;
    case 11: /* LCDUPCURR */
        /* TODO: Implement vertical refresh.  */
        return s->upbase;
    case 12: /* LCDLPCURR */
        return s->lpbase;
    default:
        hw_error("pl110_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl110_write(void *opaque, target_phys_addr_t offset,
                        uint64_t val, unsigned size)
{
    pl110_state *s = (pl110_state *)opaque;
    int n;

    /* For simplicity invalidate the display whenever a control register
       is written to.  */
    s->invalidate = 1;
    if (offset >= 0x200 && offset < 0x400) {
        /* Pallette.  */
        n = (offset - 0x200) >> 2;
        s->raw_pallette[(offset - 0x200) >> 2] = val;
        pl110_update_pallette(s, n);
        return;
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        s->timing[0] = val;
        n = ((val & 0xfc) + 4) * 4;
        pl110_resize(s, n, s->rows);
        break;
    case 1: /* LCDTiming1 */
        s->timing[1] = val;
        n = (val & 0x3ff) + 1;
        pl110_resize(s, s->cols, n);
        break;
    case 2: /* LCDTiming2 */
        s->timing[2] = val;
        break;
    case 3: /* LCDTiming3 */
        s->timing[3] = val;
        break;
    case 4: /* LCDUPBASE */
        s->upbase = val;
        break;
    case 5: /* LCDLPBASE */
        s->lpbase = val;
        break;
    case 6: /* LCDIMSC */
        if (s->version != PL110) {
            goto control;
        }
    imsc:
        s->int_mask = val;
        pl110_update(s);
        break;
    case 7: /* LCDControl */
        if (s->version != PL110) {
            goto imsc;
        }
    control:
        s->cr = val;
        s->bpp = (val >> 1) & 7;
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, s->cols, s->rows);
        }
        break;
    case 10: /* LCDICR */
        s->int_status &= ~val;
        pl110_update(s);
        break;
    default:
        hw_error("pl110_write: Bad offset %x\n", (int)offset);
    }
}

static const MemoryRegionOps pl110_ops = {
    .read = pl110_read,
    .write = pl110_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl110_mux_ctrl_set(void *opaque, int line, int level)
{
    pl110_state *s = (pl110_state *)opaque;
    s->mux_ctrl = level;
}

static int vmstate_pl110_post_load(void *opaque, int version_id)
{
    pl110_state *s = opaque;
    /* Make sure we redraw, and at the right size */
    pl110_invalidate_display(s);
    return 0;
}

static int pl110_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);

    memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq);
    qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
    s->ds = graphic_console_init(pl110_update_display,
                                 pl110_invalidate_display,
                                 NULL, NULL, s);
    return 0;
}

static int pl110_versatile_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
    s->version = PL110_VERSATILE;
    return pl110_init(dev);
}

static int pl111_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
    s->version = PL111;
    return pl110_init(dev);
}

static void pl110_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl110_init;
    dc->no_user = 1;
    dc->vmsd = &vmstate_pl110;
}

static TypeInfo pl110_info = {
    .name          = "pl110",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(pl110_state),
    .class_init    = pl110_class_init,
};

static void pl110_versatile_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl110_versatile_init;
    dc->no_user = 1;
    dc->vmsd = &vmstate_pl110;
}

static TypeInfo pl110_versatile_info = {
    .name          = "pl110_versatile",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(pl110_state),
    .class_init    = pl110_versatile_class_init,
};

static void pl111_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl111_init;
    dc->no_user = 1;
    dc->vmsd = &vmstate_pl110;
}

static TypeInfo pl111_info = {
    .name          = "pl111",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(pl110_state),
    .class_init    = pl111_class_init,
};

static void pl110_register_types(void)
{
    type_register_static(&pl110_info);
    type_register_static(&pl110_versatile_info);
    type_register_static(&pl111_info);
}

type_init(pl110_register_types)
Commit	Line	Data
5fafdf24	1	/*
bdd5003a PB	2	* Arm PrimeCell PL110 Color LCD Controller
bdd5003a PB	3	*
2e9bdce5	4	* Copyright (c) 2005-2009 CodeSourcery.
bdd5003a PB	5	* Written by Paul Brook
bdd5003a PB	6	*
8e31bf38	7	* This code is licensed under the GNU LGPL
bdd5003a PB	8	*/
bdd5003a PB	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b	11	#include "console.h"
714fa308	12	#include "framebuffer.h"
bdd5003a PB	13
bdd5003a PB	14	#define PL110_CR_EN 0x001
e9c05b42	15	#define PL110_CR_BGR 0x100
bdd5003a PB	16	#define PL110_CR_BEBO 0x200
	17	#define PL110_CR_BEPO 0x400
	18	#define PL110_CR_PWR 0x800
	19
	20	enum pl110_bppmode
	21	{
	22	BPP_1,
	23	BPP_2,
	24	BPP_4,
	25	BPP_8,
	26	BPP_16,
4fbf5556 PM	27	BPP_32,
	28	BPP_16_565, /* PL111 only */
	29	BPP_12 /* PL111 only */
	30	};
	31
	32
	33	/* The Versatile/PB uses a slightly modified PL110 controller. */
	34	enum pl110_version
	35	{
	36	PL110,
	37	PL110_VERSATILE,
	38	PL111
bdd5003a PB	39	};
	40
	41	typedef struct {
2e9bdce5	42	SysBusDevice busdev;
1a6b31ce	43	MemoryRegion iomem;
bdd5003a	44	DisplayState *ds;
c60e08d9	45
4fbf5556	46	int version;
bdd5003a PB	47	uint32_t timing[4];
	48	uint32_t cr;
	49	uint32_t upbase;
	50	uint32_t lpbase;
	51	uint32_t int_status;
	52	uint32_t int_mask;
	53	int cols;
	54	int rows;
	55	enum pl110_bppmode bpp;
	56	int invalidate;
242ea2c6	57	uint32_t mux_ctrl;
bdd5003a PB	58	uint32_t pallette[256];
bdd5003a PB	59	uint32_t raw_pallette[128];
d537cf6c	60	qemu_irq irq;
bdd5003a PB	61	} pl110_state;
bdd5003a PB	62
128939a9 PM	63	static int vmstate_pl110_post_load(void *opaque, int version_id);
128939a9 PM	64
8c60d065 PM	65	static const VMStateDescription vmstate_pl110 = {
8c60d065 PM	66	.name = "pl110",
242ea2c6	67	.version_id = 2,
8c60d065	68	.minimum_version_id = 1,
128939a9	69	.post_load = vmstate_pl110_post_load,
8c60d065	70	.fields = (VMStateField[]) {
4fbf5556	71	VMSTATE_INT32(version, pl110_state),
8c60d065 PM	72	VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
	73	VMSTATE_UINT32(cr, pl110_state),
	74	VMSTATE_UINT32(upbase, pl110_state),
	75	VMSTATE_UINT32(lpbase, pl110_state),
	76	VMSTATE_UINT32(int_status, pl110_state),
	77	VMSTATE_UINT32(int_mask, pl110_state),
	78	VMSTATE_INT32(cols, pl110_state),
	79	VMSTATE_INT32(rows, pl110_state),
	80	VMSTATE_UINT32(bpp, pl110_state),
	81	VMSTATE_INT32(invalidate, pl110_state),
	82	VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
	83	VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
242ea2c6	84	VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
8c60d065 PM	85	VMSTATE_END_OF_LIST()
	86	}
	87	};
	88
bdd5003a PB	89	static const unsigned char pl110_id[] =
	90	{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	91
cdbdb648 PB	92	/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
	93	has a different ID. However Linux only looks for the normal ID. */
	94	#if 0
	95	static const unsigned char pl110_versatile_id[] =
	96	{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	97	#else
	98	#define pl110_versatile_id pl110_id
	99	#endif
	100
4fbf5556 PM	101	static const unsigned char pl111_id[] = {
	102	0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
	103	};
	104
	105	/* Indexed by pl110_version */
	106	static const unsigned char *idregs[] = {
	107	pl110_id,
	108	pl110_versatile_id,
	109	pl111_id
	110	};
	111
602dafcf	112	#include "pixel_ops.h"
bdd5003a	113
bdd5003a PB	114	#define BITS 8
	115	#include "pl110_template.h"
	116	#define BITS 15
	117	#include "pl110_template.h"
	118	#define BITS 16
	119	#include "pl110_template.h"
	120	#define BITS 24
	121	#include "pl110_template.h"
	122	#define BITS 32
	123	#include "pl110_template.h"
	124
	125	static int pl110_enabled(pl110_state *s)
	126	{
	127	return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
	128	}
	129
95219897	130	static void pl110_update_display(void *opaque)
bdd5003a PB	131	{
	132	pl110_state s = (pl110_state )opaque;
	133	drawfn* fntable;
	134	drawfn fn;
bdd5003a PB	135	int dest_width;
bdd5003a PB	136	int src_width;
e9c05b42	137	int bpp_offset;
714fa308 PB	138	int first;
714fa308 PB	139	int last;
bdd5003a PB	140
	141	if (!pl110_enabled(s))
	142	return;
3b46e624	143
0e1f5a0c	144	switch (ds_get_bits_per_pixel(s->ds)) {
af2f6733 PB	145	case 0:
af2f6733 PB	146	return;
bdd5003a PB	147	case 8:
	148	fntable = pl110_draw_fn_8;
	149	dest_width = 1;
	150	break;
	151	case 15:
	152	fntable = pl110_draw_fn_15;
	153	dest_width = 2;
	154	break;
	155	case 16:
	156	fntable = pl110_draw_fn_16;
	157	dest_width = 2;
	158	break;
	159	case 24:
	160	fntable = pl110_draw_fn_24;
	161	dest_width = 3;
	162	break;
	163	case 32:
	164	fntable = pl110_draw_fn_32;
	165	dest_width = 4;
	166	break;
	167	default:
af2f6733	168	fprintf(stderr, "pl110: Bad color depth\n");
bdd5003a PB	169	exit(1);
bdd5003a PB	170	}
e9c05b42 AZ	171	if (s->cr & PL110_CR_BGR)
	172	bpp_offset = 0;
	173	else
4fbf5556 PM	174	bpp_offset = 24;
	175
	176	if ((s->version != PL111) && (s->bpp == BPP_16)) {
	177	/* The PL110's native 16 bit mode is 5551; however
	178	* most boards with a PL110 implement an external
	179	* mux which allows bits to be reshuffled to give
	180	* 565 format. The mux is typically controlled by
	181	* an external system register.
242ea2c6	182	* This is controlled by a GPIO input pin
4fbf5556	183	* so boards can wire it up to their register.
4fbf5556 PM	184	*
	185	* The PL111 straightforwardly implements both
	186	* 5551 and 565 under control of the bpp field
	187	* in the LCDControl register.
	188	*/
242ea2c6 PM	189	switch (s->mux_ctrl) {
	190	case 3: /* 565 BGR */
	191	bpp_offset = (BPP_16_565 - BPP_16);
	192	break;
	193	case 1: /* 5551 */
	194	break;
	195	case 0: /* 888; also if we have loaded vmstate from an old version */
	196	case 2: /* 565 RGB */
	197	default:
	198	/* treat as 565 but honour BGR bit */
	199	bpp_offset += (BPP_16_565 - BPP_16);
	200	break;
	201	}
4fbf5556	202	}
e9c05b42	203
bdd5003a	204	if (s->cr & PL110_CR_BEBO)
4fbf5556	205	fn = fntable[s->bpp + 8 + bpp_offset];
bdd5003a	206	else if (s->cr & PL110_CR_BEPO)
4fbf5556	207	fn = fntable[s->bpp + 16 + bpp_offset];
bdd5003a	208	else
e9c05b42	209	fn = fntable[s->bpp + bpp_offset];
3b46e624	210
bdd5003a PB	211	src_width = s->cols;
	212	switch (s->bpp) {
	213	case BPP_1:
	214	src_width >>= 3;
	215	break;
	216	case BPP_2:
	217	src_width >>= 2;
	218	break;
	219	case BPP_4:
	220	src_width >>= 1;
	221	break;
	222	case BPP_8:
	223	break;
	224	case BPP_16:
4fbf5556 PM	225	case BPP_16_565:
4fbf5556 PM	226	case BPP_12:
bdd5003a PB	227	src_width <<= 1;
	228	break;
	229	case BPP_32:
	230	src_width <<= 2;
	231	break;
	232	}
	233	dest_width *= s->cols;
714fa308	234	first = 0;
75c9d6c2	235	framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
714fa308 PB	236	s->upbase, s->cols, s->rows,
	237	src_width, dest_width, 0,
	238	s->invalidate,
	239	fn, s->pallette,
	240	&first, &last);
	241	if (first >= 0) {
	242	dpy_update(s->ds, 0, first, s->cols, last - first + 1);
bdd5003a	243	}
bdd5003a	244	s->invalidate = 0;
bdd5003a PB	245	}
bdd5003a PB	246
95219897	247	static void pl110_invalidate_display(void * opaque)
bdd5003a PB	248	{
	249	pl110_state s = (pl110_state )opaque;
	250	s->invalidate = 1;
bfdb3629 BS	251	if (pl110_enabled(s)) {
	252	qemu_console_resize(s->ds, s->cols, s->rows);
	253	}
bdd5003a PB	254	}
	255
	256	static void pl110_update_pallette(pl110_state *s, int n)
	257	{
	258	int i;
	259	uint32_t raw;
	260	unsigned int r, g, b;
	261
	262	raw = s->raw_pallette[n];
	263	n <<= 1;
	264	for (i = 0; i < 2; i++) {
	265	r = (raw & 0x1f) << 3;
	266	raw >>= 5;
	267	g = (raw & 0x1f) << 3;
	268	raw >>= 5;
	269	b = (raw & 0x1f) << 3;
	270	/* The I bit is ignored. */
	271	raw >>= 6;
0e1f5a0c	272	switch (ds_get_bits_per_pixel(s->ds)) {
bdd5003a PB	273	case 8:
	274	s->pallette[n] = rgb_to_pixel8(r, g, b);
	275	break;
	276	case 15:
	277	s->pallette[n] = rgb_to_pixel15(r, g, b);
	278	break;
	279	case 16:
	280	s->pallette[n] = rgb_to_pixel16(r, g, b);
	281	break;
	282	case 24:
	283	case 32:
	284	s->pallette[n] = rgb_to_pixel32(r, g, b);
	285	break;
	286	}
	287	n++;
	288	}
	289	}
	290
	291	static void pl110_resize(pl110_state *s, int width, int height)
	292	{
	293	if (width != s->cols \|\| height != s->rows) {
	294	if (pl110_enabled(s)) {
3023f332	295	qemu_console_resize(s->ds, width, height);
bdd5003a PB	296	}
	297	}
	298	s->cols = width;
	299	s->rows = height;
	300	}
	301
	302	/* Update interrupts. */
	303	static void pl110_update(pl110_state *s)
	304	{
	305	/* TODO: Implement interrupts. */
	306	}
	307
1a6b31ce AK	308	static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
1a6b31ce AK	309	unsigned size)
bdd5003a PB	310	{
	311	pl110_state s = (pl110_state )opaque;
	312
bdd5003a	313	if (offset >= 0xfe0 && offset < 0x1000) {
4fbf5556	314	return idregs[s->version][(offset - 0xfe0) >> 2];
bdd5003a PB	315	}
	316	if (offset >= 0x200 && offset < 0x400) {
	317	return s->raw_pallette[(offset - 0x200) >> 2];
	318	}
	319	switch (offset >> 2) {
	320	case 0: /* LCDTiming0 */
	321	return s->timing[0];
	322	case 1: /* LCDTiming1 */
	323	return s->timing[1];
	324	case 2: /* LCDTiming2 */
	325	return s->timing[2];
	326	case 3: /* LCDTiming3 */
	327	return s->timing[3];
	328	case 4: /* LCDUPBASE */
	329	return s->upbase;
	330	case 5: /* LCDLPBASE */
	331	return s->lpbase;
	332	case 6: /* LCDIMSC */
4fbf5556 PM	333	if (s->version != PL110) {
	334	return s->cr;
	335	}
bdd5003a PB	336	return s->int_mask;
bdd5003a PB	337	case 7: /* LCDControl */
4fbf5556 PM	338	if (s->version != PL110) {
	339	return s->int_mask;
	340	}
bdd5003a PB	341	return s->cr;
	342	case 8: /* LCDRIS */
	343	return s->int_status;
	344	case 9: /* LCDMIS */
	345	return s->int_status & s->int_mask;
	346	case 11: /* LCDUPCURR */
	347	/* TODO: Implement vertical refresh. */
	348	return s->upbase;
	349	case 12: /* LCDLPCURR */
	350	return s->lpbase;
	351	default:
2ac71179	352	hw_error("pl110_read: Bad offset %x\n", (int)offset);
bdd5003a PB	353	return 0;
	354	}
	355	}
	356
c227f099	357	static void pl110_write(void *opaque, target_phys_addr_t offset,
1a6b31ce	358	uint64_t val, unsigned size)
bdd5003a PB	359	{
	360	pl110_state s = (pl110_state )opaque;
	361	int n;
	362
	363	/* For simplicity invalidate the display whenever a control register
66a0a2cb	364	is written to. */
bdd5003a	365	s->invalidate = 1;
bdd5003a PB	366	if (offset >= 0x200 && offset < 0x400) {
	367	/* Pallette. */
	368	n = (offset - 0x200) >> 2;
	369	s->raw_pallette[(offset - 0x200) >> 2] = val;
	370	pl110_update_pallette(s, n);
e10c2bfb	371	return;
bdd5003a PB	372	}
	373	switch (offset >> 2) {
	374	case 0: /* LCDTiming0 */
	375	s->timing[0] = val;
	376	n = ((val & 0xfc) + 4) * 4;
	377	pl110_resize(s, n, s->rows);
	378	break;
	379	case 1: /* LCDTiming1 */
	380	s->timing[1] = val;
	381	n = (val & 0x3ff) + 1;
	382	pl110_resize(s, s->cols, n);
	383	break;
	384	case 2: /* LCDTiming2 */
	385	s->timing[2] = val;
	386	break;
	387	case 3: /* LCDTiming3 */
	388	s->timing[3] = val;
	389	break;
	390	case 4: /* LCDUPBASE */
	391	s->upbase = val;
	392	break;
	393	case 5: /* LCDLPBASE */
	394	s->lpbase = val;
	395	break;
	396	case 6: /* LCDIMSC */
4fbf5556	397	if (s->version != PL110) {
cdbdb648	398	goto control;
4fbf5556	399	}
cdbdb648	400	imsc:
bdd5003a PB	401	s->int_mask = val;
	402	pl110_update(s);
	403	break;
	404	case 7: /* LCDControl */
4fbf5556	405	if (s->version != PL110) {
cdbdb648	406	goto imsc;
4fbf5556	407	}
cdbdb648	408	control:
bdd5003a PB	409	s->cr = val;
	410	s->bpp = (val >> 1) & 7;
	411	if (pl110_enabled(s)) {
3023f332	412	qemu_console_resize(s->ds, s->cols, s->rows);
bdd5003a PB	413	}
	414	break;
	415	case 10: /* LCDICR */
	416	s->int_status &= ~val;
	417	pl110_update(s);
	418	break;
	419	default:
2ac71179	420	hw_error("pl110_write: Bad offset %x\n", (int)offset);
bdd5003a PB	421	}
	422	}
	423
1a6b31ce AK	424	static const MemoryRegionOps pl110_ops = {
	425	.read = pl110_read,
	426	.write = pl110_write,
	427	.endianness = DEVICE_NATIVE_ENDIAN,
bdd5003a PB	428	};
bdd5003a PB	429
242ea2c6 PM	430	static void pl110_mux_ctrl_set(void *opaque, int line, int level)
	431	{
	432	pl110_state s = (pl110_state )opaque;
	433	s->mux_ctrl = level;
	434	}
	435
128939a9 PM	436	static int vmstate_pl110_post_load(void *opaque, int version_id)
	437	{
	438	pl110_state *s = opaque;
	439	/* Make sure we redraw, and at the right size */
	440	pl110_invalidate_display(s);
	441	return 0;
	442	}
	443
81a322d4	444	static int pl110_init(SysBusDevice *dev)
bdd5003a	445	{
2e9bdce5	446	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
bdd5003a	447
1a6b31ce	448	memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
750ecd44	449	sysbus_init_mmio(dev, &s->iomem);
2e9bdce5	450	sysbus_init_irq(dev, &s->irq);
242ea2c6	451	qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
3023f332 AL	452	s->ds = graphic_console_init(pl110_update_display,
	453	pl110_invalidate_display,
	454	NULL, NULL, s);
81a322d4	455	return 0;
bdd5003a	456	}
2e9bdce5	457
81a322d4	458	static int pl110_versatile_init(SysBusDevice *dev)
2e9bdce5 PB	459	{
2e9bdce5 PB	460	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
4fbf5556 PM	461	s->version = PL110_VERSATILE;
	462	return pl110_init(dev);
	463	}
	464
	465	static int pl111_init(SysBusDevice *dev)
	466	{
	467	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
	468	s->version = PL111;
81a322d4	469	return pl110_init(dev);
2e9bdce5 PB	470	}
2e9bdce5 PB	471
999e12bb AL	472	static void pl110_class_init(ObjectClass klass, void data)
999e12bb AL	473	{
39bffca2	474	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	475	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	476
	477	k->init = pl110_init;
39bffca2 AL	478	dc->no_user = 1;
39bffca2 AL	479	dc->vmsd = &vmstate_pl110;
999e12bb AL	480	}
999e12bb AL	481
39bffca2 AL	482	static TypeInfo pl110_info = {
	483	.name = "pl110",
	484	.parent = TYPE_SYS_BUS_DEVICE,
	485	.instance_size = sizeof(pl110_state),
	486	.class_init = pl110_class_init,
8c60d065 PM	487	};
8c60d065 PM	488
999e12bb AL	489	static void pl110_versatile_class_init(ObjectClass klass, void data)
999e12bb AL	490	{
39bffca2	491	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	492	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	493
	494	k->init = pl110_versatile_init;
39bffca2 AL	495	dc->no_user = 1;
39bffca2 AL	496	dc->vmsd = &vmstate_pl110;
999e12bb AL	497	}
999e12bb AL	498
39bffca2 AL	499	static TypeInfo pl110_versatile_info = {
	500	.name = "pl110_versatile",
	501	.parent = TYPE_SYS_BUS_DEVICE,
	502	.instance_size = sizeof(pl110_state),
	503	.class_init = pl110_versatile_class_init,
8c60d065 PM	504	};
8c60d065 PM	505
999e12bb AL	506	static void pl111_class_init(ObjectClass klass, void data)
999e12bb AL	507	{
39bffca2	508	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	509	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	510
	511	k->init = pl111_init;
39bffca2 AL	512	dc->no_user = 1;
39bffca2 AL	513	dc->vmsd = &vmstate_pl110;
999e12bb AL	514	}
999e12bb AL	515
39bffca2 AL	516	static TypeInfo pl111_info = {
	517	.name = "pl111",
	518	.parent = TYPE_SYS_BUS_DEVICE,
	519	.instance_size = sizeof(pl110_state),
	520	.class_init = pl111_class_init,
4fbf5556 PM	521	};
4fbf5556 PM	522
83f7d43a	523	static void pl110_register_types(void)
2e9bdce5	524	{
39bffca2 AL	525	type_register_static(&pl110_info);
	526	type_register_static(&pl110_versatile_info);
	527	type_register_static(&pl111_info);
2e9bdce5 PB	528	}
2e9bdce5 PB	529
83f7d43a	530	type_init(pl110_register_types)