[qemu.git] / hw / pci.h

#ifndef QEMU_PCI_H
#define QEMU_PCI_H

#include "qemu-common.h"

#include "qdev.h"

/* PCI includes legacy ISA access.  */
#include "isa.h"

/* PCI bus */

extern target_phys_addr_t pci_mem_base;

#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)         ((devfn) & 0x07)

/* Class, Vendor and Device IDs from Linux's pci_ids.h */
#include "pci_ids.h"

/* QEMU-specific Vendor and Device ID definitions */

/* IBM (0x1014) */
#define PCI_DEVICE_ID_IBM_440GX          0x027f
#define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff

/* Hitachi (0x1054) */
#define PCI_VENDOR_ID_HITACHI            0x1054
#define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e

/* Apple (0x106b) */
#define PCI_DEVICE_ID_APPLE_343S1201     0x0010
#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
#define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f

/* Realtek (0x10ec) */
#define PCI_DEVICE_ID_REALTEK_8029       0x8029

/* Xilinx (0x10ee) */
#define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300

/* Marvell (0x11ab) */
#define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620

/* QEMU/Bochs VGA (0x1234) */
#define PCI_VENDOR_ID_QEMU               0x1234
#define PCI_DEVICE_ID_QEMU_VGA           0x1111

/* VMWare (0x15ad) */
#define PCI_VENDOR_ID_VMWARE             0x15ad
#define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
#define PCI_DEVICE_ID_VMWARE_NET         0x0720
#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
#define PCI_DEVICE_ID_VMWARE_IDE         0x1729

/* Intel (0x8086) */
#define PCI_DEVICE_ID_INTEL_82551IT      0x1209
#define PCI_DEVICE_ID_INTEL_82557        0x1229

/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
#define PCI_SUBDEVICE_ID_QEMU            0x1100

#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
#define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003

typedef uint64_t pcibus_t;
#define FMT_PCIBUS                      PRIx64

typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
                                uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
                                   uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
                                pcibus_t addr, pcibus_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);

typedef struct PCIIORegion {
    pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
    pcibus_t size;
    pcibus_t filtered_size;
    uint8_t type;
    PCIMapIORegionFunc *map_func;
} PCIIORegion;

#define PCI_ROM_SLOT 6
#define PCI_NUM_REGIONS 7

/* Declarations from linux/pci_regs.h */
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define  PCI_COMMAND_MASTER	0x4	/* Enable bus master */
#define PCI_STATUS              0x06    /* 16 bits */
#define  PCI_STATUS_INTERRUPT   0x08
#define PCI_REVISION_ID         0x08    /* 8 bits  */
#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL		0
#define  PCI_HEADER_TYPE_BRIDGE		1
#define  PCI_HEADER_TYPE_CARDBUS	2
#define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
#define  PCI_BASE_ADDRESS_SPACE_IO	0x01
#define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
#define PCI_IO_LIMIT            0x1d
#define  PCI_IO_RANGE_TYPE_32	0x01
#define  PCI_IO_RANGE_MASK      (~0x0fUL)
#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
#define PCI_MEMORY_LIMIT        0x22
#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT   0x26
#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
#define  PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32	0x2c
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
#define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
#define  PCI_ROM_ADDRESS_ENABLE	0x01
#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16    0x32
#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_BRIDGE_CONTROL      0x3e
#define PCI_MAX_LAT		0x3f	/* 8 bits */

/* Capability lists */
#define PCI_CAP_LIST_ID		0	/* Capability ID */
#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */

#define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
#define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
#define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */

/* Bits in the PCI Status Register (PCI 2.3 spec) */
#define PCI_STATUS_RESERVED1	0x007
#define PCI_STATUS_INT_STATUS	0x008
#define PCI_STATUS_CAP_LIST	0x010
#define PCI_STATUS_66MHZ	0x020
#define PCI_STATUS_RESERVED2	0x040
#define PCI_STATUS_FAST_BACK	0x080
#define PCI_STATUS_DEVSEL	0x600

#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
                PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
                PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)

#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)

/* Bits in the PCI Command Register (PCI 2.3 spec) */
#define PCI_COMMAND_RESERVED	0xf800

#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)

/* Size of the standard PCI config header */
#define PCI_CONFIG_HEADER_SIZE 0x40
/* Size of the standard PCI config space */
#define PCI_CONFIG_SPACE_SIZE 0x100
/* Size of the standart PCIe config space: 4KB */
#define PCIE_CONFIG_SPACE_SIZE  0x1000

#define PCI_NUM_PINS 4 /* A-D */

/* Bits in cap_present field. */
enum {
    QEMU_PCI_CAP_MSIX = 0x1,
    QEMU_PCI_CAP_EXPRESS = 0x2,
};

struct PCIDevice {
    DeviceState qdev;
    /* PCI config space */
    uint8_t *config;

    /* Used to enable config checks on load. Note that writeable bits are
     * never checked even if set in cmask. */
    uint8_t *cmask;

    /* Used to implement R/W bytes */
    uint8_t *wmask;

    /* Used to allocate config space for capabilities. */
    uint8_t *used;

    /* the following fields are read only */
    PCIBus *bus;
    uint32_t devfn;
    char name[64];
    PCIIORegion io_regions[PCI_NUM_REGIONS];

    /* do not access the following fields */
    PCIConfigReadFunc *config_read;
    PCIConfigWriteFunc *config_write;

    /* IRQ objects for the INTA-INTD pins.  */
    qemu_irq *irq;

    /* Current IRQ levels.  Used internally by the generic PCI code.  */
    uint8_t irq_state;

    /* Capability bits */
    uint32_t cap_present;

    /* Offset of MSI-X capability in config space */
    uint8_t msix_cap;

    /* MSI-X entries */
    int msix_entries_nr;

    /* Space to store MSIX table */
    uint8_t *msix_table_page;
    /* MMIO index used to map MSIX table and pending bit entries. */
    int msix_mmio_index;
    /* Reference-count for entries actually in use by driver. */
    unsigned *msix_entry_used;
    /* Region including the MSI-X table */
    uint32_t msix_bar_size;
    /* Version id needed for VMState */
    int32_t version_id;

    /* Location of option rom */
    char *romfile;
    ram_addr_t rom_offset;
};

PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                               int instance_size, int devfn,
                               PCIConfigReadFunc *config_read,
                               PCIConfigWriteFunc *config_write);

void pci_register_bar(PCIDevice *pci_dev, int region_num,
                            pcibus_t size, int type,
                            PCIMapIORegionFunc *map_func);

int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);

void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);

void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);

uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);


uint32_t pci_default_read_config(PCIDevice *d,
                                 uint32_t address, int len);
void pci_default_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);

typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
                         const char *name, int devfn_min);
PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                  void *irq_opaque, int nirq);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                         void *irq_opaque, int devfn_min, int nirq);

PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
                        const char *default_devaddr);
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
                               const char *default_devaddr);
int pci_bus_num(PCIBus *s);
void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
PCIBus *pci_find_root_bus(int domain);
PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);

int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
                     unsigned *slotp);

void pci_info(Monitor *mon);
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
                        pci_map_irq_fn map_irq, const char *name);
PCIDevice *pci_bridge_get_device(PCIBus *bus);

static inline void
pci_set_byte(uint8_t *config, uint8_t val)
{
    *config = val;
}

static inline uint8_t
pci_get_byte(uint8_t *config)
{
    return *config;
}

static inline void
pci_set_word(uint8_t *config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)config, val);
}

static inline uint16_t
pci_get_word(uint8_t *config)
{
    return le16_to_cpupu((uint16_t *)config);
}

static inline void
pci_set_long(uint8_t *config, uint32_t val)
{
    cpu_to_le32wu((uint32_t *)config, val);
}

static inline uint32_t
pci_get_long(uint8_t *config)
{
    return le32_to_cpupu((uint32_t *)config);
}

static inline void
pci_set_quad(uint8_t *config, uint64_t val)
{
    cpu_to_le64w((uint64_t *)config, val);
}

static inline uint64_t
pci_get_quad(uint8_t *config)
{
    return le64_to_cpup((uint64_t *)config);
}

static inline void
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
{
    pci_set_word(&pci_config[PCI_VENDOR_ID], val);
}

static inline void
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
{
    pci_set_word(&pci_config[PCI_DEVICE_ID], val);
}

static inline void
pci_config_set_class(uint8_t *pci_config, uint16_t val)
{
    pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
}

typedef int (*pci_qdev_initfn)(PCIDevice *dev);
typedef struct {
    DeviceInfo qdev;
    pci_qdev_initfn init;
    PCIUnregisterFunc *exit;
    PCIConfigReadFunc *config_read;
    PCIConfigWriteFunc *config_write;

    /* pci config header type */
    uint8_t header_type;

    /* pcie stuff */
    int is_express;   /* is this device pci express? */

    /* rom bar */
    const char *romfile;
} PCIDeviceInfo;

void pci_qdev_register(PCIDeviceInfo *info);
void pci_qdev_register_many(PCIDeviceInfo *info);

PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);

static inline int pci_is_express(PCIDevice *d)
{
    return d->cap_present & QEMU_PCI_CAP_EXPRESS;
}

static inline uint32_t pci_config_size(PCIDevice *d)
{
    return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}

/* These are not pci specific. Should move into a separate header.
 * Only pci.c uses them, so keep them here for now.
 */

/* Get last byte of a range from offset + length.
 * Undefined for ranges that wrap around 0. */
static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
{
    return offset + len - 1;
}

/* Check whether a given range covers a given byte. */
static inline int range_covers_byte(uint64_t offset, uint64_t len,
                                    uint64_t byte)
{
    return offset <= byte && byte <= range_get_last(offset, len);
}

/* Check whether 2 given ranges overlap.
 * Undefined if ranges that wrap around 0. */
static inline int ranges_overlap(uint64_t first1, uint64_t len1,
                                 uint64_t first2, uint64_t len2)
{
    uint64_t last1 = range_get_last(first1, len1);
    uint64_t last2 = range_get_last(first2, len2);

    return !(last2 < first1 || last1 < first2);
}

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef QEMU_PCI_H
	2	#define QEMU_PCI_H
	3
376253ec AL	4	#include "qemu-common.h"
376253ec AL	5
6b1b92d3 PB	6	#include "qdev.h"
6b1b92d3 PB	7
87ecb68b PB	8	/* PCI includes legacy ISA access. */
	9	#include "isa.h"
	10
	11	/* PCI bus */
	12
c227f099	13	extern target_phys_addr_t pci_mem_base;
87ecb68b	14
3ae80618 AL	15	#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) \| ((func) & 0x07))
	16	#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
	17	#define PCI_FUNC(devfn) ((devfn) & 0x07)
	18
a770dc7e AL	19	/* Class, Vendor and Device IDs from Linux's pci_ids.h */
a770dc7e AL	20	#include "pci_ids.h"
173a543b	21
a770dc7e	22	/* QEMU-specific Vendor and Device ID definitions */
6f338c34	23
a770dc7e AL	24	/* IBM (0x1014) */
a770dc7e AL	25	#define PCI_DEVICE_ID_IBM_440GX 0x027f
4ebcf884	26	#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
deb54399	27
a770dc7e	28	/* Hitachi (0x1054) */
deb54399	29	#define PCI_VENDOR_ID_HITACHI 0x1054
a770dc7e	30	#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
deb54399	31
a770dc7e	32	/* Apple (0x106b) */
4ebcf884 BS	33	#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
	34	#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
	35	#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
4ebcf884	36	#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
a770dc7e	37	#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
deb54399	38
a770dc7e AL	39	/* Realtek (0x10ec) */
a770dc7e AL	40	#define PCI_DEVICE_ID_REALTEK_8029 0x8029
deb54399	41
a770dc7e AL	42	/* Xilinx (0x10ee) */
a770dc7e AL	43	#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
deb54399	44
a770dc7e AL	45	/* Marvell (0x11ab) */
a770dc7e AL	46	#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
deb54399	47
a770dc7e	48	/* QEMU/Bochs VGA (0x1234) */
4ebcf884 BS	49	#define PCI_VENDOR_ID_QEMU 0x1234
	50	#define PCI_DEVICE_ID_QEMU_VGA 0x1111
	51
a770dc7e	52	/* VMWare (0x15ad) */
deb54399 AL	53	#define PCI_VENDOR_ID_VMWARE 0x15ad
	54	#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
	55	#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
	56	#define PCI_DEVICE_ID_VMWARE_NET 0x0720
	57	#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
	58	#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
	59
cef3017c	60	/* Intel (0x8086) */
a770dc7e	61	#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
d6fd1e66	62	#define PCI_DEVICE_ID_INTEL_82557 0x1229
74c62ba8	63
deb54399	64	/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
d350d97d AL	65	#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
	66	#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
	67	#define PCI_SUBDEVICE_ID_QEMU 0x1100
	68
	69	#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
	70	#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
	71	#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
14d50bef	72	#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
d350d97d	73
4f8589e1 IY	74	typedef uint64_t pcibus_t;
4f8589e1 IY	75	#define FMT_PCIBUS PRIx64
6e355d90	76
87ecb68b PB	77	typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
	78	uint32_t address, uint32_t data, int len);
	79	typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
	80	uint32_t address, int len);
	81	typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
6e355d90	82	pcibus_t addr, pcibus_t size, int type);
5851e08c	83	typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
87ecb68b	84
87ecb68b	85	typedef struct PCIIORegion {
6e355d90 IY	86	pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
	87	#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
	88	pcibus_t size;
a0c7a97e	89	pcibus_t filtered_size;
87ecb68b PB	90	uint8_t type;
	91	PCIMapIORegionFunc *map_func;
	92	} PCIIORegion;
	93
	94	#define PCI_ROM_SLOT 6
	95	#define PCI_NUM_REGIONS 7
	96
cef3017c	97	/* Declarations from linux/pci_regs.h */
87ecb68b PB	98	#define PCI_VENDOR_ID 0x00 /* 16 bits */
	99	#define PCI_DEVICE_ID 0x02 /* 16 bits */
	100	#define PCI_COMMAND 0x04 /* 16 bits */
	101	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	102	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
b7ee1603	103	#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
cef3017c	104	#define PCI_STATUS 0x06 /* 16 bits */
f9bf77dd	105	#define PCI_STATUS_INTERRUPT 0x08
cef3017c	106	#define PCI_REVISION_ID 0x08 /* 8 bits */
bd4b65ee	107	#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
87ecb68b	108	#define PCI_CLASS_DEVICE 0x0a /* Device class */
b7ee1603 MT	109	#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
b7ee1603 MT	110	#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
cef3017c	111	#define PCI_HEADER_TYPE 0x0e /* 8 bits */
6407f373 IY	112	#define PCI_HEADER_TYPE_NORMAL 0
	113	#define PCI_HEADER_TYPE_BRIDGE 1
	114	#define PCI_HEADER_TYPE_CARDBUS 2
	115	#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
b7ee1603	116	#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
0392a017 IY	117	#define PCI_BASE_ADDRESS_SPACE_IO 0x01
0392a017 IY	118	#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
14421258	119	#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
0392a017	120	#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
b7ee1603 MT	121	#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
b7ee1603 MT	122	#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
e822a52a	123	#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
fb231628 IY	124	#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
fb231628 IY	125	#define PCI_IO_LIMIT 0x1d
a0c7a97e	126	#define PCI_IO_RANGE_TYPE_32 0x01
fb231628	127	#define PCI_IO_RANGE_MASK (~0x0fUL)
b7ee1603	128	#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
fb231628 IY	129	#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
	130	#define PCI_MEMORY_LIMIT 0x22
	131	#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
	132	#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
	133	#define PCI_PREF_MEMORY_LIMIT 0x26
	134	#define PCI_PREF_RANGE_MASK (~0x0fUL)
d46636b8	135	#define PCI_PREF_RANGE_TYPE_64 0x01
fb231628	136	#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
a0c7a97e	137	#define PCI_PREF_LIMIT_UPPER32 0x2c
cef3017c AL	138	#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
cef3017c AL	139	#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
5330de09 MT	140	#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
5330de09 MT	141	#define PCI_ROM_ADDRESS_ENABLE 0x01
fb231628 IY	142	#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
fb231628 IY	143	#define PCI_IO_LIMIT_UPPER16 0x32
b7ee1603	144	#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
b3b11697	145	#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
87ecb68b PB	146	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
	147	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
	148	#define PCI_MIN_GNT 0x3e /* 8 bits */
fb231628	149	#define PCI_BRIDGE_CONTROL 0x3e
87ecb68b PB	150	#define PCI_MAX_LAT 0x3f /* 8 bits */
87ecb68b PB	151
6f4cbd39 MT	152	/* Capability lists */
	153	#define PCI_CAP_LIST_ID 0 /* Capability ID */
	154	#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
	155
cef3017c AL	156	#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
	157	#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
	158	#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
	159
8098ed41 AJ	160	/* Bits in the PCI Status Register (PCI 2.3 spec) */
	161	#define PCI_STATUS_RESERVED1 0x007
	162	#define PCI_STATUS_INT_STATUS 0x008
6f4cbd39	163	#define PCI_STATUS_CAP_LIST 0x010
8098ed41 AJ	164	#define PCI_STATUS_66MHZ 0x020
	165	#define PCI_STATUS_RESERVED2 0x040
	166	#define PCI_STATUS_FAST_BACK 0x080
	167	#define PCI_STATUS_DEVSEL 0x600
	168
	169	#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 \| \
	170	PCI_STATUS_INT_STATUS \| PCI_STATUS_CAPABILITIES \| \
	171	PCI_STATUS_66MHZ \| PCI_STATUS_RESERVED2 \| PCI_STATUS_FAST_BACK)
	172
	173	#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
	174
475dc65f AJ	175	/* Bits in the PCI Command Register (PCI 2.3 spec) */
	176	#define PCI_COMMAND_RESERVED 0xf800
	177
	178	#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
	179
b7ee1603 MT	180	/* Size of the standard PCI config header */
	181	#define PCI_CONFIG_HEADER_SIZE 0x40
	182	/* Size of the standard PCI config space */
	183	#define PCI_CONFIG_SPACE_SIZE 0x100
a9f49946 IY	184	/* Size of the standart PCIe config space: 4KB */
a9f49946 IY	185	#define PCIE_CONFIG_SPACE_SIZE 0x1000
b7ee1603	186
e369cad7 IY	187	#define PCI_NUM_PINS 4 /* A-D */
e369cad7 IY	188
02eb84d0 MT	189	/* Bits in cap_present field. */
	190	enum {
	191	QEMU_PCI_CAP_MSIX = 0x1,
a9f49946	192	QEMU_PCI_CAP_EXPRESS = 0x2,
02eb84d0 MT	193	};
02eb84d0 MT	194
87ecb68b	195	struct PCIDevice {
6b1b92d3	196	DeviceState qdev;
87ecb68b	197	/* PCI config space */
a9f49946	198	uint8_t *config;
b7ee1603	199
bd4b65ee MT	200	/* Used to enable config checks on load. Note that writeable bits are
bd4b65ee MT	201	* never checked even if set in cmask. */
a9f49946	202	uint8_t *cmask;
bd4b65ee	203
b7ee1603	204	/* Used to implement R/W bytes */
a9f49946	205	uint8_t *wmask;
87ecb68b	206
6f4cbd39	207	/* Used to allocate config space for capabilities. */
a9f49946	208	uint8_t *used;
6f4cbd39	209
87ecb68b PB	210	/* the following fields are read only */
87ecb68b PB	211	PCIBus *bus;
54586bd1	212	uint32_t devfn;
87ecb68b PB	213	char name[64];
	214	PCIIORegion io_regions[PCI_NUM_REGIONS];
	215
	216	/* do not access the following fields */
	217	PCIConfigReadFunc *config_read;
	218	PCIConfigWriteFunc *config_write;
87ecb68b PB	219
	220	/* IRQ objects for the INTA-INTD pins. */
	221	qemu_irq *irq;
	222
	223	/* Current IRQ levels. Used internally by the generic PCI code. */
d036bb21	224	uint8_t irq_state;
02eb84d0 MT	225
	226	/* Capability bits */
	227	uint32_t cap_present;
	228
	229	/* Offset of MSI-X capability in config space */
	230	uint8_t msix_cap;
	231
	232	/* MSI-X entries */
	233	int msix_entries_nr;
	234
	235	/* Space to store MSIX table */
	236	uint8_t *msix_table_page;
	237	/* MMIO index used to map MSIX table and pending bit entries. */
	238	int msix_mmio_index;
	239	/* Reference-count for entries actually in use by driver. */
	240	unsigned *msix_entry_used;
	241	/* Region including the MSI-X table */
	242	uint32_t msix_bar_size;
f16c4abf JQ	243	/* Version id needed for VMState */
f16c4abf JQ	244	int32_t version_id;
c2039bd0 AL	245
c2039bd0 AL	246	/* Location of option rom */
8c52c8f3	247	char *romfile;
c2039bd0	248	ram_addr_t rom_offset;
87ecb68b PB	249	};
	250
	251	PCIDevice pci_register_device(PCIBus bus, const char *name,
	252	int instance_size, int devfn,
	253	PCIConfigReadFunc *config_read,
	254	PCIConfigWriteFunc *config_write);
	255
28c2c264	256	void pci_register_bar(PCIDevice *pci_dev, int region_num,
6e355d90	257	pcibus_t size, int type,
87ecb68b PB	258	PCIMapIORegionFunc *map_func);
87ecb68b PB	259
6f4cbd39 MT	260	int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
	261
	262	void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
	263
	264	void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
	265
	266	uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
	267
	268
87ecb68b PB	269	uint32_t pci_default_read_config(PCIDevice *d,
	270	uint32_t address, int len);
	271	void pci_default_write_config(PCIDevice *d,
	272	uint32_t address, uint32_t val, int len);
	273	void pci_device_save(PCIDevice s, QEMUFile f);
	274	int pci_device_load(PCIDevice s, QEMUFile f);
	275
5d4e84c8	276	typedef void (pci_set_irq_fn)(void opaque, int irq_num, int level);
87ecb68b	277	typedef int (pci_map_irq_fn)(PCIDevice pci_dev, int irq_num);
ee995ffb	278	typedef int (pci_hotplug_fn)(PCIDevice pci_dev, int state);
21eea4b3 GH	279	void pci_bus_new_inplace(PCIBus bus, DeviceState parent,
	280	const char *name, int devfn_min);
	281	PCIBus pci_bus_new(DeviceState parent, const char *name, int devfn_min);
	282	void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	283	void *irq_opaque, int nirq);
ee995ffb	284	void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
02e2da45 PB	285	PCIBus pci_register_bus(DeviceState parent, const char *name,
02e2da45 PB	286	pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
5d4e84c8	287	void *irq_opaque, int devfn_min, int nirq);
87ecb68b	288
5607c388 MA	289	PCIDevice pci_nic_init(NICInfo nd, const char *default_model,
5607c388 MA	290	const char *default_devaddr);
07caea31 MA	291	PCIDevice pci_nic_init_nofail(NICInfo nd, const char *default_model,
07caea31 MA	292	const char *default_devaddr);
87ecb68b	293	int pci_bus_num(PCIBus *s);
e822a52a	294	void pci_for_each_device(PCIBus bus, int bus_num, void (fn)(PCIBus bus, PCIDevice d));
c469e1dd	295	PCIBus *pci_find_root_bus(int domain);
e822a52a IY	296	PCIBus pci_find_bus(PCIBus bus, int bus_num);
e822a52a IY	297	PCIDevice pci_find_device(PCIBus bus, int bus_num, int slot, int function);
49bd1458	298	PCIBus pci_get_bus_devfn(int devfnp, const char *devaddr);
87ecb68b	299
e9283f8b JK	300	int pci_read_devaddr(Monitor mon, const char addr, int domp, int busp,
e9283f8b JK	301	unsigned *slotp);
880345c4	302
376253ec	303	void pci_info(Monitor *mon);
480b9f24	304	PCIBus pci_bridge_init(PCIBus bus, int devfn, uint16_t vid, uint16_t did,
87ecb68b	305	pci_map_irq_fn map_irq, const char *name);
d6318738	306	PCIDevice pci_bridge_get_device(PCIBus bus);
87ecb68b	307
64d50b8b MT	308	static inline void
	309	pci_set_byte(uint8_t *config, uint8_t val)
	310	{
	311	*config = val;
	312	}
	313
	314	static inline uint8_t
	315	pci_get_byte(uint8_t *config)
	316	{
	317	return *config;
	318	}
	319
14e12559 MT	320	static inline void
	321	pci_set_word(uint8_t *config, uint16_t val)
	322	{
	323	cpu_to_le16wu((uint16_t *)config, val);
	324	}
	325
	326	static inline uint16_t
	327	pci_get_word(uint8_t *config)
	328	{
	329	return le16_to_cpupu((uint16_t *)config);
	330	}
	331
	332	static inline void
	333	pci_set_long(uint8_t *config, uint32_t val)
	334	{
	335	cpu_to_le32wu((uint32_t *)config, val);
	336	}
	337
	338	static inline uint32_t
	339	pci_get_long(uint8_t *config)
	340	{
	341	return le32_to_cpupu((uint32_t *)config);
	342	}
	343
fb5ce7d2 IY	344	static inline void
	345	pci_set_quad(uint8_t *config, uint64_t val)
	346	{
	347	cpu_to_le64w((uint64_t *)config, val);
	348	}
	349
	350	static inline uint64_t
	351	pci_get_quad(uint8_t *config)
	352	{
	353	return le64_to_cpup((uint64_t *)config);
	354	}
	355
deb54399 AL	356	static inline void
	357	pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
	358	{
14e12559	359	pci_set_word(&pci_config[PCI_VENDOR_ID], val);
deb54399 AL	360	}
	361
	362	static inline void
	363	pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
	364	{
14e12559	365	pci_set_word(&pci_config[PCI_DEVICE_ID], val);
deb54399 AL	366	}
deb54399 AL	367
173a543b BS	368	static inline void
	369	pci_config_set_class(uint8_t *pci_config, uint16_t val)
	370	{
14e12559	371	pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
173a543b BS	372	}
173a543b BS	373
81a322d4	374	typedef int (pci_qdev_initfn)(PCIDevice dev);
0aab0d3a GH	375	typedef struct {
	376	DeviceInfo qdev;
	377	pci_qdev_initfn init;
e3936fa5	378	PCIUnregisterFunc *exit;
0aab0d3a GH	379	PCIConfigReadFunc *config_read;
0aab0d3a GH	380	PCIConfigWriteFunc *config_write;
a9f49946	381
fb231628	382	/* pci config header type */
3c217c14	383	uint8_t header_type;
fb231628	384
a9f49946	385	/* pcie stuff */
3c217c14	386	int is_express; /* is this device pci express? */
8c52c8f3 GH	387
	388	/* rom bar */
	389	const char *romfile;
0aab0d3a GH	390	} PCIDeviceInfo;
	391
	392	void pci_qdev_register(PCIDeviceInfo *info);
	393	void pci_qdev_register_many(PCIDeviceInfo *info);
6b1b92d3	394
499cf102	395	PCIDevice pci_create(PCIBus bus, int devfn, const char *name);
6b1b92d3 PB	396	PCIDevice pci_create_simple(PCIBus bus, int devfn, const char *name);
6b1b92d3 PB	397
a9f49946 IY	398	static inline int pci_is_express(PCIDevice *d)
	399	{
	400	return d->cap_present & QEMU_PCI_CAP_EXPRESS;
	401	}
	402
	403	static inline uint32_t pci_config_size(PCIDevice *d)
	404	{
	405	return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
	406	}
	407
f49db805 IY	408	/* These are not pci specific. Should move into a separate header.
	409	* Only pci.c uses them, so keep them here for now.
	410	*/
	411
	412	/* Get last byte of a range from offset + length.
	413	* Undefined for ranges that wrap around 0. */
	414	static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
	415	{
	416	return offset + len - 1;
	417	}
	418
	419	/* Check whether a given range covers a given byte. */
	420	static inline int range_covers_byte(uint64_t offset, uint64_t len,
	421	uint64_t byte)
	422	{
	423	return offset <= byte && byte <= range_get_last(offset, len);
	424	}
	425
	426	/* Check whether 2 given ranges overlap.
	427	* Undefined if ranges that wrap around 0. */
	428	static inline int ranges_overlap(uint64_t first1, uint64_t len1,
	429	uint64_t first2, uint64_t len2)
	430	{
	431	uint64_t last1 = range_get_last(first1, len1);
	432	uint64_t last2 = range_get_last(first2, len2);
	433
	434	return !(last2 < first1 \|\| last1 < first2);
	435	}
	436
87ecb68b	437	#endif